From 070276a1a3baa9fbfca42555b306e0d9caac8436 Mon Sep 17 00:00:00 2001
From: Kugel Fuhr <98353208+kugelfuhr@users.noreply.github.com>
Date: Tue, 1 Jul 2025 20:19:19 +0200
Subject: [PATCH] Add a better description for CPU_HAS_ZPIND and CPU_HAS_STZ.

---
 doc/ca65.sgml | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/doc/ca65.sgml b/doc/ca65.sgml
index 0f996ff64..63a1be7e9 100644
--- a/doc/ca65.sgml
+++ b/doc/ca65.sgml
@@ -1681,10 +1681,12 @@ either a string or an expression value.
   Checks for the capability to push and pop the X and Y registers.
 
   <tag><tt>CPU_HAS_ZPIND</tt></tag>
-  Checks for the availability of the "zeropage indirect" addressing mode.
+  Checks for the availability of the "zeropage indirect" addressing mode as it
+  is implemented in the 65SC02 CPU.
 
   <tag><tt>CPU_HAS_STZ</tt></tag>
-  Checks for the availability of the "store zero" instruction.
+  Checks for the availability of the "store zero" instruction as it is
+  implemented in the 65SC02 CPU.
 
 </descrip>