diff --git a/doc/ca65.sgml b/doc/ca65.sgml index cb163fecd..90d3aba32 100644 --- a/doc/ca65.sgml +++ b/doc/ca65.sgml @@ -1434,38 +1434,6 @@ constant is defined: CPU_ISET_M740 - - and following. .endif - See also: +The dilemma: +The original design of this feature was made under the assumption, that any +"higher" CPU will support the entire instruction set of the "lower" CPU. For +example: the WDC W65C02 supports all instructions of the 65C02, which again +support all instructions of the 65SC02. Unfortunately this is not true for all +CMOS CPUs - when the 65CE02 was made, some instructions were changed, and a new +addressingmode was added. As a result all CPUS after (and including) 65CE02 +are no more (source code) compatible with all instructions originally introduced +by the 65SC02. + +Because of this, the .CPU function and the ISET* macros were repurposed to +indicate groups of instructions only, ie only the set of instructions +that was added by that particular CPU. In the value returned by .CPU only the +bits will be set, that refer to the groups of instructions that are completely +supported by that CPU. + +The advantage of this is, that the mechanism keeps working for all new CPUs +added. The inevitable disadvantage is that you now have to know exactly which +CPU added which instructions (look for reference). + + + .if (.cpu .bitand CPU_ISET_65SC02) + ; This will be assembled for the W65C02, 65C02, 65SC02, 65816, HUC6820 + lda (c_sp) + .elseif (.cpu .bitand CPU_ISET_65CE02) + ; This will be assembled for the 65CE02, 4510, 45GS02 + ldz #$00 + lda (c_sp),z + .else + ldy #$00 + lda (c_sp),y + .endif + + + See also: , which is a similar mechanism, + but without the problem outlined above. .ISIZE