diff --git a/asminc/cpu.mac b/asminc/cpu.mac
index c66641078..15b16bad5 100644
--- a/asminc/cpu.mac
+++ b/asminc/cpu.mac
@@ -5,13 +5,15 @@ CPU_ISET_6502      = $0002
 CPU_ISET_6502X     = $0004
 CPU_ISET_6502DTV   = $0008
 CPU_ISET_65SC02    = $0010
-CPU_ISET_65C02     = $0020
+CPU_ISET_65C02     = $0020  ; Rockwell extensions
 CPU_ISET_65816     = $0040
 CPU_ISET_SWEET16   = $0080
 CPU_ISET_HUC6280   = $0100
 CPU_ISET_M740      = $0200
 CPU_ISET_4510      = $0400
 CPU_ISET_45GS02    = $0800
+CPU_ISET_W65C02    = $1000  ; WDC extensions
+CPU_ISET_65CE02    = $2000  ; CSG extensions
 
 ; CPU capabilities
 ; make sure to only combine the instruction sets that are 100% compatible
@@ -21,13 +23,16 @@ CPU_6502X          = CPU_ISET_6502X   | CPU_ISET_6502
 CPU_6502DTV        = CPU_ISET_6502DTV | CPU_ISET_6502
 CPU_65SC02         = CPU_ISET_65SC02  | CPU_ISET_6502
 CPU_65C02          = CPU_ISET_65C02   | CPU_ISET_6502 | CPU_ISET_65SC02
-CPU_65816          = CPU_ISET_65816   | CPU_ISET_6502 | CPU_ISET_65SC02
-CPU_SWEET16        = CPU_ISET_SWEET16
+CPU_W65C02         = CPU_ISET_W65C02  | CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02
+
 ; FIXME: CPU_ISET_65SC02 does not apply to the following, because the zp-indirect
 ; addressing was replaced with zp-indirect,z-indexed in 652SCE02
-; NOTE: HUC6280 removes "wai" ($cb) and "stp" ($db) from the 65C02 instruction set
+
 CPU_HUC6280        = CPU_ISET_HUC6280 | CPU_ISET_6502 | CPU_ISET_65C02
-; NOTE: 4510 replaces "wai" ($cb) and "stp" ($db) of the 65C02 instruction set
-CPU_4510           = CPU_ISET_4510    | CPU_ISET_6502 | CPU_ISET_65C02
-CPU_45GS02         = CPU_ISET_45GS02  | CPU_ISET_6502 | CPU_ISET_65C02 | CPU_ISET_4510
+CPU_4510           = CPU_ISET_4510    | CPU_ISET_6502 |                   CPU_ISET_65C02 | CPU_ISET_65CE02
+CPU_45GS02         = CPU_ISET_45GS02  | CPU_ISET_6502 |                   CPU_ISET_65C02 | CPU_ISET_65CE02 | CPU_ISET_4510
 CPU_M740           = CPU_ISET_M740    | CPU_ISET_6502
+CPU_65CE02         = CPU_ISET_65CE02  | CPU_ISET_6502 |                   CPU_ISET_65C02
+
+CPU_65816          = CPU_ISET_65816   | CPU_ISET_6502 | CPU_ISET_65SC02
+CPU_SWEET16        = CPU_ISET_SWEET16
diff --git a/doc/ca65.sgml b/doc/ca65.sgml
index 7b36abec5..b7e8539af 100644
--- a/doc/ca65.sgml
+++ b/doc/ca65.sgml
@@ -156,12 +156,14 @@ Here is a description of all the command line options:
   <item>6502X - NMOS 6502 with all undocumented instructions
   <item>6502DTV - the emulated CPU of the C64DTV device
   <item>65SC02 - first CMOS instruction set (no bit manipulation, no wai/stp)
-  <item>65C02 - full CMOS instruction set (has bit manipulation and wai/stp)
-  <item>65816 - the CPU of the SNES, and the SCPU
-  <item>HuC6280 - the CPU of the PC engine
+  <item>65C02 - CMOS with Rockwell extensions
+  <item>W65C02 - full CMOS instruction set (has bit manipulation and wai/stp)
+  <item>65CE02 - CMOS with CSG extensions
   <item>4510 - the CPU of the Commodore C65
   <item>45GS02 - the CPU of the Commodore MEGA65
+  <item>HuC6280 - the CPU of the PC engine
   <item>M740 - a Microcontroller by Mitsubishi
+  <item>65816 - the CPU of the SNES, and the SCPU
   <item>sweet16 - an interpreter for a pseudo 16 bit CPU
   </itemize>
 
@@ -449,16 +451,24 @@ The assembler accepts
       <tt><ref id=".PSC02" name=".PSC02"></tt> command was given).
 <item>all valid 65C02 mnemonics when in <ref id="65C02-mode" name="65C02 mode"> (after the
       <tt><ref id=".PC02" name=".PC02"></tt> command was given).
-<item>all valid 65816 mnemonics when in <ref id="65816-mode" name="65816 mode"> (after the
-      <tt><ref id=".P816" name=".P816"></tt> command was given).
+<item>all valid W65C02 mnemonics when in <ref id="W65C02-mode" name="W65C02 mode"> (after the
+      <tt><ref id=".PWC02" name=".PWC02"></tt> command was given).
+<item>all valid 65CE02 mnemonics when in <ref id="65CE02-mode" name="65CE02 mode"> (after the
+      <tt><ref id=".PCE02" name=".PCE02"></tt> command was given).
 <item>all valid 4510 mnemonics when in <ref id="4510-mode" name="4510 mode"> (after the
       <tt><ref id=".P4510" name=".P4510"></tt> command was given).
 <item>all valid 45GS02 mnemonics when in <ref id="45GS02-mode" name="45GS02 mode"> (after the
       <tt><ref id=".P45GS02" name=".P45GS02"></tt> command was given).
+<item>all valid HuC6280 mnemonics when in <ref id="HUC6280-mode" name="HuC6280 mode"> (after the
+      <tt><ref id=".P6280" name=".P6280"></tt> command was given).
 <item>all valid M740 mnemonics when in <ref id="M740-mode" name="M740 mode"> (after the
       <tt><ref id=".PM740" name=".PM740"></tt> command was given).
+<item>all valid 65816 mnemonics when in <ref id="65816-mode" name="65816 mode"> (after the
+      <tt><ref id=".P816" name=".P816"></tt> command was given).
 </itemize>
 
+for more details on the various CPUs, see <tt><htmlurl url="cpus.html" name="here"></tt>.
+
 On 6502-derived platforms the <tt/BRK/ instruction has an optional signature
 byte. If omitted, the assembler will only produce only 1 byte.
 
@@ -535,58 +545,24 @@ Supported undocumented instructions:
 
 <sect2>65SC02 mode<label id="65SC02-mode"><p>
 
-65SC02 mode supports all regular 6502 instructions, plus the following:
-
-<tscreen><verb>
-$04  tsb zp
-$0c  tsb abs16
-$12  ora (zp)
-$14  trb zp
-$1a  inc
-$1c  trb abs16
-$32  and (zp)
-$34  bit zp, x
-$3a  dec
-$3c  bit abs16, x
-$52  eor (zp)
-$5a  phy
-$64  stz zp
-$72  adc (zp)
-$74  stz zp, x
-$7a  ply
-$7c  jmp (abs16, x)
-$80  bra rel8
-$89  bit #imm8
-$92  sta (zp)
-$9c  stz abs16
-$9e  stz abs16, x
-$b2  lda (zp)
-$d2  cmp (zp)
-$da  phx
-$f2  sbc (zp)
-$fa  plx
-</verb></tscreen>
+65SC02 mode supports all regular 6502 instructions, plus the original CMOS
+instructions.
 
 
-<sect2>65C02 mode<label id="65C02-mode"><p>
+<sect2>65C02 mode (CMOS with Rockwell extensions)<label id="65C02-mode"><p>
 
-65C02 mode supports all "official" W65C02 opcodes.
+65C02 mode supports all original CMOS instructions, plus the Rockwell (bit
+manipulation instructions) extensions.
 
-The R65C02 adds bit manipulation instructions:
 
-<tscreen><verb>
-smbB zp         set bit in zp location
-rmbB zp         reset bit in zp location
-bbsB zp, rel8   branch if bit is set in zp location
-bbrB zp, rel8   branch if bit is reset in zp location
-</verb></tscreen>
+<sect2>W65C02 mode (CMOS with WDC extensions)<label id="W65C02-mode"><p>
 
-And the W65C02 adds those:
+W65C02 mode supports the Rockwell extensions, plus wai and stp.
 
-<tscreen><verb>
-$cb  wai    wait for interrupt
-$db  stp    wait for reset
-</verb></tscreen>
+
+<sect2>65CE02 mode<label id="65CE02-mode"><p>
+
+All 65CE02 instructions are accepted, plus the Rockwell extensions.
 
 
 <sect2>4510 mode<label id="4510-mode"><p>
@@ -595,14 +571,6 @@ The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX.
 It contains among other functions a slightly modified 65CE02/4502 CPU, to allow
 address mapping for 20 bits of address space (1 megabyte addressable area).
 
-The 4510 mode supports the complete (legal) 65CE02 instruction set, plus these
-three, which were changed/added:
-<tscreen><verb>
-$5c  map             "4-byte NOP reserved for future expansion" on 65CE02
-$cb  asw $1234       wai on W65C02
-$db  phz             stp on W65C02
-</verb></tscreen>
-
 As compared to the description of the CPU in the
 <url url="http://www.zimmers.net/anonftp/pub/cbm/c65/c65manualupdated.txt.gz"
 name="C65 System Specification">
@@ -626,40 +594,9 @@ The 45GS02 is a microcontroller that is the core of the MEGA65.
 It is an extension of the 4510 CPU and adds 32-bit addressing and a 32-bit
 pseudo register Q that is comprised of the four registers A, X, Y, and Z.
 
-<sect2>HUC6280 mode<label id="HUC6280-mode"><p>
+<sect2>HUC6280 mode (CMOS with Hudson extensions)<label id="HUC6280-mode"><p>
 
-The HUC6280 is a superset of the R65C02. It adds some other instructions:
-
-<tscreen><verb>
-$02  sxy
-$03  st0 #{imm}
-$13  st1 #{imm}
-$22  sax
-$23  st2 #{imm}
-$42  say
-$43  tma #{imm}
-$44  bsr {rel}
-$53  tam #{imm}
-$54  csl
-$62  cla
-$73  tii {addr}, {addr}, {addr}
-$82  clx
-$83  tst #{imm}, {zp}
-$82  clx
-$83  tst #{imm}, {zp}
-$93  tst #{imm}, {addr}
-$a3  tst #{imm}, {zp}, x
-$b3  tst #{imm}, {addr}, x
-$c2  cly
-$c3  tdd {addr}, {addr}, {addr}
-$d3  tin {addr}, {addr}, {addr}
-$d4  csh
-$e3  tia {addr}, {addr}, {addr}
-$f3  tai {addr}, {addr}, {addr}
-$f4  set
-</verb></tscreen>
-
-Note that this CPU does not implement <tt>wai</tt> and <tt>stp</tt>.
+The HUC6280 is a superset of 65C02, used in the PC Engine.
 
 
 <sect2>M740 mode<label id="M740-mode"><p>
@@ -699,6 +636,13 @@ or two far addresses whose high byte will be used.
                 mvp     $123456, $789ABC   ; bank $12 to $78
 </verb></tscreen>
 
+also see <ref id="long_jsr_jmp_rts" name="long_jsr_jmp_rts">
+ <ref id=".SMART" name=".SMART">
+ <ref id=".A8" name=".A8">
+ <ref id=".A16" name=".A16">
+ <ref id=".I8" name=".I8">
+ <ref id=".I16" name=".I16">
+
 
 <sect2>sweet16 mode<label id="sweet16-mode"><p>
 
@@ -3423,6 +3367,12 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".CHARMAP" name=".CH
   (see <tt><ref id=".P45GS02" name=".P45GS02"></tt> command).
 
 
+<sect1><tt>.IFP6280</tt><label id=".IFP816"><p>
+
+  Conditional assembly: Check if the assembler is currently in HuC6280 mode
+  (see <tt><ref id=".P6280" name=".P6280"></tt> command).
+
+
 <sect1><tt>.IFP816</tt><label id=".IFP816"><p>
 
   Conditional assembly: Check if the assembler is currently in 65816 mode
@@ -3435,6 +3385,12 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".CHARMAP" name=".CH
   (see <tt><ref id=".PC02" name=".PC02"></tt> command).
 
 
+<sect1><tt>.IFPCE02</tt><label id=".IFPCE02"><p>
+
+  Conditional assembly: Check if the assembler is currently in 65CE02 mode
+  (see <tt><ref id=".PCE02" name=".PCE02"></tt> command).
+
+
 <sect1><tt>.IFPDTV</tt><label id=".IFPDTV"><p>
 
   Conditional assembly: Check if the assembler is currently in 6502DTV mode
@@ -3453,6 +3409,12 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".CHARMAP" name=".CH
   (see <tt><ref id=".PSC02" name=".PSC02"></tt> command).
 
 
+<sect1><tt>.IFPSWEET16</tt><label id=".IFPSWEET16"><p>
+
+  Conditional assembly: Check if the assembler is currently in Sweet16 mode
+  (see <tt><ref id=".PSWEET16" name=".PSWEET16"></tt> command).
+
+
 <sect1><tt>.IFREF</tt><label id=".IFREF"><p>
 
   Conditional assembly: Check if a symbol is referenced. Must be followed
@@ -3476,6 +3438,12 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".CHARMAP" name=".CH
   <tt><ref id=".REFERTO" name=".REFERTO"></tt>
 
 
+<sect1><tt>.IFPWC02</tt><label id=".IFPWC02"><p>
+
+  Conditional assembly: Check if the assembler is currently in 65WC02 mode
+  (see <tt><ref id=".PWC02" name=".PWC02"></tt> command).
+
+
 <sect1><tt>.IMPORT</tt><label id=".IMPORT"><p>
 
   Import a symbol from another module. The command is followed by a comma
@@ -3842,6 +3810,18 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
   <tt><ref id=".P816" name=".P816"></tt>, and
   <tt><ref id=".P4510" name=".P4510"></tt>
 
+
+<sect1><tt>.P6280</tt><label id=".P6280"><p>
+
+  Enable the HuC6280 instruction set. This is a superset of the 65C02 and
+  6502 instruction sets.
+
+  See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PSC02"
+  name=".PSC02"></tt>, <tt><ref id=".PC02" name=".PC02"></tt>,
+  <tt><ref id=".P4510" name=".P4510"></tt>, and
+  <tt><ref id=".P45GS02" name=".P45GS02"></tt>
+
+
 <sect1><tt>.P816</tt><label id=".P816"><p>
 
   Enable the 65816 instruction set. This is a superset of the 65SC02 and
@@ -3852,6 +3832,7 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
   <tt><ref id=".P4510" name=".P4510"></tt>, and
   <tt><ref id=".P45GS02" name=".P45GS02"></tt>
 
+
 <sect1><tt>.PAGELEN, .PAGELENGTH</tt><label id=".PAGELENGTH"><p>
 
   Set the page length for the listing. Must be followed by an integer
@@ -3881,6 +3862,17 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
   <tt><ref id=".P4510" name=".P4510"></tt>, and
   <tt><ref id=".P45GS02" name=".P45GS02"></tt>
 
+<sect1><tt>.PCE02</tt><label id=".PCE02"><p>
+
+  Enable the 65CE02 instructions set. This instruction set includes all
+  6502 and extended 65CE02 instructions.
+
+  See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PSC02"
+  name=".PSC02"></tt>, <tt><ref id=".P816" name=".P816"></tt>,
+  <tt><ref id=".P4510" name=".P4510"></tt>, and
+  <tt><ref id=".P45GS02" name=".P45GS02"></tt>
+
+
 <sect1><tt>.PDTV</tt><label id=".PDTV"><p>
 
   Enable the 6502DTV instruction set. This is a superset of the 6502
@@ -3986,6 +3978,17 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
   <tt><ref id=".P4510" name=".P4510"></tt>, and
   <tt><ref id=".P45GS02" name=".P45GS02"></tt>
 
+
+<sect1><tt>.PSWEET16</tt><label id=".PSWEET16"><p>
+
+  Enable the Sweet16 instructions set.
+
+  See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PC02"
+  name=".PC02"></tt>, <tt><ref id=".P816" name=".P816"></tt>,
+  <tt><ref id=".P4510" name=".P4510"></tt>, and
+  <tt><ref id=".P45GS02" name=".P45GS02"></tt>
+
+
 <sect1><tt>.PUSHCHARMAP</tt><label id=".PUSHCHARMAP"><p>
 
   Push the currently active character mapping onto a stack. The stack has a size of 16
@@ -4034,6 +4037,17 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
   See: <tt><ref id=".POPSEG" name=".POPSEG"></tt>
 
 
+<sect1><tt>.PWC02</tt><label id=".PWC02"><p>
+
+  Enable the W65C02 instructions set. This instruction set includes all
+  6502, 65SC02, 65C02 and two extra instructions (wai and stp)
+
+  See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PSC02"
+  name=".PSC02"></tt>, <tt><ref id=".P816" name=".P816"></tt>,
+  <tt><ref id=".P4510" name=".P4510"></tt>, and
+  <tt><ref id=".P45GS02" name=".P45GS02"></tt>
+
+
 <sect1><tt>.REFERTO, .REFTO</tt><label id=".REFERTO"><p>
 
   Mark a symbol as referenced.
diff --git a/doc/cc65.sgml b/doc/cc65.sgml
index 166c0fad4..734e4eaf4 100644
--- a/doc/cc65.sgml
+++ b/doc/cc65.sgml
@@ -1212,6 +1212,14 @@ The compiler defines several macros at startup:
   given, but can be changed using the <tt/<ref id="option--cpu" name="--cpu">/
   command line option.
 
+  <tag><tt>__CPU_4510__</tt></tag>
+
+  This macro is defined if the code is compiled for a 4510 CPU.
+
+  <tag><tt>__CPU_45GS02__</tt></tag>
+
+  This macro is defined if the code is compiled for a 45GS02 CPU.
+
   <tag><tt>__CPU_6502__</tt></tag>
 
   This macro is defined if the code is compiled for a 6502 CPU.
@@ -1233,6 +1241,10 @@ The compiler defines several macros at startup:
 
   This macro is defined if the code is compiled for a 65C02 CPU.
 
+  <tag><tt>__CPU_65CE02__</tt></tag>
+
+  This macro is defined if the code is compiled for a 65CE02 CPU.
+
   <tag><tt>__CPU_65816__</tt></tag>
 
   This macro is defined if the code is compiled for a 65816 CPU.
@@ -1241,6 +1253,14 @@ The compiler defines several macros at startup:
 
   This macro is defined if the code is compiled for a HUC6280 CPU.
 
+  <tag><tt>__CPU_M740__</tt></tag>
+
+  This macro is defined if the code is compiled for a M740 CPU.
+
+  <tag><tt>__CPU_W65C02__</tt></tag>
+
+  This macro is defined if the code is compiled for a W65C02 CPU.
+
   <tag><tt>__CPU_ISET_6502__</tt></tag>
 
   This macro expands to a numeric constant that can be used to check the
@@ -1271,6 +1291,12 @@ The compiler defines several macros at startup:
   <tt/<ref id="macro-CPU" name="__CPU__">/ macro for the instruction set
   of the 65C02 CPU.
 
+  <tag><tt>__CPU_ISET_65CE02__</tt></tag>
+
+  This macro expands to a numeric constant that can be used to check the
+  <tt/<ref id="macro-CPU" name="__CPU__">/ macro for the instruction set
+  of the 65CE02 CPU.
+
   <tag><tt>__CPU_ISET_65816__</tt></tag>
 
   This macro expands to a numeric constant that can be used to check the
@@ -1283,6 +1309,18 @@ The compiler defines several macros at startup:
   <tt/<ref id="macro-CPU" name="__CPU__">/ macro for the instruction set
   of the HUC6280 CPU.
 
+  <tag><tt>__CPU_ISET_M740__</tt></tag>
+
+  This macro expands to a numeric constant that can be used to check the
+  <tt/<ref id="macro-CPU" name="__CPU__">/ macro for the instruction set
+  of the M740 CPU.
+
+  <tag><tt>__CPU_ISET_W65C02__</tt></tag>
+
+  This macro expands to a numeric constant that can be used to check the
+  <tt/<ref id="macro-CPU" name="__CPU__">/ macro for the instruction set
+  of the W65C02 CPU.
+
   <tag><tt>__CX16__</tt></tag>
 
   This macro is defined if the target is the Commander X16 (-t cx16).
diff --git a/doc/cpus.sgml b/doc/cpus.sgml
new file mode 100644
index 000000000..60230408f
--- /dev/null
+++ b/doc/cpus.sgml
@@ -0,0 +1,1082 @@
+<!doctype linuxdoc system>
+
+<article>
+<title>ca65/da65 Users Guide
+<author><url url="mailto:uz@cc65.org" name="Ullrich von Bassewitz">,<newline>
+<url url="mailto:groepaz@gmx.net" name="Groepaz">
+
+<abstract>
+An Overview on all supported CPUs
+</abstract>
+
+<!-- Table of contents -->
+<toc>
+
+<!-- Begin the document -->
+
+<sect>Overview<p>
+
+  <itemize>
+  <item><ref id="6502-mode" name="6502"> - NMOS 6502 (all legal instructions)
+  <item><ref id="6502X-mode" name="6502X"> - NMOS 6502 with all undocumented instructions
+  <item><ref id="DTV-mode" name="6502DTV"> - the CPU of the C64 DTV device
+  <item><ref id="65SC02-mode" name="65SC02"> - original CMOS
+  <item><ref id="65C02-mode" name="65C02"> - CMOS with Rockwell extensions
+  <item><ref id="65CE02-mode" name="65CE02"> - CMOS with CSG extensions
+  <item><ref id="W65C02-mode" name="W65C02"> - CMOS with WDC extensions
+  <item><ref id="4510-mode" name="4510"> - the CPU of the Commodore C65
+  <item><ref id="45GS02-mode" name="45GS02"> - the CPU of the Commodore MEGA65
+  <item><ref id="HUC6280-mode" name="HuC6280"> - the CPU of the PC engine
+  <item><ref id="M740-mode" name="M740"> - a Microcontroller by Mitsubishi
+  <item><ref id="65816-mode" name="65816"> - the CPU of the SNES, and the SCPU
+  <item><ref id="sweet16-mode" name="Sweet16"> - an interpreter for a pseudo 16 bit CPU
+  </itemize>
+
+<sect>NMOS branch<p>
+
+<sect1>6502<label id="6502-mode"><p>
+
+The original NMOS 6502 CPU.
+
+For Example: MOS MCS6502 Rev. D, Rockwell R6502, Synertek SY6502, UMC UM6502
+
+(56 instructions, 151 opcodes)
+
+<tscreen><verb>
+$00  brk
+$01  ora (zp,x)
+$05  ora zp
+$06  asl zp
+$08  php
+$09  ora #imm
+$0a  asl a
+$0d  ora addr
+$0e  asl addr
+$10  bpl rel80
+$11  ora (zp),y
+$15  ora zp,x
+$16  asl zp,x
+$18  clc
+$19  ora addr,y
+$1d  ora addr,x
+$1e  asl addr,x
+$20  jsr addr
+$21  and (zp,x)
+$24  bit zp
+$25  and zp
+$26  rol zp
+$28  plp
+$29  and #imm
+$2a  rol a
+$2c  bit addr
+$2d  and addr
+$2e  rol addr
+$30  bmi rel8
+$31  and (zp),y
+$35  and zp,x
+$36  rol zp,x
+$38  sec
+$39  and addr,y
+$3d  and addr,x
+$3e  rol addr,x
+$40  rti
+$41  eor (zp,x)
+$45  eor zp
+$46  lsr zp
+$48  pha
+$49  eor #imm
+$4a  lsr a
+$4c  jmp addr
+$4d  eor addr
+$4e  lsr addr
+$50  bvc rel8
+$51  eor (zp),y
+$55  eor zp,x
+$56  lsr zp,x
+$58  cli
+$59  eor addr,y
+$5d  eor addr,x
+$5e  lsr addr,x
+$60  rts
+$61  adc (zp,x)
+$65  adc zp
+$66  ror zp
+$68  pla
+$69  adc #imm
+$6a  ror a
+$6c  jmp (addr)
+$6d  adc addr
+$6e  ror addr
+$70  bvs rel8
+$71  adc (zp),y
+$75  adc zp,x
+$76  ror zp,x
+$78  sei
+$79  adc addr,y
+$7d  adc addr,x
+$7e  ror addr,x
+$81  sta (zp,x)
+$84  sty zp
+$85  sta zp
+$86  stx zp
+$88  dey
+$8a  txa
+$8c  sty addr
+$8d  sta addr
+$8e  stx addr
+$90  bcc rel8
+$91  sta (zp),y
+$94  sty zp,x
+$95  sta zp,x
+$96  stx zp,y
+$98  tya
+$99  sta addr,y
+$9a  txs
+$9d  sta addr,x
+$a0  ldy #imm
+$a1  lda (zp,x)
+$a2  ldx #imm
+$a4  ldy zp
+$a5  lda zp
+$a6  ldx zp
+$a8  tay
+$a9  lda #imm
+$aa  tax
+$ac  ldy addr
+$ad  lda addr
+$ae  ldx addr
+$b0  bcs rel8
+$b1  lda (zp),y
+$b4  ldy zp,x
+$b5  lda zp,x
+$b6  ldx zp,y
+$b8  clv
+$b9  lda addr,y
+$ba  tsx
+$bc  ldy addr,x
+$bd  lda addr,x
+$be  ldx addr,y
+$c0  cpy #imm
+$c1  cmp (zp,x)
+$c4  cpy zp
+$c5  cmp zp
+$c6  dec zp
+$c8  iny
+$c9  cmp #imm
+$ca  dex
+$cc  cpy addr
+$cd  cmp addr
+$ce  dec addr
+$d0  bne rel8
+$d1  cmp (zp),y
+$d5  cmp zp,x
+$d6  dec zp,x
+$d8  cld
+$d9  cmp addr,y
+$dd  cmp addr,x
+$de  dec addr,x
+$e0  cpx #imm
+$e1  sbc (zp,x)
+$e4  cpx zp
+$e5  sbc zp
+$e6  inc zp
+$e8  inx
+$e9  sbc #imm
+$ea  nop
+$ec  cpx addr
+$ed  sbc addr
+$ee  inc addr
+$f0  beq rel81
+$f1  sbc (zp),y
+$f5  sbc zp,x
+$f6  inc zp,x
+$f8  sed
+$f9  sbc addr,y
+$fd  sbc addr,x
+$fe  inc addr,x
+</verb></tscreen>
+
+
+
+<sect1>6502X<label id="6502X-mode"><p>
+
+6502X mode is an extension to the normal 6502 mode. In this mode, several
+mnemonics for undocumented instructions of the NMOS 6502 CPUs are accepted.
+
+Note: Since these instructions are undocumented, there are no official mnemonics
+for them.
+
+(20 new instructions, 105 new opcodes, 76 instructions/256 opcodes total)
+
+<itemize>
+<item><tt>ALR: A:=(A and #imm)/2;</tt>
+<item><tt>ANC: A:= A and #imm;</tt> Generates opcode &dollar;0B.
+<item><tt>ANE: A:= (A or CONST) and X and #imm;</tt>
+<item><tt>ARR: A:=(A and #imm)/2;</tt>
+<item><tt>AXS: X:=A and X-#imm;</tt>
+<item><tt>DCP: addr:=addr-1; A-addr;</tt>
+<item><tt>ISC: addr:=addr+1; A:=A-addr;</tt>
+<item><tt>JAM:</tt>
+<item><tt>LAS: A,X,S:=addr and S;</tt>
+<item><tt>LAX: A,X:=addr;</tt>
+<item><tt>NOP: #imm; zp; zp,x; abs; abs,x</tt>
+<item><tt>RLA: addr:=addrrol; A:=A and addr;</tt>
+<item><tt>RRA: addr:=addrror; A:=A adc addr;</tt>
+<item><tt>SAX: addr:=A and X;</tt>
+<item><tt>SHA: addr:=A and X and {addr hi +1};</tt>
+<item><tt>SHX: addr:=X and {addr hi +1};</tt>
+<item><tt>SHY: addr:=Y and {addr hi +1};</tt>
+<item><tt>SLO: addr:=addr*2; A:=A or addr;</tt>
+<item><tt>SRE: addr:=addr/2; A:=A xor addr;</tt>
+<item><tt>TAS: addr:=A and X and {addr hi +1}; SP:=A and X;</tt>
+</itemize>
+
+<tscreen><verb>
+$02  jam
+$03  slo (zp,x)
+$04  nop zp
+$07  slo zp
+$0b  anc #imm
+$0c  nop addr
+$0f  slo addr
+$12  jam
+$13  slo (zp),y
+$14  nop zp,x
+$17  slo zp,y
+$1a  nop
+$1b  slo addr,y
+$1c  nop addr,x
+$1f  slo addr,x
+$22  jam
+$23  rla (zp,x)
+$27  rla zp
+$2b  anc #imm
+$2f  rla addr
+$32  jam
+$33  rla (zp),y
+$34  nop zp,x
+$37  rla zp,y
+$3a  nop
+$3b  rla addr,y
+$3c  nop addr,x
+$3f  rla addr,x
+$42  jam
+$43  sre (zp,x)
+$44  nop zp
+$47  sre zp
+$4b  alr #imm
+$4f  sre addr
+$52  jam
+$53  sre (zp),y
+$54  nop zp,x
+$57  sre zp,y
+$5a  nop
+$5b  sre addr,y
+$5c  nop addr,x
+$5f  sre addr,x
+$62  jam
+$63  rra (zp,x)
+$64  nop zp
+$67  rra zp
+$6b  arr #imm
+$6f  rra addr
+$72  jam
+$73  rra (zp),y
+$74  nop zp,x
+$77  rra zp,y
+$7a  nop
+$7b  rra addr,y
+$7c  nop addr,x
+$7f  rra addr,x
+$80  nop #imm
+$82  nop #imm
+$83  sax (zp,x)
+$87  sax zp
+$89  nop #imm
+$8b  ane #imm
+$8f  sax addr
+$92  jam
+$93  sha (zp),y
+$97  sax zp,y
+$9b  tas addr,y
+$9c  shy addr,x
+$9e  shx addr,y
+$9f  sha addr,y
+$a3  lax (zp,x)
+$a7  lax zp
+$ab  lax #imm
+$af  lax addr
+$b2  jam
+$b3  lax (zp),y
+$b7  lax zp,y
+$bb  las addr,y
+$bf  lax addr,y
+$c2  nop #imm
+$c3  dcp (zp,x)
+$c7  dcp zp
+$cb  axs #imm
+$cf  dcp addr
+$d2  jam
+$d3  dcp (zp),y
+$d4  nop zp,x
+$d7  dcp zp,y
+$da  nop
+$db  dcp addr,y
+$dc  nop addr,x
+$df  dcp addr,x
+$e2  nop #imm
+$e3  isc (zp,x)
+$e7  isc zp
+$eb  sbc #imm
+$ef  isc addr
+$f2  jam
+$f3  isc (zp),y
+$f4  nop zp,x
+$f7  isc zp,y
+$fa  nop
+$fb  isc addr,y
+$fc  nop addr,x
+$ff  isc addr,x
+</verb></tscreen>
+
+
+
+<sect1>6502DTV<label id="DTV-mode"><p>
+
+The CPU of the C64 DTV is based on the 6510. It adds some instructions, and does
+not support all undocumented 6510 instructions.
+
+(3+10 new instructions, 3+56 new opcodes, 69 instructions/210 opcodes total)
+
+Opcodes added over 6502 (these are JAM on 6502):
+
+<tscreen><verb>
+$12  bra rel8
+$32  sac #imm
+$42  sir #imm
+</verb></tscreen>
+
+Supported undocumented 6510 instructions (nop, anc, rla, lax, las, alr, arr,
+rra, shy, shx, axs, sbc):
+
+<tscreen><verb>
+$04  nop zp
+$0b  anc #imm
+$0c  nop addr
+$14  nop zp,x
+$1a  nop
+$1c  nop addr,x
+$23  rla (zp,x)
+$27  rla zp
+$2b  anc #imm
+$2f  rla addr
+$33  rla (zp),y
+$34  nop zp,x
+$37  rla zp,y
+$3a  nop
+$3b  rla addr,y
+$3c  nop addr,x
+$3f  rla addr,x
+$44  nop zp
+$4b  alr #imm
+$54  nop zp,x
+$5a  nop
+$5c  nop addr,x
+$63  rra (zp,x)
+$64  nop zp
+$67  rra zp
+$6b  arr #imm
+$6f  rra addr
+$73  rra (zp),y
+$74  nop zp,x
+$77  rra zp,y
+$7a  nop
+$7b  rra addr,y
+$7c  nop addr,x
+$7f  rra addr,x
+$80  nop #imm
+$82  nop #imm
+$89  nop #imm
+$9c  shy addr,x
+$9e  shx addr,y
+$a3  lax (zp,x)
+$a7  lax zp
+$ab  lax #imm
+$af  lax addr
+$b3  lax (zp),y
+$b7  lax zp,y
+$bb  las addr,y
+$bf  lax addr,y
+$c2  nop #imm
+$cb  axs #imm
+$d4  nop zp,x
+$da  nop
+$dc  nop addr,x
+$e2  nop #imm
+$eb  sbc #imm
+$f4  nop zp,x
+$fa  nop
+$fc  nop addr,x
+</verb></tscreen>
+
+
+<sect>CMOS branch<p>
+
+The original CMOS version was apparently developed already back in the Commodore
+days, but never saw the light of day. It was then licensed by (now) WDC to
+different other vendors. Unfortunately some of those named their chips "65C02"
+(not SC), which causes a lot of confusion now. So keep that in mind: some chips
+that are named "65C02" will only support the original 65SC02 instruction set.
+
+
+<sect1>65SC02 (Original CMOS)<label id="65SC02-mode"><p>
+
+The first CMOS instruction set, without bit manipulation, nor wai/stp. It adds
+8 new instructions (phx, phy, plx, ply, bra, stz, tsb, trb) and two new address
+modes (zeropage-indirect, absolute-x-indexed-indirect) to the original (legal)
+6502 instructions.
+
+For example: Synertek SY65C02, GTE G65SC02, CMD G65SC02, NCR 65C02
+
+(8 new instructions, 27 new opcodes, 64 instructions/178 opcodes total)
+
+<tscreen><verb>
+$04  tsb zp
+$0c  tsb abs16
+$12  ora (zp)
+$14  trb zp
+$1a  inc
+$1c  trb abs16
+$32  and (zp)
+$34  bit zp, x
+$3a  dec
+$3c  bit abs16, x
+$52  eor (zp)
+$5a  phy
+$64  stz zp
+$72  adc (zp)
+$74  stz zp, x
+$7a  ply
+$7c  jmp (abs16, x)
+$80  bra rel8
+$89  bit #imm8
+$92  sta (zp)
+$9c  stz abs16
+$9e  stz abs16, x
+$b2  lda (zp)
+$d2  cmp (zp)
+$da  phx
+$f2  sbc (zp)
+$fa  plx
+</verb></tscreen>
+
+
+
+<sect1>65C02 (CMOS with Rockwell extensions)<label id="65C02-mode"><p>
+
+The Rockwell extensions add additional bit manipulation and bit test-and-branch
+commands to the original 65SC02 instruction set.
+
+For Example: Rockwell R65C02, Ricoh RP65C02, NCR 65CX02
+
+(4 new instructions, 32 new opcodes, 68 instructions/210 opcodes total)
+
+<tscreen><verb>
+$07  rmb0 zp          clear bit in zp location
+$0f  bbr0 zp, rel8    branch if bit is not set in zp location
+$17  rmb1 zp
+$1f  bbr1 zp, rel8
+$27  rmb2 zp
+$2f  bbr2 zp, rel8
+$37  rmb3 zp
+$3f  bbr3 zp, rel8
+$47  rmb4 zp
+$4f  bbr4 zp, rel8
+$57  rmb5 zp
+$5f  bbr5 zp, rel8
+$67  rmb6 zp
+$6f  bbr6 zp, rel8
+$77  rmb7 zp
+$7f  bbr7 zp, rel8
+$87  smb0 zp          set bit in zp location
+$8f  bbs0 zp, rel8    branch if bit is set in zp location
+$97  smb1 zp
+$9f  bbs1 zp, rel8
+$a7  smb2 zp
+$af  bbs2 zp, rel8
+$b7  smb3 zp
+$bf  bbs3 zp, rel8
+$c7  smb4 zp
+$cf  bbs4 zp, rel8
+$d7  smb5 zp
+$df  bbs5 zp, rel8
+$e7  smb6 zp
+$ef  bbs6 zp, rel8
+$f7  smb7 zp
+$ff  bbs7 zp, rel8
+</verb></tscreen>
+
+All "illegal" opcodes perform NOP on this CPU.
+
+
+
+<sect1>W65C02 (CMOS with WDC extensions)<label id="W65C02-mode"><p>
+
+For their W65C02S WDC took the Rockwell extensions, and added two extra
+instructions (which they also added to the 65C816/65C802)
+
+(2 new instructions, 2 new opcodes, 70 instructions/212 opcodes total)
+
+<tscreen><verb>
+$cb  wai    wait for interrupt
+$db  stp    wait for reset
+</verb></tscreen>
+
+All "illegal" opcodes perform NOP on this CPU.
+
+
+
+<sect1>65CE02 (CMOS with CSG extensions)<label id="65CE02-mode"><p>
+
+CSG took the Rockwell extensions and developed them further. Notable additions
+are long relative branches/jumps, and finally a real z register. Note that the
+two opcodes used by the WDC extensions have been repurposed for something else,
+so the 65CE02 is not 100% compatible with the W65C02.
+
+For Example: CSG 65CE02 (used on the Amiga A2232 Serial Card)
+
+(34 new instructions, 46 new opcodes, 102 instructions/256 opcodes total)
+
+<tscreen><verb>
+$02  cle              clear stack extend disable
+$03  see              set stack extend disable
+$0b  tsy              transfer stack_ptr_high to Y
+$12  ora (zp), z
+$13  lbpl rel16
+$1b  inz              increment Z
+$22  jsr (abs16)
+$23  jsr (abs16, x)
+$2b  tys              transfer Y to stack_ptr_high
+$32  and (zp), z
+$33  lbmi rel16
+$3b  dez              decrement Z
+$42  neg              negate A
+$43  asr
+$44  asr zp
+$4b  taz              transfer A to Z
+$52  eor (zp), z
+$53  lbvc rel16
+$54  asr zp, x
+$5b  tab
+$5c  aug              "4-byte NOP reserved for future expansion"
+$62  rtn #imm8
+$63  lbsr rel16       relative jsr, "branch to subroutine"
+$64  stz zp           store Z
+$6b  tza              transfer Z to A
+$72  adc (zp), z
+$73  lbvs rel16
+$74  stz zp, x        store Z
+$7b  tba
+$82  sta (off8, s), y
+$83  lbra rel16       relative jmp
+$8b  sty abs16, x
+$92  sta (zp), z
+$93  lbcc rel16
+$9b  stx abs16, y
+$9c  stz abs16        store Z
+$9e  stz abs16, x     store Z
+$a3  ldz #imm8
+$ab  ldz abs16
+$b2  lda (zp), z
+$b3  lbcs rel16
+$bb  ldz abs16, x
+$c2  cpz #imm8
+$c3  dew zp
+$cb  asw abs16
+$d2  cmp (zp), z
+$d3  lbne rel16
+$d4  cpz zp
+$db  phz              push Z
+$dc  cpz abs16
+$e2  lda (off8, s), y
+$e3  inw zp
+$eb  row abs16
+$f2  sbc (zp), z
+$f3  lbeq rel16
+$f4  phw #imm16
+$fb  plz              pull Z
+$fc  phw abs16
+</verb></tscreen>
+
+One notable change is that some instructions of the original CMOS instruction set
+were changed from "zeropage indirect" addressing to "zeropage indirect, z indexed".
+This could be done, because the z register is initially guaranteed to be zero,
+making the CPU binary compatible with older CMOS variants.
+
+<tscreen><verb>
+$12  ora (zp)  ->  ora (zp), z
+$32  and (zp)  ->  and (zp), z
+$52  eor (zp)  ->  eor (zp), z
+$72  adc (zp)  ->  adc (zp), z
+$92  sta (zp)  ->  sta (zp), z
+$b2  lda (zp)  ->  cmp (zp), z
+$d2  cmp (zp)  ->  lda (zp), z
+$f2  sbc (zp)  ->  sbc (zp), z
+</verb></tscreen>
+
+Additional to that, the meaning of the following instruction changes from "store
+zero" to "store z register". Again, this makes the CPU binary compatible with
+older CMOS variants
+
+<tscreen><verb>
+$64  stz zp
+$74  stz zp, x
+$9c  stz abs16
+$9e  stz abs16, x
+</verb></tscreen>
+
+The other 65SC02 instructions (phx, phy, plx, ply, tsb, trb, bra) are unchanged.
+
+
+
+<sect1>4510<label id="4510-mode"><p>
+
+The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX.
+It contains among other functions a slightly modified 65CE02/4502 CPU, to allow
+address mapping for 20 bits of address space (1 megabyte addressable area).
+
+The 4510 supports the complete 65CE02 instruction set, but changes
+the 4-Byte NOP into the "map" instruction:
+
+<tscreen><verb>
+$5c  map
+</verb></tscreen>
+
+For more information about the Commodore C65/C64DX and the 4510 CPU, see
+<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/"> and
+<url url="https://en.wikipedia.org/wiki/Commodore_65" name="Wikipedia">.
+
+
+
+<sect1>45GS02<label id="45GS02-mode"><p>
+
+The 45GS02 is a microcontroller that is the core of the MEGA65.
+It is an extension of the 4510 CPU and adds 32-bit addressing and a 32-bit
+pseudo register Q that is comprised of the four registers A, X, Y, and Z.
+
+<tscreen><verb>
+$42 $42 $05      orq zp
+$42 $42 $06      aslq zp
+$42 $42 $0a      aslq
+$42 $42 $0d      orq addr
+$42 $42 $0e      aslq addr
+$42 $42 $12      orq (zp)
+$42 $42 $16      aslq zp,x
+$42 $42 $1a      inq
+$42 $42 $1e      aslq addr,x
+$42 $42 $24      bitq zp
+$42 $42 $25      andq zp
+$42 $42 $26      rolq zp
+$42 $42 $2a      rolq
+$42 $42 $2c      bitq addr
+$42 $42 $2d      andq addr
+$42 $42 $2e      rolq addr
+$42 $42 $32      andq (zp)
+$42 $42 $36      rolq zp, x
+$42 $42 $3a      deq
+$42 $42 $3e      rolq addr, x
+$42 $42 $43      asrq
+$42 $42 $44      asrq zp
+$42 $42 $45      eorq zp
+$42 $42 $46      lsrq zp
+$42 $42 $4a      lsrq
+$42 $42 $4d      eorq addr
+$42 $42 $4e      lsrq addr
+$42 $42 $52      eorq (zp)
+$42 $42 $54      asrq zp, x
+$42 $42 $56      lsrq zp, x
+$42 $42 $5e      lsrq addr, x
+$42 $42 $65      adcq zp
+$42 $42 $66      rorq zp
+$42 $42 $6a      rorq
+$42 $42 $6d      adcq addr
+$42 $42 $6e      rorq addr
+$42 $42 $72      adcq (zp)
+$42 $42 $76      rorq zp, x
+$42 $42 $7e      rorq addr, x
+$42 $42 $85      stq zp
+$42 $42 $8d      stq addr
+$42 $42 $92      stq (zp)
+$42 $42 $a5      ldq zp
+$42 $42 $ad      ldq addr
+$42 $42 $b2      ldq (zp), z
+$42 $42 $c5      cmpq zp
+$42 $42 $c6      deq zp
+$42 $42 $cd      cmpq addr
+$42 $42 $ce      deq addr
+$42 $42 $d2      cmpq (zp)
+$42 $42 $d6      deq zp, x
+$42 $42 $de      deq addr, x
+$42 $42 $e5      sbcq zp
+$42 $42 $e6      inq zp
+$42 $42 $ed      sbcq addr
+$42 $42 $ee      inq addr
+$42 $42 $f2      sbcq (zp)
+$42 $42 $f6      inq zp, x
+$42 $42 $fe      inq addr, x
+
+$ea $12          ora [zp], z
+$ea $32          and [zp], z
+$ea $52          eor [zp], z
+$ea $72          adc [zp], z
+$ea $92          sta [zp], z
+$ea $b2          lda [zp], z
+$ea $d2          cmp [zp], z
+$ea $f2          sbc [zp], z
+
+$42 $42 $ea $12  orq [zp]
+$42 $42 $ea $32  andq [zp]
+$42 $42 $ea $52  eorq [zp]
+$42 $42 $ea $72  adcq [zp]
+$42 $42 $ea $92  stq [zp]
+$42 $42 $ea $b2  ldq [zp], z
+$42 $42 $ea $d2  cmpq [zp]
+$42 $42 $ea $f2  sbcq [zp]
+</verb></tscreen>
+
+
+<sect1>HUC6280<label id="HUC6280-mode"><p>
+
+The HUC6280 is a superset of 65C02. It implements the original CMOS instructions
+with Rockwell extensions, plus some other instructions:
+
+<tscreen><verb>
+$02  sxy
+$03  st0 #imm
+$13  st1 #imm
+$22  sax
+$23  st2 #imm
+$42  say
+$43  tma #imm
+$44  bsr rel8
+$53  tam #imm
+$54  csl
+$62  cla
+$73  tii addr, addr, addr
+$82  clx
+$83  tst #imm, zp
+$82  clx
+$83  tst #imm, zp
+$93  tst #imm, addr
+$a3  tst #imm, zp, x
+$b3  tst #imm, addr, x
+$c2  cly
+$c3  tdd addr, addr, addr
+$d3  tin addr, addr, addr
+$d4  csh
+$e3  tia addr, addr, addr
+$f3  tai addr, addr, addr
+$f4  set
+</verb></tscreen>
+
+
+<sect1>M740<label id="M740-mode"><p>
+
+The M740 is a microcontroller by Mitsubishi, which was marketed for embedded
+devices in the mid 80s. It is a superset of 6502, the added CMOS instructions
+seem to be completely custom however:
+
+<tscreen><verb>
+$02  jsr (zp)
+$03  bbs0 a, rel8
+$07  bbs0 zp, rel8
+$0b  seb0 a
+$0f  seb0 zp
+$12  clt
+$13  bbc0 a, rel8
+$17  bbc0 zp, rel8
+$1a  inc a
+$1b  clb0 a
+$1f  clb0 zp
+$22  jsr $ff12
+$23  bbs1 a, rel8
+$27  bbs1 zp, rel8
+$2b  seb1 a
+$2f  seb1 zp
+$32  set
+$33  bbc1 a, rel8
+$37  bbc1 zp, rel8
+$3a  dec a
+$3b  clb1 a
+$3c  ldm zp, #imm
+$3f  clb1 zp
+$42  stp
+$43  bbs2 a, rel8
+$44  com zp
+$47  bbs2 zp, rel8
+$4b  seb2 a
+$4f  seb2 zp
+$53  bbc2 a, rel8
+$57  bbc2 zp, rel8
+$5b  clb2 a
+$5f  clb2 zp
+$63  bbs3 a, rel8
+$64  tst zp
+$67  bbs3 zp, rel8
+$6b  seb3 a
+$6f  seb3 zp
+$73  bbc3 a, rel8
+$77  bbc3 zp, rel8
+$7b  clb3 a
+$7f  clb3 zp
+$80  bra rel8
+$82  rrf zp
+$83  bbs4 a, rel8
+$87  bbs4 zp, rel8
+$8b  seb4 a
+$8f  seb4 zp
+$93  bbc4 a, rel8
+$97  bbc4 zp, rel8
+$9b  clb4 a
+$9f  clb4 zp
+$a3  bbs5 a, rel8
+$a7  bbs5 zp, rel8
+$ab  seb5 a
+$af  seb5 zp
+$b2  lda (zp)
+$b3  bbc5 a, rel8
+$b7  bbc5 zp, rel8
+$bb  clb5 a
+$bf  clb5 zp
+$c2  slw
+$c3  bbs6 a, rel8
+$c7  bbs6 zp, rel8
+$cb  seb6 a
+$cf  seb6 zp
+$d3  bbc6 a, rel8
+$d7  bbc6 zp, rel8
+$db  clb6 a
+$df  clb6 zp
+$e2  fst
+$e3  bbs7 a, rel8
+$e7  bbs7 zp, rel8
+$eb  seb7 a
+$ef  seb7 zp
+$f3  bbc7 a, rel8
+$f7  bbc7 zp, rel8
+$fb  clb7 a
+$ff  clb7 zp
+</verb></tscreen>
+
+Four instructions are the same on 65SC02:
+
+<tscreen><verb>
+$1a  inc a
+$3a  dec a
+$80  bra rel8
+$b2  lda (zp)
+</verb></tscreen>
+
+These four instructions are different from 65SC02:
+
+<tscreen><verb>
+$12  ora (zp)     -> clt
+$32  and (zp)     -> set
+$3c  bit addr,x   -> ldm zp, #imm
+$64  stz zp       -> tst zp
+</verb></tscreen>
+
+The following 65SC02 instructions are not implemented:
+
+<tscreen><verb>
+$04  tsb zp
+$0c  tsb addr
+$14  trb zp
+$1c  trb addr
+$34  bit zp,y
+$52  eor (zp)
+$5a  phy
+$72  adc (zp)
+$74  stz zp,y
+$7a  ply
+$7c  jmp (addr)
+$89  bit #imm8
+$92  sta (zp)
+$9c  stz addr
+$9e  stz addr,x
+$d2  cmp (zp)
+$da  phx
+$f2  sbc (zp)
+$fa  plx
+</verb></tscreen>
+
+For more information about the M740 Controllers, see
+<url url="https://en.wikipedia.org/wiki/Mitsubishi_740" name="Wikipedia">.
+
+
+
+<sect1>65816<label id="65816-mode"><p><p>
+
+The W65C816S is a 16bit CPU developed by WDC. The instruction set contains the
+complete legal 6502 instructions, the original CMOS instructions (65SC02), plus
+some new instructions and addressing modes. It has wai/stp, but it does NOT have
+the Rockwell extensions (BBRx, BBSx, RMBx and SMBx bit manipulation instructions).
+
+(24 new instructions, 77 new opcodes, 88 instructions/256 opcodes total)
+
+<tscreen><verb>
+$02  cop imm8               coprocessor operation
+$03  ora offs8, s
+$07  ora [dp]
+$0b  phd                    push direct page register
+$0f  ora abs24
+$13  ora (offs8, s), y
+$17  ora [dp], y
+$1b  tcs                    transfer C to stack pointer
+$1f  ora abs24, x
+$22  jsl abs24
+$23  and offs8, s
+$27  and [dp]
+$2b  pld                    pull direct page register
+$2f  and abs24
+$33  and (offs8, s), y
+$37  and [dp], y
+$3b  tsc                    transfer stack pointer to C
+$3f  and abs24, x
+$42  wdm                    (reserved for future expansion)
+$43  eor offs8, s
+$44  mvp src, dst
+$47  eor [dp]
+$4b  phk                    push program bank register
+$4f  eor abs24
+$53  eor (offs8, s), y
+$54  mvn src, dst
+$57  eor [dp], y
+$5b  tcd                    transfer C to direct page register
+$5c  jml abs24
+$5f  eor abs24, x
+$62  per rel16              push effective relative address
+$63  adc offs8, s
+$67  adc [dp]
+$6b  rtl                    return long (fetches 24-bit address from stack)
+$6f  adc abs24
+$73  adc (offs8, s), y
+$77  adc [dp], y
+$7b  tdc                    transfer direct page register to C
+$7f  adc abs24, x
+$82  brl rel16              branch long (16-bit offset)
+$83  sta offs8, s
+$87  sta [dp]
+$8b  phb                    push data bank register
+$8f  sta abs24
+$93  sta (offs8, s), y
+$97  sta [dp], y
+$9b  txy                    transfer X to Y
+$9f  sta abs24, x
+$a3  lda offs8, s
+$a7  lda [dp]
+$ab  plb                    pull data bank register
+$af  lda abs24
+$b3  lda (offs8, s), y
+$b7  lda [dp], y
+$bb  tyx                    transfer Y to X
+$bf  lda abs24, x
+$c2  rep #imm8              clear bits in status register
+$c3  cmp offs8, s
+$c7  cmp [dp]
+$cb  wai                    wait for interrupt
+$cf  cmp abs24
+$d3  cmp (offs8, s), y
+$d4  pei (dp)               push effective indirect address
+$d7  cmp [dp], y
+$db  stp                    wait for reset
+$dc  jmp [abs16]
+$df  cmp abs24, x
+$e2  sep #imm8              set bits in status register
+$e3  sbc offs8, s
+$e7  sbc [dp]
+$eb  xba                    exchange high and low bytes of accumulator
+$ef  sbc abs24
+$f3  sbc (offs8, s), y
+$f4  pea abs16              push effective absolute address
+$f7  sbc [dp], y
+$fb  xce                    exchange Carry and Emulation bits
+$fc  jsr (abs16, x)
+$ff  sbc abs24, x
+</verb></tscreen>
+
+
+
+<sect>other<p>
+
+<sect1>Sweet16<label id="sweet16-mode"><p><p>
+
+SWEET 16 is an interpreter for a pseudo 16 bit CPU written by Steve Wozniak
+for the Apple ][ machines. It is available in the Apple ][ ROM.
+
+It implements the following opcodes:
+
+<tscreen><verb>
+00   1     RTN                                (Return to 6502 mode)
+01   2     BR        ea                       (Branch always)
+02   2     BNC       ea                       (Branch if No Carry)
+03   2     BC        ea                       (Branch if Carry)
+04   2     BP        ea                       (Branch if Plus)
+05   2     BM        ea                       (Branch if Minus)
+06   2     BZ        ea                       (Branch if Zero)
+07   2     BNZ       ea                       (Branch if NonZero)
+08   2     BM1       ea                       (Branch if Minus 1)
+09   2     BNM1      ea                       (Branch if Not Minus 1)
+0A   1     BK                                 (Break to Monitor)
+0B   1     RS                                 (Return from Subroutine)
+0C   1     BS        ea                       (Branch to Subroutine)
+1n   3     SET       Rn    R<-2 byte constant (Set Constant) (load register immediate)
+2n   1     LD        Rn    ACC<-R             (Load)
+3n   1     ST        Rn    ACC->R (Store)
+4n   1     LD        @Rn   ACC<-@R, R<-R+1    (Load Indirect)
+5n   1     ST        @Rn   ACC->@R, R<-R+1    (Store Indirect)
+6n   1     LDD       @Rn   ACC<-@R double     (Load Double Indirect)
+7n   1     STD       @Rn   ACC->@R double     (Store Double Indirect)
+8n   1     POP       @Rn   R<-R-1, ACC<-@R    (pop) (Pop Indirect)
+9n   1     STP       @Rn   R<-R-1, ACC->@R    (Store POP Indirect)
+An   1     ADD       Rn    ACC<-@R            (pop) double (Add)
+Bn   1     SUB       Rn    compare ACC to R   (Sub)
+Cn   1     POPD      @Rn   ACC<-ACC+R         (Pop Double Indirect)
+Dn   1     CPR       Rn    ACC<-ACC-R         (Compare)
+En   1     INR       Rn    R<-R+1             (Increment)
+Fn   1     DCR       Rn    R<-R-1             (Decrement)
+</verb></tscreen>
+
+For more information about SWEET 16, see
+<url url="http://www.6502.org/source/interpreters/sweet16.htm">.
+
+
+
+<sect>Copyright<p>
+
+ca65 (and all cc65 binutils) are (C) Copyright 1998-2003 Ullrich von
+Bassewitz. For usage of the binaries and/or sources the following
+conditions do apply:
+
+This software is provided 'as-is', without any expressed or implied
+warranty.  In no event will the authors be held liable for any damages
+arising from the use of this software.
+
+Permission is granted to anyone to use this software for any purpose,
+including commercial applications, and to alter it and redistribute it
+freely, subject to the following restrictions:
+
+<enum>
+<item>  The origin of this software must not be misrepresented; you must not
+        claim that you wrote the original software. If you use this software
+        in a product, an acknowledgment in the product documentation would be
+        appreciated but is not required.
+<item>  Altered source versions must be plainly marked as such, and must not
+        be misrepresented as being the original software.
+<item>  This notice may not be removed or altered from any source
+        distribution.
+</enum>
+
+
+
+</article>
diff --git a/doc/da65.sgml b/doc/da65.sgml
index 314e552a9..ba3ceb165 100644
--- a/doc/da65.sgml
+++ b/doc/da65.sgml
@@ -267,19 +267,21 @@ With the command line option <tt><ref id="option--cpu" name="--cpu"></tt>, the
 disassembler may be told which CPU to support:
 
   <itemize>
-  <item><ref id="6502-mode" name="6502"> - NMOS 6502 (all legal instructions)
-  <item><ref id="6502X-mode" name="6502X"> - NMOS 6502 with all undocumented instructions
-  <item><ref id="DTV-mode" name="6502DTV"> - the emulated CPU of the C64DTV device
-  <item><ref id="65SC02-mode" name="65SC02"> - first CMOS instruction set (no bit manipulation, no wai/stp)
-  <item><ref id="65C02-mode" name="65C02"> - full CMOS instruction set (has bit manipulation and wai/stp)
-  <item><ref id="65816-mode" name="65816"> - the CPU of the SNES, and the SCPU
-  <item><ref id="HUC6280-mode" name="HuC6280"> - the CPU of the PC engine
-  <item><ref id="4510-mode" name="4510"> - the CPU of the Commodore C65
-  <item><ref id="45GS02-mode" name="45GS02"> - the CPU of the Commodore MEGA65
-  <item><ref id="M740-mode" name="M740"> - a Microcontroller by Mitsubishi
+  <item>6502 - NMOS 6502 (all legal instructions)
+  <item>6502X - NMOS 6502 with all undocumented instructions
+  <item>6502DTV - the emulated CPU of the C64DTV device
+  <item>65SC02 - first CMOS instruction set (no bit manipulation, no wai/stp)
+  <item>65C02 - CMOS with Rockwell extensions
+  <item>W65C02 - full CMOS instruction set (has bit manipulation and wai/stp)
+  <item>65CE02 - CMOS with CSG extensions
+  <item>4510 - the CPU of the Commodore C65
+  <item>45GS02 - the CPU of the Commodore MEGA65
+  <item>HuC6280 - the CPU of the PC engine
+  <item>M740 - a Microcontroller by Mitsubishi
+  <item>65816 - the CPU of the SNES, and the SCPU
   </itemize>
 
-for more details on the various CPUs, see <tt><htmlurl url="ca65.html#6502-mode" name="here"></tt>.
+for more details on the various CPUs, see <tt><htmlurl url="cpus.html" name="here"></tt>.
 
 
 <sect2>6502 mode<label id="6502-mode"><p>
@@ -308,8 +310,12 @@ The first CMOS instruction set, without bit manipulation or wai/stp.
 The 65C02 understands the same opcodes as the 65SC02, plus 16 additional bit
 manipulation and bit test-and-branch commands.
 
+<sect2>W65C02 mode<label id="W65C02-mode"><p>
+
 This mode also supports wai/stp.
 
+<sect2>65CE02 mode<label id="65CE02-mode"><p>
+
 
 <sect2>4510 mode<label id="4510-mode"><p>
 
diff --git a/src/ca65/condasm.c b/src/ca65/condasm.c
index c63e54e3a..7cd3310b3 100644
--- a/src/ca65/condasm.c
+++ b/src/ca65/condasm.c
@@ -424,6 +424,16 @@ void DoConditionals (void)
                 CalcOverallIfCond ();
                 break;
 
+            case TOK_IFP6280:
+                D = AllocIf (".IFP6280", 1);
+                NextTok ();
+                if (IfCond) {
+                    SetIfCond (D, GetCPU() == CPU_HUC6280);
+                }
+                ExpectSep ();
+                CalcOverallIfCond ();
+                break;
+
             case TOK_IFP816:
                 D = AllocIf (".IFP816", 1);
                 NextTok ();
@@ -444,6 +454,16 @@ void DoConditionals (void)
                 CalcOverallIfCond ();
                 break;
 
+            case TOK_IFPCE02:
+                D = AllocIf (".IFPCE02", 1);
+                NextTok ();
+                if (IfCond) {
+                    SetIfCond (D, GetCPU() == CPU_65CE02);
+                }
+                ExpectSep ();
+                CalcOverallIfCond ();
+                break;
+
             case TOK_IFPDTV:
                 D = AllocIf (".IFPDTV", 1);
                 NextTok ();
@@ -474,6 +494,26 @@ void DoConditionals (void)
                 CalcOverallIfCond ();
                 break;
 
+            case TOK_IFPSWEET16:
+                D = AllocIf (".IFPSWEET16", 1);
+                NextTok ();
+                if (IfCond) {
+                    SetIfCond (D, GetCPU() == CPU_SWEET16);
+                }
+                ExpectSep ();
+                CalcOverallIfCond ();
+                break;
+
+            case TOK_IFPWC02:
+                D = AllocIf (".IFPWC02", 1);
+                NextTok ();
+                if (IfCond) {
+                    SetIfCond (D, GetCPU() == CPU_W65C02);
+                }
+                ExpectSep ();
+                CalcOverallIfCond ();
+                break;
+
             case TOK_IFREF:
                 D = AllocIf (".IFREF", 1);
                 NextTok ();
@@ -518,11 +558,15 @@ int CheckConditionals (void)
         case TOK_IFP02X:
         case TOK_IFP4510:
         case TOK_IFP45GS02:
+        case TOK_IFP6280:
         case TOK_IFP816:
         case TOK_IFPC02:
+        case TOK_IFPCE02:
         case TOK_IFPDTV:
         case TOK_IFPM740:
         case TOK_IFPSC02:
+        case TOK_IFPSWEET16:
+        case TOK_IFPWC02:
         case TOK_IFREF:
             DoConditionals ();
             return 1;
diff --git a/src/ca65/instr.c b/src/ca65/instr.c
index c19be11b2..d38a42843 100644
--- a/src/ca65/instr.c
+++ b/src/ca65/instr.c
@@ -426,7 +426,7 @@ static const struct {
     }
 };
 
-/* Instruction table for the 65SC02 */
+/* Instruction table for the 65SC02 (original CMOS) */
 static const struct {
     unsigned Count;
     InsDesc  Ins[66];
@@ -505,14 +505,125 @@ static const struct {
     }
 };
 
-/* Instruction table for the 65C02 */
+/* Instruction table for the 65C02 (CMOS with Rockwell extensions) */
 static const struct {
     unsigned Count;
-    InsDesc  Ins[100];
+    InsDesc  Ins[98];
 } InsTab65C02 = {
     /* CAUTION: table must be sorted for bsearch */
     sizeof (InsTab65C02.Ins) / sizeof (InsTab65C02.Ins[0]),
     {
+/* BEGIN SORTED.SH */
+        { "ADC",  0x080A66C, 0x60, 0, PutAll },
+        { "AND",  0x080A66C, 0x20, 0, PutAll },
+        { "ASL",  0x000006e, 0x02, 1, PutAll },
+        { "BBR0", 0x0000000, 0x0F, 0, PutBitBranch },
+        { "BBR1", 0x0000000, 0x1F, 0, PutBitBranch },
+        { "BBR2", 0x0000000, 0x2F, 0, PutBitBranch },
+        { "BBR3", 0x0000000, 0x3F, 0, PutBitBranch },
+        { "BBR4", 0x0000000, 0x4F, 0, PutBitBranch },
+        { "BBR5", 0x0000000, 0x5F, 0, PutBitBranch },
+        { "BBR6", 0x0000000, 0x6F, 0, PutBitBranch },
+        { "BBR7", 0x0000000, 0x7F, 0, PutBitBranch },
+        { "BBS0", 0x0000000, 0x8F, 0, PutBitBranch },
+        { "BBS1", 0x0000000, 0x9F, 0, PutBitBranch },
+        { "BBS2", 0x0000000, 0xAF, 0, PutBitBranch },
+        { "BBS3", 0x0000000, 0xBF, 0, PutBitBranch },
+        { "BBS4", 0x0000000, 0xCF, 0, PutBitBranch },
+        { "BBS5", 0x0000000, 0xDF, 0, PutBitBranch },
+        { "BBS6", 0x0000000, 0xEF, 0, PutBitBranch },
+        { "BBS7", 0x0000000, 0xFF, 0, PutBitBranch },
+        { "BCC",  0x0020000, 0x90, 0, PutPCRel8 },
+        { "BCS",  0x0020000, 0xb0, 0, PutPCRel8 },
+        { "BEQ",  0x0020000, 0xf0, 0, PutPCRel8 },
+        { "BIT",  0x0A0006C, 0x00, 2, PutAll },
+        { "BMI",  0x0020000, 0x30, 0, PutPCRel8 },
+        { "BNE",  0x0020000, 0xd0, 0, PutPCRel8 },
+        { "BPL",  0x0020000, 0x10, 0, PutPCRel8 },
+        { "BRA",  0x0020000, 0x80, 0, PutPCRel8 },
+        { "BRK",  0x0800005, 0x00, 6, PutAll },
+        { "BVC",  0x0020000, 0x50, 0, PutPCRel8 },
+        { "BVS",  0x0020000, 0x70, 0, PutPCRel8 },
+        { "CLC",  0x0000001, 0x18, 0, PutAll },
+        { "CLD",  0x0000001, 0xd8, 0, PutAll },
+        { "CLI",  0x0000001, 0x58, 0, PutAll },
+        { "CLV",  0x0000001, 0xb8, 0, PutAll },
+        { "CMP",  0x080A66C, 0xc0, 0, PutAll },
+        { "CPX",  0x080000C, 0xe0, 1, PutAll },
+        { "CPY",  0x080000C, 0xc0, 1, PutAll },
+        { "DEA",  0x0000001, 0x00, 3, PutAll },   /* == DEC */
+        { "DEC",  0x000006F, 0x00, 3, PutAll },
+        { "DEX",  0x0000001, 0xca, 0, PutAll },
+        { "DEY",  0x0000001, 0x88, 0, PutAll },
+        { "EOR",  0x080A66C, 0x40, 0, PutAll },
+        { "INA",  0x0000001, 0x00, 4, PutAll },   /* == INC */
+        { "INC",  0x000006f, 0x00, 4, PutAll },
+        { "INX",  0x0000001, 0xe8, 0, PutAll },
+        { "INY",  0x0000001, 0xc8, 0, PutAll },
+        { "JMP",  0x0010808, 0x4c, 6, PutAll },
+        { "JSR",  0x0000008, 0x20, 7, PutAll },
+        { "LDA",  0x080A66C, 0xa0, 0, PutAll },
+        { "LDX",  0x080030C, 0xa2, 1, PutAll },
+        { "LDY",  0x080006C, 0xa0, 1, PutAll },
+        { "LSR",  0x000006F, 0x42, 1, PutAll },
+        { "NOP",  0x0000001, 0xea, 0, PutAll },
+        { "ORA",  0x080A66C, 0x00, 0, PutAll },
+        { "PHA",  0x0000001, 0x48, 0, PutAll },
+        { "PHP",  0x0000001, 0x08, 0, PutAll },
+        { "PHX",  0x0000001, 0xda, 0, PutAll },
+        { "PHY",  0x0000001, 0x5a, 0, PutAll },
+        { "PLA",  0x0000001, 0x68, 0, PutAll },
+        { "PLP",  0x0000001, 0x28, 0, PutAll },
+        { "PLX",  0x0000001, 0xfa, 0, PutAll },
+        { "PLY",  0x0000001, 0x7a, 0, PutAll },
+        { "RMB0", 0x0000004, 0x07, 1, PutAll },
+        { "RMB1", 0x0000004, 0x17, 1, PutAll },
+        { "RMB2", 0x0000004, 0x27, 1, PutAll },
+        { "RMB3", 0x0000004, 0x37, 1, PutAll },
+        { "RMB4", 0x0000004, 0x47, 1, PutAll },
+        { "RMB5", 0x0000004, 0x57, 1, PutAll },
+        { "RMB6", 0x0000004, 0x67, 1, PutAll },
+        { "RMB7", 0x0000004, 0x77, 1, PutAll },
+        { "ROL",  0x000006F, 0x22, 1, PutAll },
+        { "ROR",  0x000006F, 0x62, 1, PutAll },
+        { "RTI",  0x0000001, 0x40, 0, PutAll },
+        { "RTS",  0x0000001, 0x60, 0, PutAll },
+        { "SBC",  0x080A66C, 0xe0, 0, PutAll },
+        { "SEC",  0x0000001, 0x38, 0, PutAll },
+        { "SED",  0x0000001, 0xf8, 0, PutAll },
+        { "SEI",  0x0000001, 0x78, 0, PutAll },
+        { "SMB0", 0x0000004, 0x87, 1, PutAll },
+        { "SMB1", 0x0000004, 0x97, 1, PutAll },
+        { "SMB2", 0x0000004, 0xA7, 1, PutAll },
+        { "SMB3", 0x0000004, 0xB7, 1, PutAll },
+        { "SMB4", 0x0000004, 0xC7, 1, PutAll },
+        { "SMB5", 0x0000004, 0xD7, 1, PutAll },
+        { "SMB6", 0x0000004, 0xE7, 1, PutAll },
+        { "SMB7", 0x0000004, 0xF7, 1, PutAll },
+        { "STA",  0x000A66C, 0x80, 0, PutAll },
+        { "STX",  0x000010c, 0x82, 1, PutAll },
+        { "STY",  0x000002c, 0x80, 1, PutAll },
+        { "STZ",  0x000006c, 0x04, 5, PutAll },
+        { "TAX",  0x0000001, 0xaa, 0, PutAll },
+        { "TAY",  0x0000001, 0xa8, 0, PutAll },
+        { "TRB",  0x000000c, 0x10, 1, PutAll },
+        { "TSB",  0x000000c, 0x00, 1, PutAll },
+        { "TSX",  0x0000001, 0xba, 0, PutAll },
+        { "TXA",  0x0000001, 0x8a, 0, PutAll },
+        { "TXS",  0x0000001, 0x9a, 0, PutAll },
+        { "TYA",  0x0000001, 0x98, 0, PutAll },
+/* END SORTED.SH */
+    }
+};
+
+/* Instruction table for the W65C02 (CMOS with WDC extensions) */
+static const struct {
+    unsigned Count;
+    InsDesc  Ins[100];
+} InsTabW65C02 = {
+    /* CAUTION: table must be sorted for bsearch */
+    sizeof (InsTabW65C02.Ins) / sizeof (InsTabW65C02.Ins[0]),
+    {
 /* BEGIN SORTED.SH */
         { "ADC",  0x080A66C, 0x60, 0, PutAll },
         { "AND",  0x080A66C, 0x20, 0, PutAll },
@@ -618,6 +729,152 @@ static const struct {
     }
 };
 
+/* Instruction table for the 65CE02 */
+static const struct {
+    unsigned Count;
+    InsDesc  Ins[133];
+} InsTab65CE02 = {
+    /* CAUTION: table must be sorted for bsearch */
+    sizeof (InsTab65CE02.Ins) / sizeof (InsTab65CE02.Ins[0]),
+    {
+/* BEGIN SORTED.SH */
+        { "ADC",  0x080A66C, 0x60, 0, PutAll },
+        { "AND",  0x080A66C, 0x20, 0, PutAll },
+        { "ASL",  0x000006e, 0x02, 1, PutAll },
+        { "ASR",  0x0000026, 0x43, 0, Put4510 },
+        { "ASW",  0x0000008, 0xcb, 6, PutAll },
+        { "AUG",  0x0000001, 0x5C, 0, PutAll },
+        { "BBR0", 0x0000000, 0x0F, 0, PutBitBranch },
+        { "BBR1", 0x0000000, 0x1F, 0, PutBitBranch },
+        { "BBR2", 0x0000000, 0x2F, 0, PutBitBranch },
+        { "BBR3", 0x0000000, 0x3F, 0, PutBitBranch },
+        { "BBR4", 0x0000000, 0x4F, 0, PutBitBranch },
+        { "BBR5", 0x0000000, 0x5F, 0, PutBitBranch },
+        { "BBR6", 0x0000000, 0x6F, 0, PutBitBranch },
+        { "BBR7", 0x0000000, 0x7F, 0, PutBitBranch },
+        { "BBS0", 0x0000000, 0x8F, 0, PutBitBranch },
+        { "BBS1", 0x0000000, 0x9F, 0, PutBitBranch },
+        { "BBS2", 0x0000000, 0xAF, 0, PutBitBranch },
+        { "BBS3", 0x0000000, 0xBF, 0, PutBitBranch },
+        { "BBS4", 0x0000000, 0xCF, 0, PutBitBranch },
+        { "BBS5", 0x0000000, 0xDF, 0, PutBitBranch },
+        { "BBS6", 0x0000000, 0xEF, 0, PutBitBranch },
+        { "BBS7", 0x0000000, 0xFF, 0, PutBitBranch },
+        { "BCC",  0x0020000, 0x90, 0, PutPCRel8 },
+        { "BCS",  0x0020000, 0xb0, 0, PutPCRel8 },
+        { "BEQ",  0x0020000, 0xf0, 0, PutPCRel8 },
+        { "BIT",  0x0A0006C, 0x00, 2, PutAll },
+        { "BMI",  0x0020000, 0x30, 0, PutPCRel8 },
+        { "BNE",  0x0020000, 0xd0, 0, PutPCRel8 },
+        { "BPL",  0x0020000, 0x10, 0, PutPCRel8 },
+        { "BRA",  0x0020000, 0x80, 0, PutPCRel8 },
+        { "BRK",  0x0800005, 0x00, 6, PutAll },
+        { "BSR",  0x0040000, 0x63, 0, PutPCRel4510 },
+        { "BVC",  0x0020000, 0x50, 0, PutPCRel8 },
+        { "BVS",  0x0020000, 0x70, 0, PutPCRel8 },
+        { "CLC",  0x0000001, 0x18, 0, PutAll },
+        { "CLD",  0x0000001, 0xd8, 0, PutAll },
+        { "CLE",  0x0000001, 0x02, 0, PutAll },
+        { "CLI",  0x0000001, 0x58, 0, PutAll },
+        { "CLV",  0x0000001, 0xb8, 0, PutAll },
+        { "CMP",  0x080A66C, 0xc0, 0, PutAll },
+        { "CPX",  0x080000C, 0xe0, 1, PutAll },
+        { "CPY",  0x080000C, 0xc0, 1, PutAll },
+        { "CPZ",  0x080000C, 0xd0, 1, Put4510 },
+        { "DEA",  0x0000001, 0x00, 3, PutAll },   /* == DEC */
+        { "DEC",  0x000006F, 0x00, 3, PutAll },
+        { "DEW",  0x0000004, 0xc3, 9, PutAll },
+        { "DEX",  0x0000001, 0xca, 0, PutAll },
+        { "DEY",  0x0000001, 0x88, 0, PutAll },
+        { "DEZ",  0x0000001, 0x3B, 0, PutAll },
+        { "EOM",  0x0000001, 0xea, 0, PutAll },
+        { "EOR",  0x080A66C, 0x40, 0, PutAll },
+        { "INA",  0x0000001, 0x00, 4, PutAll },   /* == INC */
+        { "INC",  0x000006f, 0x00, 4, PutAll },
+        { "INW",  0x0000004, 0xe3, 9, PutAll },
+        { "INX",  0x0000001, 0xe8, 0, PutAll },
+        { "INY",  0x0000001, 0xc8, 0, PutAll },
+        { "INZ",  0x0000001, 0x1B, 0, PutAll },
+        { "JMP",  0x0010808, 0x4c, 6, PutAll },
+        { "JSR",  0x0010808, 0x20, 7, Put4510 },
+        { "LBCC", 0x0040000, 0x93, 0, PutPCRel4510 },
+        { "LBCS", 0x0040000, 0xb3, 0, PutPCRel4510 },
+        { "LBEQ", 0x0040000, 0xf3, 0, PutPCRel4510 },
+        { "LBMI", 0x0040000, 0x33, 0, PutPCRel4510 },
+        { "LBNE", 0x0040000, 0xd3, 0, PutPCRel4510 },
+        { "LBPL", 0x0040000, 0x13, 0, PutPCRel4510 },
+        { "LBRA", 0x0040000, 0x83, 0, PutPCRel4510 },
+        { "LBVC", 0x0040000, 0x53, 0, PutPCRel4510 },
+        { "LBVS", 0x0040000, 0x73, 0, PutPCRel4510 },
+        { "LDA",  0x090A66C, 0xa0, 0, Put4510 },
+        { "LDX",  0x080030C, 0xa2, 1, PutAll },
+        { "LDY",  0x080006C, 0xa0, 1, PutAll },
+        { "LDZ",  0x0800048, 0xa3, 1, Put4510 },
+        { "LSR",  0x000006F, 0x42, 1, PutAll },
+        { "NEG",  0x0000001, 0x42, 0, PutAll },
+        { "NOP",  0x0000001, 0xea, 0, PutAll }, /* == EOM */
+        { "ORA",  0x080A66C, 0x00, 0, PutAll },
+        { "PHA",  0x0000001, 0x48, 0, PutAll },
+        { "PHD",  0x8000008, 0xf4, 1, PutAll }, /* == PHW */
+        { "PHP",  0x0000001, 0x08, 0, PutAll },
+        { "PHW",  0x8000008, 0xf4, 1, PutAll },
+        { "PHX",  0x0000001, 0xda, 0, PutAll },
+        { "PHY",  0x0000001, 0x5a, 0, PutAll },
+        { "PHZ",  0x0000001, 0xdb, 0, PutAll },
+        { "PLA",  0x0000001, 0x68, 0, PutAll },
+        { "PLP",  0x0000001, 0x28, 0, PutAll },
+        { "PLX",  0x0000001, 0xfa, 0, PutAll },
+        { "PLY",  0x0000001, 0x7a, 0, PutAll },
+        { "PLZ",  0x0000001, 0xfb, 0, PutAll },
+        { "RMB0", 0x0000004, 0x07, 1, PutAll },
+        { "RMB1", 0x0000004, 0x17, 1, PutAll },
+        { "RMB2", 0x0000004, 0x27, 1, PutAll },
+        { "RMB3", 0x0000004, 0x37, 1, PutAll },
+        { "RMB4", 0x0000004, 0x47, 1, PutAll },
+        { "RMB5", 0x0000004, 0x57, 1, PutAll },
+        { "RMB6", 0x0000004, 0x67, 1, PutAll },
+        { "RMB7", 0x0000004, 0x77, 1, PutAll },
+        { "ROL",  0x000006F, 0x22, 1, PutAll },
+        { "ROR",  0x000006F, 0x62, 1, PutAll },
+        { "ROW",  0x0000008, 0xeb, 6, PutAll },
+        { "RTI",  0x0000001, 0x40, 0, PutAll },
+        { "RTN",  0x0800000, 0x62, 1, PutAll },
+        { "RTS",  0x0000001, 0x60, 0, PutAll },
+        { "SBC",  0x080A66C, 0xe0, 0, PutAll },
+        { "SEC",  0x0000001, 0x38, 0, PutAll },
+        { "SED",  0x0000001, 0xf8, 0, PutAll },
+        { "SEE",  0x0000001, 0x03, 0, PutAll },
+        { "SEI",  0x0000001, 0x78, 0, PutAll },
+        { "SMB0", 0x0000004, 0x87, 1, PutAll },
+        { "SMB1", 0x0000004, 0x97, 1, PutAll },
+        { "SMB2", 0x0000004, 0xA7, 1, PutAll },
+        { "SMB3", 0x0000004, 0xB7, 1, PutAll },
+        { "SMB4", 0x0000004, 0xC7, 1, PutAll },
+        { "SMB5", 0x0000004, 0xD7, 1, PutAll },
+        { "SMB6", 0x0000004, 0xE7, 1, PutAll },
+        { "SMB7", 0x0000004, 0xF7, 1, PutAll },
+        { "STA",  0x010A66C, 0x80, 0, Put4510 },
+        { "STX",  0x000030c, 0x82, 1, Put4510 },
+        { "STY",  0x000006c, 0x80, 1, Put4510 },
+        { "STZ",  0x000006c, 0x04, 5, PutAll },
+        { "TAB",  0x0000001, 0x5b, 0, PutAll },
+        { "TAX",  0x0000001, 0xaa, 0, PutAll },
+        { "TAY",  0x0000001, 0xa8, 0, PutAll },
+        { "TAZ",  0x0000001, 0x4b, 0, PutAll },
+        { "TBA",  0x0000001, 0x7b, 0, PutAll },
+        { "TRB",  0x000000c, 0x10, 1, PutAll },
+        { "TSB",  0x000000c, 0x00, 1, PutAll },
+        { "TSX",  0x0000001, 0xba, 0, PutAll },
+        { "TSY",  0x0000001, 0x0b, 0, PutAll },
+        { "TXA",  0x0000001, 0x8a, 0, PutAll },
+        { "TXS",  0x0000001, 0x9a, 0, PutAll },
+        { "TYA",  0x0000001, 0x98, 0, PutAll },
+        { "TYS",  0x0000001, 0x2b, 0, PutAll },
+        { "TZA",  0x0000001, 0x6b, 0, PutAll },
+/* END SORTED.SH */
+    }
+};
+
 /* Instruction table for the 4510 */
 static const struct {
     unsigned Count;
@@ -1355,14 +1612,16 @@ static const InsTable* InsTabs[CPU_COUNT] = {
     (const InsTable*) &InsTab6502,
     (const InsTable*) &InsTab6502X,
     (const InsTable*) &InsTab6502DTV,
-    (const InsTable*) &InsTab65SC02,
-    (const InsTable*) &InsTab65C02,
+    (const InsTable*) &InsTab65SC02,        /* original CMOS */
+    (const InsTable*) &InsTab65C02,         /* CMOS with Rockwell extensions */
     (const InsTable*) &InsTab65816,
     (const InsTable*) &InsTabSweet16,
     (const InsTable*) &InsTabHuC6280,
-    (const InsTable*) &InsTabm740,           /* Mitsubishi 740 */
+    (const InsTable*) &InsTabm740,          /* Mitsubishi 740 */
     (const InsTable*) &InsTab4510,
     (const InsTable*) &InsTab45GS02,
+    (const InsTable*) &InsTabW65C02,        /* CMOS with WDC extensions */
+    (const InsTable*) &InsTab65CE02,        /* CMOS with CSG extensions */
 };
 const InsTable* InsTab = (const InsTable*) &InsTab6502;
 
diff --git a/src/ca65/pseudo.c b/src/ca65/pseudo.c
index 7e52ecb5e..e6e10df2c 100644
--- a/src/ca65/pseudo.c
+++ b/src/ca65/pseudo.c
@@ -1578,10 +1578,18 @@ static void DoPC02 (void)
 
 
 
-static void DoP816 (void)
-/* Switch to 65816 CPU */
+static void DoPWC02 (void)
+/* Switch to W65C02 CPU */
 {
-    SetCPU (CPU_65816);
+    SetCPU (CPU_W65C02);
+}
+
+
+
+static void DoPCE02 (void)
+/* Switch to 65CE02 CPU */
+{
+    SetCPU (CPU_65CE02);
 }
 
 
@@ -1602,6 +1610,22 @@ static void DoP45GS02 (void)
 
 
 
+static void DoP6280 (void)
+/* Switch to HuC6280 CPU */
+{
+    SetCPU (CPU_HUC6280);
+}
+
+
+
+static void DoP816 (void)
+/* Switch to 65816 CPU */
+{
+    SetCPU (CPU_65816);
+}
+
+
+
 static void DoPDTV (void)
 /* Switch to C64DTV CPU */
 {
@@ -1728,6 +1752,14 @@ static void DoPSC02 (void)
 
 
 
+static void DoPSweet16 (void)
+/* Switch to Sweet16 CPU */
+{
+    SetCPU (CPU_SWEET16);
+}
+
+
+
 static void DoPushCharmap (void)
 /* Save the current charmap */
 {
@@ -2160,11 +2192,15 @@ static CtrlDesc CtrlCmdTab [] = {
     { ccKeepToken,      DoConditionals  },      /* .IFP02X */
     { ccKeepToken,      DoConditionals  },      /* .IFP4510 */
     { ccKeepToken,      DoConditionals  },      /* .IFP45GS02 */
+    { ccKeepToken,      DoConditionals  },      /* .IFP6280 */
     { ccKeepToken,      DoConditionals  },      /* .IFP816 */
     { ccKeepToken,      DoConditionals  },      /* .IFPC02 */
+    { ccKeepToken,      DoConditionals  },      /* .IFPCE02 */
     { ccKeepToken,      DoConditionals  },      /* .IFPDTV */
     { ccKeepToken,      DoConditionals  },      /* .IFPM740 */
     { ccKeepToken,      DoConditionals  },      /* .IFPSC02 */
+    { ccKeepToken,      DoConditionals  },      /* .IFPSWEET16 */
+    { ccKeepToken,      DoConditionals  },      /* .IFPWC02 */
     { ccKeepToken,      DoConditionals  },      /* .IFREF */
     { ccNone,           DoImport        },      /* .IMPORT */
     { ccNone,           DoImportZP      },      /* .IMPORTZP */
@@ -2196,10 +2232,12 @@ static CtrlDesc CtrlCmdTab [] = {
     { ccNone,           DoP02X          },      /* .P02X */
     { ccNone,           DoP4510         },      /* .P4510 */
     { ccNone,           DoP45GS02       },      /* .P45GS02 */
+    { ccNone,           DoP6280         },      /* .P6280 */
     { ccNone,           DoP816          },      /* .P816 */
     { ccNone,           DoPageLength    },      /* .PAGELEN, .PAGELENGTH */
     { ccNone,           DoUnexpected    },      /* .PARAMCOUNT */
-    { ccNone,           DoPC02          },      /* .PSC02 */
+    { ccNone,           DoPC02          },      /* .PC02 */
+    { ccNone,           DoPCE02         },      /* .PCE02 */
     { ccNone,           DoPDTV          },      /* .PDTV */
     { ccNone,           DoPM740         },      /* .PM740 */
     { ccNone,           DoPopCharmap    },      /* .POPCHARMAP */
@@ -2207,9 +2245,11 @@ static CtrlDesc CtrlCmdTab [] = {
     { ccNone,           DoPopSeg        },      /* .POPSEG */
     { ccNone,           DoProc          },      /* .PROC */
     { ccNone,           DoPSC02         },      /* .PSC02 */
+    { ccNone,           DoPSweet16      },      /* .PSWEET16 */
     { ccNone,           DoPushCharmap   },      /* .PUSHCHARMAP */
     { ccNone,           DoPushCPU       },      /* .PUSHCPU */
     { ccNone,           DoPushSeg       },      /* .PUSHSEG */
+    { ccNone,           DoPWC02         },      /* .PWC02 */
     { ccNone,           DoUnexpected    },      /* .REF, .REFERENCED */
     { ccNone,           DoReferTo       },      /* .REFTO, .REFERTO */
     { ccNone,           DoReloc         },      /* .RELOC */
diff --git a/src/ca65/scanner.c b/src/ca65/scanner.c
index dd0209856..f3892d32e 100644
--- a/src/ca65/scanner.c
+++ b/src/ca65/scanner.c
@@ -224,11 +224,15 @@ struct DotKeyword {
     { ".IFP02X",        TOK_IFP02X              },
     { ".IFP4510",       TOK_IFP4510             },
     { ".IFP45GS02",     TOK_IFP45GS02           },
+    { ".IFP6280",       TOK_IFP6280             },
     { ".IFP816",        TOK_IFP816              },
     { ".IFPC02",        TOK_IFPC02              },
+    { ".IFPCE02",       TOK_IFPCE02             },
     { ".IFPDTV",        TOK_IFPDTV              },
     { ".IFPM740",       TOK_IFPM740             },
     { ".IFPSC02",       TOK_IFPSC02             },
+    { ".IFPSWEET16",    TOK_IFPSWEET16          },
+    { ".IFPWC02",       TOK_IFPWC02             },
     { ".IFREF",         TOK_IFREF               },
     { ".IMPORT",        TOK_IMPORT              },
     { ".IMPORTZP",      TOK_IMPORTZP            },
@@ -265,11 +269,13 @@ struct DotKeyword {
     { ".P02X",          TOK_P02X                },
     { ".P4510",         TOK_P4510               },
     { ".P45GS02",       TOK_P45GS02             },
+    { ".P6280",         TOK_P6280               },
     { ".P816",          TOK_P816                },
     { ".PAGELEN",       TOK_PAGELENGTH          },
     { ".PAGELENGTH",    TOK_PAGELENGTH          },
     { ".PARAMCOUNT",    TOK_PARAMCOUNT          },
     { ".PC02",          TOK_PC02                },
+    { ".PCE02",         TOK_PCE02               },
     { ".PDTV",          TOK_PDTV                },
     { ".PM740",         TOK_PM740               },
     { ".POPCHARMAP",    TOK_POPCHARMAP          },
@@ -277,9 +283,11 @@ struct DotKeyword {
     { ".POPSEG",        TOK_POPSEG              },
     { ".PROC",          TOK_PROC                },
     { ".PSC02",         TOK_PSC02               },
+    { ".PSWEET16",      TOK_PSWEET16            },
     { ".PUSHCHARMAP",   TOK_PUSHCHARMAP         },
     { ".PUSHCPU",       TOK_PUSHCPU             },
     { ".PUSHSEG",       TOK_PUSHSEG             },
+    { ".PWC02",         TOK_PWC02               },
     { ".REF",           TOK_REFERENCED          },
     { ".REFERENCED",    TOK_REFERENCED          },
     { ".REFERTO",       TOK_REFERTO             },
@@ -1281,7 +1289,7 @@ Again:
                         break;
 
                     case 'S':
-                        if ((CPU == CPU_4510) || (CPU == CPU_45GS02) || (CPU == CPU_65816)) {
+                        if ((CPU == CPU_65CE02) || (CPU == CPU_4510) || (CPU == CPU_45GS02) || (CPU == CPU_65816)) {
                             CurTok.Tok = TOK_S;
                             return;
                         }
@@ -1308,7 +1316,7 @@ Again:
                             CurTok.Tok = TOK_OVERRIDE_ZP;
                            return;
                         } else {
-                            if ((CPU == CPU_4510) || (CPU == CPU_45GS02)) {
+                            if ((CPU == CPU_65CE02) || (CPU == CPU_4510) || (CPU == CPU_45GS02)) {
                                 CurTok.Tok = TOK_Z;
                                 return;
                             }
@@ -1320,7 +1328,8 @@ Again:
                 }
                 break;
             case 2:
-                if ((CPU == CPU_4510 || CPU == CPU_45GS02) &&
+                /* FIXME: make sure we only alias "sp" to "s" when its really needed */
+                if (((CPU == CPU_65CE02) || (CPU == CPU_4510) || (CPU == CPU_45GS02)) &&
                     (toupper (SB_AtUnchecked (&CurTok.SVal, 0)) == 'S') &&
                     (toupper (SB_AtUnchecked (&CurTok.SVal, 1)) == 'P')) {
 
diff --git a/src/ca65/token.h b/src/ca65/token.h
index 9ca7ea657..e2b223880 100644
--- a/src/ca65/token.h
+++ b/src/ca65/token.h
@@ -197,11 +197,15 @@ typedef enum token_t {
     TOK_IFP02X,
     TOK_IFP4510,
     TOK_IFP45GS02,
+    TOK_IFP6280,
     TOK_IFP816,
     TOK_IFPC02,
+    TOK_IFPCE02,
     TOK_IFPDTV,
     TOK_IFPM740,
     TOK_IFPSC02,
+    TOK_IFPSWEET16,
+    TOK_IFPWC02,
     TOK_IFREF,
     TOK_IMPORT,
     TOK_IMPORTZP,
@@ -233,10 +237,12 @@ typedef enum token_t {
     TOK_P02X,
     TOK_P4510,
     TOK_P45GS02,
+    TOK_P6280,
     TOK_P816,
     TOK_PAGELENGTH,
     TOK_PARAMCOUNT,
     TOK_PC02,
+    TOK_PCE02,
     TOK_PDTV,
     TOK_PM740,
     TOK_POPCHARMAP,
@@ -244,9 +250,11 @@ typedef enum token_t {
     TOK_POPSEG,
     TOK_PROC,
     TOK_PSC02,
+    TOK_PSWEET16,
     TOK_PUSHCHARMAP,
     TOK_PUSHCPU,
     TOK_PUSHSEG,
+    TOK_PWC02,
     TOK_REFERENCED,
     TOK_REFERTO,
     TOK_RELOC,
diff --git a/src/cc65/codegen.c b/src/cc65/codegen.c
index 42be0099a..04340af67 100644
--- a/src/cc65/codegen.c
+++ b/src/cc65/codegen.c
@@ -200,6 +200,8 @@ void g_preamble (void)
         case CPU_6502DTV:   AddTextLine ("\t.setcpu\t\t\"6502DTV\"");   break;
         case CPU_65SC02:    AddTextLine ("\t.setcpu\t\t\"65SC02\"");    break;
         case CPU_65C02:     AddTextLine ("\t.setcpu\t\t\"65C02\"");     break;
+        case CPU_W65C02:    AddTextLine ("\t.setcpu\t\t\"W65C02\"");    break;
+        case CPU_65CE02:    AddTextLine ("\t.setcpu\t\t\"65CE02\"");    break;
         case CPU_65816:     AddTextLine ("\t.setcpu\t\t\"65816\"");     break;
         case CPU_HUC6280:   AddTextLine ("\t.setcpu\t\t\"HUC6280\"");   break;
         case CPU_4510:      AddTextLine ("\t.setcpu\t\t\"4510\"");      break;
diff --git a/src/cc65/main.c b/src/cc65/main.c
index 648c603cd..5fc6ea343 100644
--- a/src/cc65/main.c
+++ b/src/cc65/main.c
@@ -373,10 +373,18 @@ static void DefineCpuMacros (void)
             DefineNumericMacro ("__CPU_65C02__", 1);
             break;
 
+        case CPU_65CE02:
+            DefineNumericMacro ("__CPU_65CE02__", 1);
+            break;
+
         case CPU_65816:
             DefineNumericMacro ("__CPU_65816__", 1);
             break;
 
+        case CPU_W65C02:
+            DefineNumericMacro ("__CPU_W65C02__", 1);
+            break;
+
         case CPU_HUC6280:
             DefineNumericMacro ("__CPU_HUC6280__", 1);
             break;
@@ -402,6 +410,8 @@ static void DefineCpuMacros (void)
     DefineNumericMacro ("__CPU_ISET_6502DTV__", CPU_ISET_6502DTV);
     DefineNumericMacro ("__CPU_ISET_65SC02__", CPU_ISET_65SC02);
     DefineNumericMacro ("__CPU_ISET_65C02__", CPU_ISET_65C02);
+    DefineNumericMacro ("__CPU_ISET_W65C02__", CPU_ISET_W65C02);
+    DefineNumericMacro ("__CPU_ISET_65CE02__", CPU_ISET_65CE02);
     DefineNumericMacro ("__CPU_ISET_65816__", CPU_ISET_65816);
     DefineNumericMacro ("__CPU_ISET_HUC6280__", CPU_ISET_HUC6280);
     DefineNumericMacro ("__CPU_ISET_4510__", CPU_ISET_4510);
diff --git a/src/common/cpu.c b/src/common/cpu.c
index 54bb8a3fb..252283211 100644
--- a/src/common/cpu.c
+++ b/src/common/cpu.c
@@ -56,14 +56,16 @@ const char* CPUNames[CPU_COUNT] = {
     "6502",
     "6502X",
     "6502DTV",
-    "65SC02",
-    "65C02",
+    "65SC02",   /* the original CMOS instruction set */
+    "65C02",    /* CMOS with Rockwell extensions */
     "65816",
     "sweet16",
     "huc6280",
     "m740",
     "4510",
-    "45GS02"
+    "45GS02",
+    "W65C02",   /* CMOS with WDC extensions */
+    "65CE02",   /* CMOS with CSG extensions */
 };
 
 /* Tables with CPU instruction sets
@@ -76,16 +78,16 @@ const unsigned CPUIsets[CPU_COUNT] = {
     CPU_ISET_6502DTV | CPU_ISET_6502,
     CPU_ISET_65SC02  | CPU_ISET_6502,
     CPU_ISET_65C02   | CPU_ISET_6502 | CPU_ISET_65SC02,
-    /* FIXME: does 65816 have both wai/stp and indirect-zp (without z)? */
-    CPU_ISET_65816   | CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02,
+    /* 65816 has wai/stp and NO bit manipulation */
+    CPU_ISET_65816   | CPU_ISET_6502 | CPU_ISET_65SC02,
     CPU_ISET_SWEET16,
-    /* FIXME: HUC6280 does not have wai/stp */
     CPU_ISET_HUC6280 | CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02,
     CPU_ISET_M740    | CPU_ISET_6502,
     /* 4510 does NOT have indirect-zp (without z), so we can not use 65SC02 */
-    /* FIXME: 4510 does not have wai/stp */
-    CPU_ISET_4510    | CPU_ISET_6502 |  CPU_ISET_65C02,
-    CPU_ISET_45GS02  | CPU_ISET_6502 |  CPU_ISET_65C02 | CPU_ISET_4510,
+    CPU_ISET_4510    | CPU_ISET_6502                   | CPU_ISET_65C02 | CPU_ISET_65CE02,
+    CPU_ISET_45GS02  | CPU_ISET_6502                   | CPU_ISET_65C02 | CPU_ISET_65CE02 | CPU_ISET_4510,
+    CPU_ISET_W65C02  | CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02,
+    CPU_ISET_65CE02  | CPU_ISET_6502                   | CPU_ISET_65C02,
 };
 
 
diff --git a/src/common/cpu.h b/src/common/cpu.h
index 81795e146..4202ed573 100644
--- a/src/common/cpu.h
+++ b/src/common/cpu.h
@@ -51,14 +51,16 @@ typedef enum {
     CPU_6502,
     CPU_6502X,                  /* "Extended", that is: with illegal opcodes */
     CPU_6502DTV,                /* CPU_6502 + DTV extra and illegal opcodes */
-    CPU_65SC02,
-    CPU_65C02,
+    CPU_65SC02,                 /* the original CMOS instruction set */
+    CPU_65C02,                  /* CMOS with Rockwell extensions */
     CPU_65816,
     CPU_SWEET16,
     CPU_HUC6280,                /* Used in PC engine */
     CPU_M740,                   /* Mitsubishi 740 series MCUs */
     CPU_4510,                   /* CPU of C65 */
     CPU_45GS02,                 /* CPU of MEGA65 */
+    CPU_W65C02,                 /* CMOS with WDC extensions */
+    CPU_65CE02,                 /* CMOS with CSG extensions */
     CPU_COUNT                   /* Number of different CPUs */
 } cpu_t;
 
@@ -75,7 +77,9 @@ enum {
     CPU_ISET_HUC6280    = 1 << CPU_HUC6280,
     CPU_ISET_M740       = 1 << CPU_M740,
     CPU_ISET_4510       = 1 << CPU_4510,
-    CPU_ISET_45GS02     = 1 << CPU_45GS02
+    CPU_ISET_45GS02     = 1 << CPU_45GS02,
+    CPU_ISET_W65C02     = 1 << CPU_W65C02,
+    CPU_ISET_65CE02     = 1 << CPU_65CE02
 };
 
 /* CPU used */
diff --git a/src/common/target.c b/src/common/target.c
index 51e015adc..a12f69bf9 100644
--- a/src/common/target.c
+++ b/src/common/target.c
@@ -246,7 +246,7 @@ static const TargetProperties PropertyTable[TGT_COUNT] = {
     { "sym1",           CPU_6502,       BINFMT_BINARY,      CTNone  },
     { "mega65",         CPU_45GS02,     BINFMT_BINARY,      CTPET   },
     { "kim1",           CPU_6502,       BINFMT_BINARY,      CTNone  },
-    { "rp6502",         CPU_65C02,      BINFMT_BINARY,      CTNone  },
+    { "rp6502",         CPU_W65C02,     BINFMT_BINARY,      CTNone  },
     { "agat",           CPU_6502,       BINFMT_BINARY,      CTAgat  },
 };
 
diff --git a/src/da65.vcxproj b/src/da65.vcxproj
index 6610f907c..65dc3fccf 100644
--- a/src/da65.vcxproj
+++ b/src/da65.vcxproj
@@ -101,6 +101,8 @@
     <ClCompile Include="da65\opc65816.c" />
     <ClCompile Include="da65\opc65c02.c" />
     <ClCompile Include="da65\opc65sc02.c" />
+    <ClCompile Include="da65\opc65ce02.c" />
+    <ClCompile Include="da65\opcw65c02.c" />
     <ClCompile Include="da65\opchuc6280.c" />
     <ClCompile Include="da65\opcm740.c" />
     <ClCompile Include="da65\opctable.c" />
diff --git a/src/da65/opc65c02.c b/src/da65/opc65c02.c
index b69558f2a..88c8c8dec 100644
--- a/src/da65/opc65c02.c
+++ b/src/da65/opc65c02.c
@@ -250,7 +250,7 @@ const OpcDesc OpcTable_65C02[256] = {
     {   "iny",  1,  flNone,                   OH_Implicit              }, /* $c8 */
     {   "cmp",  2,  flNone,                   OH_Immediate             }, /* $c9 */
     {   "dex",  1,  flNone,                   OH_Implicit              }, /* $ca */
-    {   "wai",  1,  flNone,                   OH_Implicit              }, /* $cb */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $cb */
     {   "cpy",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $cc */
     {   "cmp",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $cd */
     {   "dec",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ce */
@@ -266,7 +266,7 @@ const OpcDesc OpcTable_65C02[256] = {
     {   "cld",  1,  flNone,                   OH_Implicit              }, /* $d8 */
     {   "cmp",  3,  flUseLabel,               OH_AbsoluteY             }, /* $d9 */
     {   "phx",  1,  flNone,                   OH_Implicit              }, /* $da */
-    {   "stp",  1,  flNone,                   OH_Implicit              }, /* $db */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $db */
     {   "",     1,  flIllegal,                OH_Illegal,              }, /* $dc */
     {   "cmp",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $dd */
     {   "dec",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $de */
diff --git a/src/da65/opc65ce02.c b/src/da65/opc65ce02.c
new file mode 100644
index 000000000..093e79a9e
--- /dev/null
+++ b/src/da65/opc65ce02.c
@@ -0,0 +1,306 @@
+/*****************************************************************************/
+/*                                                                           */
+/*                               opc65CE02.c                                 */
+/*                                                                           */
+/*                      65CE02 opcode description table                      */
+/*                                                                           */
+/*                                                                           */
+/*                                                                           */
+/* (C) 2003-2011, Ullrich von Bassewitz                                      */
+/*                Roemerstrasse 52                                           */
+/*                D-70794 Filderstadt                                        */
+/* EMail:         uz@cc65.org                                                */
+/*                                                                           */
+/*                                                                           */
+/* This software is provided 'as-is', without any expressed or implied       */
+/* warranty.  In no event will the authors be held liable for any damages    */
+/* arising from the use of this software.                                    */
+/*                                                                           */
+/* Permission is granted to anyone to use this software for any purpose,     */
+/* including commercial applications, and to alter it and redistribute it    */
+/* freely, subject to the following restrictions:                            */
+/*                                                                           */
+/* 1. The origin of this software must not be misrepresented; you must not   */
+/*    claim that you wrote the original software. If you use this software   */
+/*    in a product, an acknowledgment in the product documentation would be  */
+/*    appreciated but is not required.                                       */
+/* 2. Altered source versions must be plainly marked as such, and must not   */
+/*    be misrepresented as being the original software.                      */
+/* 3. This notice may not be removed or altered from any source              */
+/*    distribution.                                                          */
+/*                                                                           */
+/*****************************************************************************/
+
+
+
+/* da65 */
+#include "handler.h"
+#include "opc65ce02.h"
+
+
+
+/*****************************************************************************/
+/*                                   Data                                    */
+/*****************************************************************************/
+
+
+
+/* Descriptions for all opcodes */
+const OpcDesc OpcTable_65CE02[256] = {
+    {   "brk",  1,  flNone,                   OH_Implicit                  }, /* $00 */
+    {   "ora",  2,  flUseLabel,               OH_DirectXIndirect           }, /* $01 */
+    {   "cle",  1,  flNone,                   OH_Implicit                  }, /* $02 */
+    {   "see",  1,  flNone,                   OH_Implicit                  }, /* $03 */
+    {   "tsb",  2,  flUseLabel,               OH_Direct                    }, /* $04 */
+    {   "ora",  2,  flUseLabel,               OH_Direct                    }, /* $05 */
+    {   "asl",  2,  flUseLabel,               OH_Direct                    }, /* $06 */
+    {   "rmb0", 2,  flUseLabel,               OH_Direct                    }, /* $07 */
+    {   "php",  1,  flNone,                   OH_Implicit                  }, /* $08 */
+    {   "ora",  2,  flNone,                   OH_Immediate                 }, /* $09 */
+    {   "asl",  1,  flNone,                   OH_Accumulator               }, /* $0a */
+    {   "tsy",  1,  flNone,                   OH_Implicit                  }, /* $0b */
+    {   "tsb",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $0c */
+    {   "ora",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $0d */
+    {   "asl",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $0e */
+    {   "bbr0", 3,  flUseLabel,               OH_BitBranch                 }, /* $0f */
+    {   "bpl",  2,  flLabel,                  OH_Relative                  }, /* $10 */
+    {   "ora",  2,  flUseLabel,               OH_DirectIndirectY           }, /* $11 */
+    {   "ora",  2,  flUseLabel,               OH_DirectIndirectZ           }, /* $12 */
+    {   "lbpl", 3,  flLabel,                  OH_RelativeLong4510          }, /* $13 */
+    {   "trb",  2,  flUseLabel,               OH_Direct                    }, /* $14 */
+    {   "ora",  2,  flUseLabel,               OH_DirectX                   }, /* $15 */
+    {   "asl",  2,  flUseLabel,               OH_DirectX                   }, /* $16 */
+    {   "rmb1", 2,  flUseLabel,               OH_Direct                    }, /* $17 */
+    {   "clc",  1,  flNone,                   OH_Implicit                  }, /* $18 */
+    {   "ora",  3,  flUseLabel,               OH_AbsoluteY                 }, /* $19 */
+    {   "inc",  1,  flNone,                   OH_Accumulator               }, /* $1a */
+    {   "inz",  1,  flNone,                   OH_Implicit                  }, /* $1b */
+    {   "trb",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $1c */
+    {   "ora",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $1d */
+    {   "asl",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $1e */
+    {   "bbr1", 3,  flUseLabel,               OH_BitBranch                 }, /* $1f */
+    {   "jsr",  3,  flLabel,                  OH_Absolute                  }, /* $20 */
+    {   "and",  2,  flUseLabel,               OH_DirectXIndirect           }, /* $21 */
+    {   "jsr",  3,  flLabel,                  OH_JmpAbsoluteIndirect       }, /* $22 */
+    {   "jsr",  3,  flLabel,                  OH_JmpAbsoluteXIndirect      }, /* $23 */
+    {   "bit",  2,  flUseLabel,               OH_Direct                    }, /* $24 */
+    {   "and",  2,  flUseLabel,               OH_Direct                    }, /* $25 */
+    {   "rol",  2,  flUseLabel,               OH_Direct                    }, /* $26 */
+    {   "rmb2", 2,  flUseLabel,               OH_Direct                    }, /* $27 */
+    {   "plp",  1,  flNone,                   OH_Implicit                  }, /* $28 */
+    {   "and",  2,  flNone,                   OH_Immediate                 }, /* $29 */
+    {   "rol",  1,  flNone,                   OH_Accumulator               }, /* $2a */
+    {   "tys",  1,  flNone,                   OH_Implicit                  }, /* $2b */
+    {   "bit",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $2c */
+    {   "and",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $2d */
+    {   "rol",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $2e */
+    {   "bbr2", 3,  flUseLabel,               OH_BitBranch                 }, /* $2f */
+    {   "bmi",  2,  flLabel,                  OH_Relative                  }, /* $30 */
+    {   "and",  2,  flUseLabel,               OH_DirectIndirectY           }, /* $31 */
+    {   "and",  2,  flUseLabel,               OH_DirectIndirectZ           }, /* $32 */
+    {   "lbmi", 3,  flLabel,                  OH_RelativeLong4510          }, /* $33 */
+    {   "bit",  2,  flUseLabel,               OH_DirectX                   }, /* $34 */
+    {   "and",  2,  flUseLabel,               OH_DirectX                   }, /* $35 */
+    {   "rol",  2,  flUseLabel,               OH_DirectX                   }, /* $36 */
+    {   "rmb3", 2,  flUseLabel,               OH_Direct                    }, /* $37 */
+    {   "sec",  1,  flNone,                   OH_Implicit                  }, /* $38 */
+    {   "and",  3,  flUseLabel,               OH_AbsoluteY                 }, /* $39 */
+    {   "dec",  1,  flNone,                   OH_Accumulator               }, /* $3a */
+    {   "dez",  1,  flNone,                   OH_Implicit                  }, /* $3b */
+    {   "bit",  3,  flUseLabel,               OH_AbsoluteX                 }, /* $3c */
+    {   "and",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $3d */
+    {   "rol",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $3e */
+    {   "bbr3", 3,  flUseLabel,               OH_BitBranch                 }, /* $3f */
+    {   "rti",  1,  flNone,                   OH_Rts                       }, /* $40 */
+    {   "eor",  2,  flUseLabel,               OH_DirectXIndirect           }, /* $41 */
+    {   "neg",  1,  flNone,                   OH_Implicit                  }, /* $42 */
+    {   "asr",  1,  flNone,                   OH_Accumulator               }, /* $43 */
+    {   "asr",  2,  flUseLabel,               OH_Direct                    }, /* $44 */
+    {   "eor",  2,  flUseLabel,               OH_Direct                    }, /* $45 */
+    {   "lsr",  2,  flUseLabel,               OH_Direct                    }, /* $46 */
+    {   "rmb4", 2,  flUseLabel,               OH_Direct                    }, /* $47 */
+    {   "pha",  1,  flNone,                   OH_Implicit                  }, /* $48 */
+    {   "eor",  2,  flNone,                   OH_Immediate                 }, /* $49 */
+    {   "lsr",  1,  flNone,                   OH_Accumulator               }, /* $4a */
+    {   "taz",  1,  flNone,                   OH_Implicit                  }, /* $4b */
+    {   "jmp",  3,  flLabel,                  OH_JmpAbsolute               }, /* $4c */
+    {   "eor",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $4d */
+    {   "lsr",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $4e */
+    {   "bbr4", 3,  flUseLabel,               OH_BitBranch                 }, /* $4f */
+    {   "bvc",  2,  flLabel,                  OH_Relative                  }, /* $50 */
+    {   "eor",  2,  flUseLabel,               OH_DirectIndirectY           }, /* $51 */
+    {   "eor",  2,  flUseLabel,               OH_DirectIndirectZ           }, /* $52 */
+    {   "lbvc", 3,  flLabel,                  OH_RelativeLong4510          }, /* $53 */
+    {   "asr",  2,  flUseLabel,               OH_DirectX                   }, /* $54 */
+    {   "eor",  2,  flUseLabel,               OH_DirectX                   }, /* $55 */
+    {   "lsr",  2,  flUseLabel,               OH_DirectX                   }, /* $56 */
+    {   "rmb5", 2,  flUseLabel,               OH_Direct                    }, /* $57 */
+    {   "cli",  1,  flNone,                   OH_Implicit                  }, /* $58 */
+    {   "eor",  3,  flUseLabel,               OH_AbsoluteY                 }, /* $59 */
+    {   "phy",  1,  flNone,                   OH_Implicit                  }, /* $5a */
+    {   "tab",  1,  flNone,                   OH_Implicit                  }, /* $5b */
+    {   "aug",  1,  flNone,                   OH_Implicit                  }, /* $5c */
+    {   "eor",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $5d */
+    {   "lsr",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $5e */
+    {   "bbr5", 3,  flUseLabel,               OH_BitBranch                 }, /* $5f */
+    {   "rts",  1,  flNone,                   OH_Rts                       }, /* $60 */
+    {   "adc",  2,  flUseLabel,               OH_DirectXIndirect           }, /* $61 */
+    {   "rtn",  2,  flNone,                   OH_Immediate                 }, /* $62 */
+    {   "bsr",  3,  flLabel,                  OH_RelativeLong4510          }, /* $63 */
+    {   "stz",  2,  flUseLabel,               OH_Direct                    }, /* $64 */
+    {   "adc",  2,  flUseLabel,               OH_Direct                    }, /* $65 */
+    {   "ror",  2,  flUseLabel,               OH_Direct                    }, /* $66 */
+    {   "rmb6", 2,  flUseLabel,               OH_Direct,                   }, /* $67 */
+    {   "pla",  1,  flNone,                   OH_Implicit                  }, /* $68 */
+    {   "adc",  2,  flNone,                   OH_Immediate                 }, /* $69 */
+    {   "ror",  1,  flNone,                   OH_Accumulator               }, /* $6a */
+    {   "tza",  1,  flNone,                   OH_Implicit                  }, /* $6b */
+    {   "jmp",  3,  flLabel,                  OH_JmpAbsoluteIndirect       }, /* $6c */
+    {   "adc",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $6d */
+    {   "ror",  3,  flUseLabel,               OH_Absolute                  }, /* $6e */
+    {   "bbr6", 3,  flUseLabel,               OH_BitBranch                 }, /* $6f */
+    {   "bvs",  2,  flLabel,                  OH_Relative                  }, /* $70 */
+    {   "adc",  2,  flUseLabel,               OH_DirectIndirectY           }, /* $71 */
+    {   "adc",  2,  flUseLabel,               OH_DirectIndirectZ           }, /* $72 */
+    {   "lbvs", 3,  flLabel,                  OH_RelativeLong4510          }, /* $73 */
+    {   "stz",  2,  flUseLabel,               OH_DirectX                   }, /* $74 */
+    {   "adc",  2,  flUseLabel,               OH_DirectX                   }, /* $75 */
+    {   "ror",  2,  flUseLabel,               OH_DirectX                   }, /* $76 */
+    {   "rmb7", 2,  flUseLabel,               OH_Direct                    }, /* $77 */
+    {   "sei",  1,  flNone,                   OH_Implicit                  }, /* $78 */
+    {   "adc",  3,  flUseLabel,               OH_AbsoluteY                 }, /* $79 */
+    {   "ply",  1,  flNone,                   OH_Implicit                  }, /* $7a */
+    {   "tba",  1,  flNone,                   OH_Implicit                  }, /* $7b */
+    {   "jmp",  3,  flLabel,                  OH_AbsoluteXIndirect         }, /* $7c */
+    {   "adc",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $7d */
+    {   "ror",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $7e */
+    {   "bbr7", 3,  flUseLabel,               OH_BitBranch                 }, /* $7f */
+    {   "bra",  2,  flLabel,                  OH_Relative                  }, /* $80 */
+    {   "sta",  2,  flUseLabel,               OH_DirectXIndirect           }, /* $81 */
+    {   "sta",  2,  flNone,                   OH_StackRelativeIndirectY4510}, /* $82 */
+    {   "lbra", 3,  flLabel,                  OH_RelativeLong4510          }, /* $83 */
+    {   "sty",  2,  flUseLabel,               OH_Direct                    }, /* $84 */
+    {   "sta",  2,  flUseLabel,               OH_Direct                    }, /* $85 */
+    {   "stx",  2,  flUseLabel,               OH_Direct                    }, /* $86 */
+    {   "smb0", 2,  flUseLabel,               OH_Direct                    }, /* $87 */
+    {   "dey",  1,  flNone,                   OH_Implicit                  }, /* $88 */
+    {   "bit",  2,  flNone,                   OH_Immediate                 }, /* $89 */
+    {   "txa",  1,  flNone,                   OH_Implicit                  }, /* $8a */
+    {   "sty",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $8b */
+    {   "sty",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $8c */
+    {   "sta",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $8d */
+    {   "stx",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $8e */
+    {   "bbs0", 3,  flUseLabel,               OH_BitBranch                 }, /* $8f */
+    {   "bcc",  2,  flLabel,                  OH_Relative                  }, /* $90 */
+    {   "sta",  2,  flUseLabel,               OH_DirectIndirectY           }, /* $91 */
+    {   "sta",  2,  flUseLabel,               OH_DirectIndirectZ           }, /* $92 */
+    {   "lbcc", 3,  flLabel,                  OH_RelativeLong4510          }, /* $93 */
+    {   "sty",  2,  flUseLabel,               OH_DirectX                   }, /* $94 */
+    {   "sta",  2,  flUseLabel,               OH_DirectX                   }, /* $95 */
+    {   "stx",  2,  flUseLabel,               OH_DirectY                   }, /* $96 */
+    {   "smb1", 2,  flUseLabel,               OH_Direct                    }, /* $97 */
+    {   "tya",  1,  flNone,                   OH_Implicit                  }, /* $98 */
+    {   "sta",  3,  flUseLabel,               OH_AbsoluteY                 }, /* $99 */
+    {   "txs",  1,  flNone,                   OH_Implicit                  }, /* $9a */
+    {   "stx",  3,  flUseLabel|flAbsOverride, OH_AbsoluteY                 }, /* $9b */
+    {   "stz",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $9c */
+    {   "sta",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $9d */
+    {   "stz",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $9e */
+    {   "bbs1", 3,  flUseLabel,               OH_BitBranch                 }, /* $9f */
+    {   "ldy",  2,  flNone,                   OH_Immediate                 }, /* $a0 */
+    {   "lda",  2,  flUseLabel,               OH_DirectXIndirect           }, /* $a1 */
+    {   "ldx",  2,  flNone,                   OH_Immediate                 }, /* $a2 */
+    {   "ldz",  2,  flNone,                   OH_Immediate                 }, /* $a3 */
+    {   "ldy",  2,  flUseLabel,               OH_Direct                    }, /* $a4 */
+    {   "lda",  2,  flUseLabel,               OH_Direct                    }, /* $a5 */
+    {   "ldx",  2,  flUseLabel,               OH_Direct                    }, /* $a6 */
+    {   "smb2", 2,  flUseLabel,               OH_Direct                    }, /* $a7 */
+    {   "tay",  1,  flNone,                   OH_Implicit                  }, /* $a8 */
+    {   "lda",  2,  flNone,                   OH_Immediate                 }, /* $a9 */
+    {   "tax",  1,  flNone,                   OH_Implicit                  }, /* $aa */
+    {   "ldz",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $ab */
+    {   "ldy",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $ac */
+    {   "lda",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $ad */
+    {   "ldx",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $ae */
+    {   "bbs2", 3,  flUseLabel,               OH_BitBranch                 }, /* $af */
+    {   "bcs",  2,  flLabel,                  OH_Relative                  }, /* $b0 */
+    {   "lda",  2,  flUseLabel,               OH_DirectIndirectY           }, /* $b1 */
+    {   "lda",  2,  flUseLabel,               OH_DirectIndirectZ           }, /* $b2 */
+    {   "lbcs", 3,  flLabel,                  OH_RelativeLong4510          }, /* $b3 */
+    {   "ldy",  2,  flUseLabel,               OH_DirectX                   }, /* $b4 */
+    {   "lda",  2,  flUseLabel,               OH_DirectX                   }, /* $b5 */
+    {   "ldx",  2,  flUseLabel,               OH_DirectY                   }, /* $b6 */
+    {   "smb3", 2,  flUseLabel,               OH_Direct                    }, /* $b7 */
+    {   "clv",  1,  flNone,                   OH_Implicit                  }, /* $b8 */
+    {   "lda",  3,  flUseLabel,               OH_AbsoluteY                 }, /* $b9 */
+    {   "tsx",  1,  flNone,                   OH_Implicit                  }, /* $ba */
+    {   "ldz",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $bb */
+    {   "ldy",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $bc */
+    {   "lda",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $bd */
+    {   "ldx",  3,  flUseLabel|flAbsOverride, OH_AbsoluteY                 }, /* $be */
+    {   "bbs3", 3,  flUseLabel,               OH_BitBranch                 }, /* $bf */
+    {   "cpy",  2,  flNone,                   OH_Immediate                 }, /* $c0 */
+    {   "cmp",  2,  flUseLabel,               OH_DirectXIndirect           }, /* $c1 */
+    {   "cpz",  2,  flNone,                   OH_Immediate                 }, /* $c2 */
+    {   "dew",  2,  flUseLabel,               OH_Direct                    }, /* $c3 */
+    {   "cpy",  2,  flUseLabel,               OH_Direct                    }, /* $c4 */
+    {   "cmp",  2,  flUseLabel,               OH_Direct                    }, /* $c5 */
+    {   "dec",  2,  flUseLabel,               OH_Direct                    }, /* $c6 */
+    {   "smb4", 2,  flUseLabel,               OH_Direct                    }, /* $c7 */
+    {   "iny",  1,  flNone,                   OH_Implicit                  }, /* $c8 */
+    {   "cmp",  2,  flNone,                   OH_Immediate                 }, /* $c9 */
+    {   "dex",  1,  flNone,                   OH_Implicit                  }, /* $ca */
+    {   "asw",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $cb */
+    {   "cpy",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $cc */
+    {   "cmp",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $cd */
+    {   "dec",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $ce */
+    {   "bbs4", 3,  flUseLabel,               OH_BitBranch                 }, /* $cf */
+    {   "bne",  2,  flLabel,                  OH_Relative                  }, /* $d0 */
+    {   "cmp",  2,  flUseLabel,               OH_DirectIndirectY           }, /* $d1 */
+    {   "cmp",  2,  flUseLabel,               OH_DirectIndirectZ           }, /* $d2 */
+    {   "lbne", 3,  flLabel,                  OH_RelativeLong4510          }, /* $d3 */
+    {   "cpz",  2,  flUseLabel,               OH_Direct                    }, /* $d4 */
+    {   "cmp",  2,  flUseLabel,               OH_DirectX                   }, /* $d5 */
+    {   "dec",  2,  flUseLabel,               OH_DirectX                   }, /* $d6 */
+    {   "smb5", 2,  flUseLabel,               OH_Direct                    }, /* $d7 */
+    {   "cld",  1,  flNone,                   OH_Implicit                  }, /* $d8 */
+    {   "cmp",  3,  flUseLabel,               OH_AbsoluteY                 }, /* $d9 */
+    {   "phx",  1,  flNone,                   OH_Implicit                  }, /* $da */
+    {   "phz",  1,  flNone,                   OH_Implicit                  }, /* $db */
+    {   "cpz",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $dc */
+    {   "cmp",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $dd */
+    {   "dec",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $de */
+    {   "bbs5", 3,  flUseLabel,               OH_BitBranch                 }, /* $df */
+    {   "cpx",  2,  flNone,                   OH_Immediate                 }, /* $e0 */
+    {   "sbc",  2,  flUseLabel,               OH_DirectXIndirect           }, /* $e1 */
+    {   "lda",  2,  flNone,                   OH_StackRelativeIndirectY4510}, /* $e2 */
+    {   "inw",  2,  flUseLabel,               OH_Direct                    }, /* $e3 */
+    {   "cpx",  2,  flUseLabel,               OH_Direct                    }, /* $e4 */
+    {   "sbc",  2,  flUseLabel,               OH_Direct                    }, /* $e5 */
+    {   "inc",  2,  flUseLabel,               OH_Direct                    }, /* $e6 */
+    {   "smb6", 2,  flUseLabel,               OH_Direct                    }, /* $e7 */
+    {   "inx",  1,  flNone,                   OH_Implicit                  }, /* $e8 */
+    {   "sbc",  2,  flNone,                   OH_Immediate                 }, /* $e9 */
+    {   "eom",  1,  flNone,                   OH_Implicit                  }, /* $ea */
+    {   "row",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $eb */
+    {   "cpx",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $ec */
+    {   "sbc",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $ed */
+    {   "inc",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $ee */
+    {   "bbs6", 3,  flUseLabel,               OH_BitBranch                 }, /* $ef */
+    {   "beq",  2,  flLabel,                  OH_Relative                  }, /* $f0 */
+    {   "sbc",  2,  flUseLabel,               OH_DirectIndirectY           }, /* $f1 */
+    {   "sbc",  2,  flUseLabel,               OH_DirectIndirectZ           }, /* $f2 */
+    {   "lbeq", 3,  flLabel,                  OH_RelativeLong4510          }, /* $f3 */
+    {   "phw",  3,  flNone,                   OH_ImmediateWord             }, /* $f4 */
+    {   "sbc",  2,  flUseLabel,               OH_DirectX                   }, /* $f5 */
+    {   "inc",  2,  flUseLabel,               OH_DirectX                   }, /* $f6 */
+    {   "smb7", 2,  flUseLabel,               OH_Direct                    }, /* $f7 */
+    {   "sed",  1,  flNone,                   OH_Implicit                  }, /* $f8 */
+    {   "sbc",  3,  flUseLabel,               OH_AbsoluteY                 }, /* $f9 */
+    {   "plx",  1,  flNone,                   OH_Implicit                  }, /* $fa */
+    {   "plz",  1,  flNone,                   OH_Implicit                  }, /* $fb */
+    {   "phw",  3,  flUseLabel|flAbsOverride, OH_Absolute                  }, /* $fc */
+    {   "sbc",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $fd */
+    {   "inc",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX                 }, /* $fe */
+    {   "bbs7", 3,  flUseLabel,               OH_BitBranch                 }, /* $ff */
+};
diff --git a/src/da65/opc65ce02.h b/src/da65/opc65ce02.h
new file mode 100644
index 000000000..e3987dbcd
--- /dev/null
+++ b/src/da65/opc65ce02.h
@@ -0,0 +1,58 @@
+/*****************************************************************************/
+/*                                                                           */
+/*                               opc65CE02.h                                 */
+/*                                                                           */
+/*                      65CE02 opcode description table                      */
+/*                                                                           */
+/*                                                                           */
+/*                                                                           */
+/* (C) 2003      Ullrich von Bassewitz                                       */
+/*               Roemerstrasse 52                                            */
+/*               D-70794 Filderstadt                                         */
+/* EMail:        uz@cc65.org                                                 */
+/*                                                                           */
+/*                                                                           */
+/* This software is provided 'as-is', without any expressed or implied       */
+/* warranty.  In no event will the authors be held liable for any damages    */
+/* arising from the use of this software.                                    */
+/*                                                                           */
+/* Permission is granted to anyone to use this software for any purpose,     */
+/* including commercial applications, and to alter it and redistribute it    */
+/* freely, subject to the following restrictions:                            */
+/*                                                                           */
+/* 1. The origin of this software must not be misrepresented; you must not   */
+/*    claim that you wrote the original software. If you use this software   */
+/*    in a product, an acknowledgment in the product documentation would be  */
+/*    appreciated but is not required.                                       */
+/* 2. Altered source versions must be plainly marked as such, and must not   */
+/*    be misrepresented as being the original software.                      */
+/* 3. This notice may not be removed or altered from any source              */
+/*    distribution.                                                          */
+/*                                                                           */
+/*****************************************************************************/
+
+
+
+#ifndef OPC65CE02_H
+#define OPC65CE02_H
+
+
+
+#include "opcdesc.h"
+
+
+
+/*****************************************************************************/
+/*                                   Data                                    */
+/*****************************************************************************/
+
+
+
+/* Descriptions for all opcodes */
+extern const OpcDesc OpcTable_65CE02[256];
+
+
+
+/* End of opc65CE02.h */
+
+#endif
diff --git a/src/da65/opctable.c b/src/da65/opctable.c
index 445f8880c..de90dd83a 100644
--- a/src/da65/opctable.c
+++ b/src/da65/opctable.c
@@ -43,6 +43,8 @@
 #include "opc65816.h"
 #include "opc65c02.h"
 #include "opc65sc02.h"
+#include "opcw65c02.h"
+#include "opc65ce02.h"
 #include "opchuc6280.h"
 #include "opcm740.h"
 #include "opctable.h"
@@ -75,6 +77,8 @@ void SetOpcTable (cpu_t CPU)
         case CPU_6502DTV: OpcTable = OpcTable_6502DTV;  break;
         case CPU_65SC02:  OpcTable = OpcTable_65SC02;   break;
         case CPU_65C02:   OpcTable = OpcTable_65C02;    break;
+        case CPU_W65C02:  OpcTable = OpcTable_W65C02;   break;
+        case CPU_65CE02:  OpcTable = OpcTable_65CE02;   break;
         case CPU_65816:   OpcTable = OpcTable_65816;    break;
         case CPU_HUC6280: OpcTable = OpcTable_HuC6280;  break;
         case CPU_M740:    OpcTable = OpcTable_M740;     break;
diff --git a/src/da65/opcw65c02.c b/src/da65/opcw65c02.c
new file mode 100644
index 000000000..2c48e1019
--- /dev/null
+++ b/src/da65/opcw65c02.c
@@ -0,0 +1,306 @@
+/*****************************************************************************/
+/*                                                                           */
+/*                                opcw65c02.c                                */
+/*                                                                           */
+/*                      W65C02 opcode description table                      */
+/*                                                                           */
+/*                                                                           */
+/*                                                                           */
+/* (C) 2003-2011, Ullrich von Bassewitz                                      */
+/*                Roemerstrasse 52                                           */
+/*                D-70794 Filderstadt                                        */
+/* EMail:         uz@cc65.org                                                */
+/*                                                                           */
+/*                                                                           */
+/* This software is provided 'as-is', without any expressed or implied       */
+/* warranty.  In no event will the authors be held liable for any damages    */
+/* arising from the use of this software.                                    */
+/*                                                                           */
+/* Permission is granted to anyone to use this software for any purpose,     */
+/* including commercial applications, and to alter it and redistribute it    */
+/* freely, subject to the following restrictions:                            */
+/*                                                                           */
+/* 1. The origin of this software must not be misrepresented; you must not   */
+/*    claim that you wrote the original software. If you use this software   */
+/*    in a product, an acknowledgment in the product documentation would be  */
+/*    appreciated but is not required.                                       */
+/* 2. Altered source versions must be plainly marked as such, and must not   */
+/*    be misrepresented as being the original software.                      */
+/* 3. This notice may not be removed or altered from any source              */
+/*    distribution.                                                          */
+/*                                                                           */
+/*****************************************************************************/
+
+
+
+/* da65 */
+#include "handler.h"
+#include "opcw65c02.h"
+
+
+
+/*****************************************************************************/
+/*                                   Data                                    */
+/*****************************************************************************/
+
+
+
+/* Descriptions for all opcodes */
+const OpcDesc OpcTable_W65C02[256] = {
+    {   "brk",  1,  flNone,                   OH_Implicit              }, /* $00 */
+    {   "ora",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $01 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $02 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $03 */
+    {   "tsb",  2,  flUseLabel,               OH_Direct                }, /* $04 */
+    {   "ora",  2,  flUseLabel,               OH_Direct                }, /* $05 */
+    {   "asl",  2,  flUseLabel,               OH_Direct                }, /* $06 */
+    {   "rmb0", 2,  flUseLabel,               OH_Direct,               }, /* $07 */
+    {   "php",  1,  flNone,                   OH_Implicit              }, /* $08 */
+    {   "ora",  2,  flNone,                   OH_Immediate             }, /* $09 */
+    {   "asl",  1,  flNone,                   OH_Accumulator           }, /* $0a */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $0b */
+    {   "tsb",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $0c */
+    {   "ora",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $0d */
+    {   "asl",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $0e */
+    {   "bbr0", 3,  flUseLabel,               OH_BitBranch             }, /* $0f */
+    {   "bpl",  2,  flLabel,                  OH_Relative              }, /* $10 */
+    {   "ora",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $11 */
+    {   "ora",  2,  flUseLabel,               OH_DirectIndirect        }, /* $12 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $13 */
+    {   "trb",  2,  flUseLabel,               OH_Direct                }, /* $14 */
+    {   "ora",  2,  flUseLabel,               OH_DirectX               }, /* $15 */
+    {   "asl",  2,  flUseLabel,               OH_DirectX               }, /* $16 */
+    {   "rmb1", 2,  flUseLabel,               OH_Direct,               }, /* $17 */
+    {   "clc",  1,  flNone,                   OH_Implicit              }, /* $18 */
+    {   "ora",  3,  flUseLabel,               OH_AbsoluteY             }, /* $19 */
+    {   "inc",  1,  flNone,                   OH_Accumulator           }, /* $1a */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $1b */
+    {   "trb",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $1c */
+    {   "ora",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $1d */
+    {   "asl",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $1e */
+    {   "bbr1", 3,  flUseLabel,               OH_BitBranch             }, /* $1f */
+    {   "jsr",  3,  flLabel,                  OH_JsrAbsolute           }, /* $20 */
+    {   "and",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $21 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $22 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $23 */
+    {   "bit",  2,  flUseLabel,               OH_Direct                }, /* $24 */
+    {   "and",  2,  flUseLabel,               OH_Direct                }, /* $25 */
+    {   "rol",  2,  flUseLabel,               OH_Direct                }, /* $26 */
+    {   "rmb2", 2,  flUseLabel,               OH_Direct,               }, /* $27 */
+    {   "plp",  1,  flNone,                   OH_Implicit              }, /* $28 */
+    {   "and",  2,  flNone,                   OH_Immediate             }, /* $29 */
+    {   "rol",  1,  flNone,                   OH_Accumulator           }, /* $2a */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $2b */
+    {   "bit",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $2c */
+    {   "and",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $2d */
+    {   "rol",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $2e */
+    {   "bbr2", 3,  flUseLabel,               OH_BitBranch             }, /* $2f */
+    {   "bmi",  2,  flLabel,                  OH_Relative              }, /* $30 */
+    {   "and",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $31 */
+    {   "and",  2,  flUseLabel,               OH_DirectIndirect,       }, /* $32 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $33 */
+    {   "bit",  2,  flUseLabel,               OH_DirectX               }, /* $34 */
+    {   "and",  2,  flUseLabel,               OH_DirectX               }, /* $35 */
+    {   "rol",  2,  flUseLabel,               OH_DirectX               }, /* $36 */
+    {   "rmb3", 2,  flUseLabel,               OH_Direct,               }, /* $37 */
+    {   "sec",  1,  flNone,                   OH_Implicit              }, /* $38 */
+    {   "and",  3,  flUseLabel,               OH_AbsoluteY             }, /* $39 */
+    {   "dec",  1,  flNone,                   OH_Accumulator           }, /* $3a */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $3b */
+    {   "bit",  3,  flUseLabel,               OH_AbsoluteX             }, /* $3c */
+    {   "and",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $3d */
+    {   "rol",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $3e */
+    {   "bbr3", 3,  flUseLabel,               OH_BitBranch             }, /* $3f */
+    {   "rti",  1,  flNone,                   OH_Rts                   }, /* $40 */
+    {   "eor",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $41 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $42 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $43 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $44 */
+    {   "eor",  2,  flUseLabel,               OH_Direct                }, /* $45 */
+    {   "lsr",  2,  flUseLabel,               OH_Direct                }, /* $46 */
+    {   "rmb4", 2,  flUseLabel,               OH_Direct,               }, /* $47 */
+    {   "pha",  1,  flNone,                   OH_Implicit              }, /* $48 */
+    {   "eor",  2,  flNone,                   OH_Immediate             }, /* $49 */
+    {   "lsr",  1,  flNone,                   OH_Accumulator           }, /* $4a */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $4b */
+    {   "jmp",  3,  flLabel,                  OH_JmpAbsolute           }, /* $4c */
+    {   "eor",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $4d */
+    {   "lsr",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $4e */
+    {   "bbr4", 3,  flUseLabel,               OH_BitBranch             }, /* $4f */
+    {   "bvc",  2,  flLabel,                  OH_Relative              }, /* $50 */
+    {   "eor",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $51 */
+    {   "eor",  2,  flUseLabel,               OH_DirectIndirect        }, /* $52 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $53 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $54 */
+    {   "eor",  2,  flUseLabel,               OH_DirectX               }, /* $55 */
+    {   "lsr",  2,  flUseLabel,               OH_DirectX               }, /* $56 */
+    {   "rmb5", 2,  flUseLabel,               OH_Direct,               }, /* $57 */
+    {   "cli",  1,  flNone,                   OH_Implicit              }, /* $58 */
+    {   "eor",  3,  flUseLabel,               OH_AbsoluteY             }, /* $59 */
+    {   "phy",  1,  flNone,                   OH_Implicit              }, /* $5a */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $5b */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $5c */
+    {   "eor",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $5d */
+    {   "lsr",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $5e */
+    {   "bbr5", 3,  flUseLabel,               OH_BitBranch             }, /* $5f */
+    {   "rts",  1,  flNone,                   OH_Rts                   }, /* $60 */
+    {   "adc",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $61 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $62 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $63 */
+    {   "stz",  2,  flUseLabel,               OH_Direct                }, /* $64 */
+    {   "adc",  2,  flUseLabel,               OH_Direct                }, /* $65 */
+    {   "ror",  2,  flUseLabel,               OH_Direct                }, /* $66 */
+    {   "rmb6", 2,  flUseLabel,               OH_Direct,               }, /* $67 */
+    {   "pla",  1,  flNone,                   OH_Implicit              }, /* $68 */
+    {   "adc",  2,  flNone,                   OH_Immediate             }, /* $69 */
+    {   "ror",  1,  flNone,                   OH_Accumulator           }, /* $6a */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $6b */
+    {   "jmp",  3,  flLabel,                  OH_JmpAbsoluteIndirect   }, /* $6c */
+    {   "adc",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $6d */
+    {   "ror",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $6e */
+    {   "bbr6", 3,  flUseLabel,               OH_BitBranch             }, /* $6f */
+    {   "bvs",  2,  flLabel,                  OH_Relative              }, /* $70 */
+    {   "adc",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $71 */
+    {   "adc",  2,  flUseLabel,               OH_DirectIndirect,       }, /* $72 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $73 */
+    {   "stz",  2,  flUseLabel,               OH_DirectX               }, /* $74 */
+    {   "adc",  2,  flUseLabel,               OH_DirectX               }, /* $75 */
+    {   "ror",  2,  flUseLabel,               OH_DirectX               }, /* $76 */
+    {   "rmb7", 2,  flUseLabel,               OH_Direct,               }, /* $77 */
+    {   "sei",  1,  flNone,                   OH_Implicit              }, /* $78 */
+    {   "adc",  3,  flUseLabel,               OH_AbsoluteY             }, /* $79 */
+    {   "ply",  1,  flNone,                   OH_Implicit              }, /* $7a */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $7b */
+    {   "jmp",  3,  flLabel,                  OH_AbsoluteXIndirect     }, /* $7c */
+    {   "adc",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $7d */
+    {   "ror",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $7e */
+    {   "bbr7", 3,  flUseLabel,               OH_BitBranch             }, /* $7f */
+    {   "bra",  2,  flLabel,                  OH_Relative              }, /* $80 */
+    {   "sta",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $81 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $82 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $83 */
+    {   "sty",  2,  flUseLabel,               OH_Direct                }, /* $84 */
+    {   "sta",  2,  flUseLabel,               OH_Direct                }, /* $85 */
+    {   "stx",  2,  flUseLabel,               OH_Direct                }, /* $86 */
+    {   "smb0", 2,  flUseLabel,               OH_Direct,               }, /* $87 */
+    {   "dey",  1,  flNone,                   OH_Implicit              }, /* $88 */
+    {   "bit",  2,  flNone,                   OH_Immediate             }, /* $89 */
+    {   "txa",  1,  flNone,                   OH_Implicit              }, /* $8a */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $8b */
+    {   "sty",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $8c */
+    {   "sta",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $8d */
+    {   "stx",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $8e */
+    {   "bbs0", 3,  flUseLabel,               OH_BitBranch             }, /* $8f */
+    {   "bcc",  2,  flLabel,                  OH_Relative              }, /* $90 */
+    {   "sta",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $91 */
+    {   "sta",  2,  flUseLabel,               OH_DirectIndirect        }, /* $92 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $93 */
+    {   "sty",  2,  flUseLabel,               OH_DirectX               }, /* $94 */
+    {   "sta",  2,  flUseLabel,               OH_DirectX               }, /* $95 */
+    {   "stx",  2,  flUseLabel,               OH_DirectY               }, /* $96 */
+    {   "smb1", 2,  flUseLabel,               OH_Direct,               }, /* $97 */
+    {   "tya",  1,  flNone,                   OH_Implicit              }, /* $98 */
+    {   "sta",  3,  flUseLabel,               OH_AbsoluteY             }, /* $99 */
+    {   "txs",  1,  flNone,                   OH_Implicit              }, /* $9a */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $9b */
+    {   "stz",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $9c */
+    {   "sta",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $9d */
+    {   "stz",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $9e */
+    {   "bbs1", 3,  flUseLabel,               OH_BitBranch             }, /* $9f */
+    {   "ldy",  2,  flNone,                   OH_Immediate             }, /* $a0 */
+    {   "lda",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $a1 */
+    {   "ldx",  2,  flNone,                   OH_Immediate             }, /* $a2 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $a3 */
+    {   "ldy",  2,  flUseLabel,               OH_Direct                }, /* $a4 */
+    {   "lda",  2,  flUseLabel,               OH_Direct                }, /* $a5 */
+    {   "ldx",  2,  flUseLabel,               OH_Direct                }, /* $a6 */
+    {   "smb2", 2,  flUseLabel,               OH_Direct,               }, /* $a7 */
+    {   "tay",  1,  flNone,                   OH_Implicit              }, /* $a8 */
+    {   "lda",  2,  flNone,                   OH_Immediate             }, /* $a9 */
+    {   "tax",  1,  flNone,                   OH_Implicit              }, /* $aa */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $ab */
+    {   "ldy",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ac */
+    {   "lda",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ad */
+    {   "ldx",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ae */
+    {   "bbs2", 3,  flUseLabel,               OH_BitBranch             }, /* $af */
+    {   "bcs",  2,  flLabel,                  OH_Relative              }, /* $b0 */
+    {   "lda",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $b1 */
+    {   "lda",  2,  flUseLabel,               OH_DirectIndirect        }, /* $b2 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $b3 */
+    {   "ldy",  2,  flUseLabel,               OH_DirectX               }, /* $b4 */
+    {   "lda",  2,  flUseLabel,               OH_DirectX               }, /* $b5 */
+    {   "ldx",  2,  flUseLabel,               OH_DirectY               }, /* $b6 */
+    {   "smb3", 2,  flUseLabel,               OH_Direct,               }, /* $b7 */
+    {   "clv",  1,  flNone,                   OH_Implicit              }, /* $b8 */
+    {   "lda",  3,  flUseLabel,               OH_AbsoluteY             }, /* $b9 */
+    {   "tsx",  1,  flNone,                   OH_Implicit              }, /* $ba */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $bb */
+    {   "ldy",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $bc */
+    {   "lda",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $bd */
+    {   "ldx",  3,  flUseLabel|flAbsOverride, OH_AbsoluteY             }, /* $be */
+    {   "bbs3", 3,  flUseLabel,               OH_BitBranch             }, /* $bf */
+    {   "cpy",  2,  flNone,                   OH_Immediate             }, /* $c0 */
+    {   "cmp",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $c1 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $c2 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $c3 */
+    {   "cpy",  2,  flUseLabel,               OH_Direct                }, /* $c4 */
+    {   "cmp",  2,  flUseLabel,               OH_Direct                }, /* $c5 */
+    {   "dec",  2,  flUseLabel,               OH_Direct                }, /* $c6 */
+    {   "smb4", 2,  flUseLabel,               OH_Direct,               }, /* $c7 */
+    {   "iny",  1,  flNone,                   OH_Implicit              }, /* $c8 */
+    {   "cmp",  2,  flNone,                   OH_Immediate             }, /* $c9 */
+    {   "dex",  1,  flNone,                   OH_Implicit              }, /* $ca */
+    {   "wai",  1,  flNone,                   OH_Implicit              }, /* $cb */
+    {   "cpy",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $cc */
+    {   "cmp",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $cd */
+    {   "dec",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ce */
+    {   "bbs4", 3,  flUseLabel,               OH_BitBranch             }, /* $cf */
+    {   "bne",  2,  flLabel,                  OH_Relative              }, /* $d0 */
+    {   "cmp",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $d1 */
+    {   "cmp",  2,  flUseLabel,               OH_DirectIndirect        }, /* $d2 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $d3 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $d4 */
+    {   "cmp",  2,  flUseLabel,               OH_DirectX               }, /* $d5 */
+    {   "dec",  2,  flUseLabel,               OH_DirectX               }, /* $d6 */
+    {   "smb5", 2,  flUseLabel,               OH_Direct,               }, /* $d7 */
+    {   "cld",  1,  flNone,                   OH_Implicit              }, /* $d8 */
+    {   "cmp",  3,  flUseLabel,               OH_AbsoluteY             }, /* $d9 */
+    {   "phx",  1,  flNone,                   OH_Implicit              }, /* $da */
+    {   "stp",  1,  flNone,                   OH_Implicit              }, /* $db */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $dc */
+    {   "cmp",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $dd */
+    {   "dec",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $de */
+    {   "bbs5", 3,  flUseLabel,               OH_BitBranch             }, /* $df */
+    {   "cpx",  2,  flNone,                   OH_Immediate             }, /* $e0 */
+    {   "sbc",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $e1 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $e2 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $e3 */
+    {   "cpx",  2,  flUseLabel,               OH_Direct                }, /* $e4 */
+    {   "sbc",  2,  flUseLabel,               OH_Direct                }, /* $e5 */
+    {   "inc",  2,  flUseLabel,               OH_Direct                }, /* $e6 */
+    {   "smb6", 2,  flUseLabel,               OH_Direct,               }, /* $e7 */
+    {   "inx",  1,  flNone,                   OH_Implicit              }, /* $e8 */
+    {   "sbc",  2,  flNone,                   OH_Immediate             }, /* $e9 */
+    {   "nop",  1,  flNone,                   OH_Implicit              }, /* $ea */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $eb */
+    {   "cpx",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ec */
+    {   "sbc",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ed */
+    {   "inc",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ee */
+    {   "bbs6", 3,  flUseLabel,               OH_BitBranch             }, /* $ef */
+    {   "beq",  2,  flLabel,                  OH_Relative              }, /* $f0 */
+    {   "sbc",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $f1 */
+    {   "sbc",  2,  flUseLabel,               OH_DirectIndirect        }, /* $f2 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $f3 */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $f4 */
+    {   "sbc",  2,  flUseLabel,               OH_DirectX               }, /* $f5 */
+    {   "inc",  2,  flUseLabel,               OH_DirectX               }, /* $f6 */
+    {   "smb7", 2,  flUseLabel,               OH_Direct,               }, /* $f7 */
+    {   "sed",  1,  flNone,                   OH_Implicit              }, /* $f8 */
+    {   "sbc",  3,  flUseLabel,               OH_AbsoluteY             }, /* $f9 */
+    {   "plx",  1,  flNone,                   OH_Implicit              }, /* $fa */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $fb */
+    {   "",     1,  flIllegal,                OH_Illegal,              }, /* $fc */
+    {   "sbc",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $fd */
+    {   "inc",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $fe */
+    {   "bbs7", 3,  flUseLabel,               OH_BitBranch             }, /* $ff */
+};
diff --git a/src/da65/opcw65c02.h b/src/da65/opcw65c02.h
new file mode 100644
index 000000000..0805ce5dd
--- /dev/null
+++ b/src/da65/opcw65c02.h
@@ -0,0 +1,58 @@
+/*****************************************************************************/
+/*                                                                           */
+/*                                opcw65c02.h                                */
+/*                                                                           */
+/*                      W65C02 opcode description table                      */
+/*                                                                           */
+/*                                                                           */
+/*                                                                           */
+/* (C) 2003      Ullrich von Bassewitz                                       */
+/*               Roemerstrasse 52                                            */
+/*               D-70794 Filderstadt                                         */
+/* EMail:        uz@cc65.org                                                 */
+/*                                                                           */
+/*                                                                           */
+/* This software is provided 'as-is', without any expressed or implied       */
+/* warranty.  In no event will the authors be held liable for any damages    */
+/* arising from the use of this software.                                    */
+/*                                                                           */
+/* Permission is granted to anyone to use this software for any purpose,     */
+/* including commercial applications, and to alter it and redistribute it    */
+/* freely, subject to the following restrictions:                            */
+/*                                                                           */
+/* 1. The origin of this software must not be misrepresented; you must not   */
+/*    claim that you wrote the original software. If you use this software   */
+/*    in a product, an acknowledgment in the product documentation would be  */
+/*    appreciated but is not required.                                       */
+/* 2. Altered source versions must be plainly marked as such, and must not   */
+/*    be misrepresented as being the original software.                      */
+/* 3. This notice may not be removed or altered from any source              */
+/*    distribution.                                                          */
+/*                                                                           */
+/*****************************************************************************/
+
+
+
+#ifndef OPCW65C02_H
+#define OPCW65C02_H
+
+
+
+#include "opcdesc.h"
+
+
+
+/*****************************************************************************/
+/*                                   Data                                    */
+/*****************************************************************************/
+
+
+
+/* Descriptions for all opcodes */
+extern const OpcDesc OpcTable_W65C02[256];
+
+
+
+/* End of opcw65c02.h */
+
+#endif
diff --git a/test/asm/cpudetect/4510-cpudetect.ref b/test/asm/cpudetect/4510-cpudetect.ref
index 484469a79..5eba7ec5a 100644
Binary files a/test/asm/cpudetect/4510-cpudetect.ref and b/test/asm/cpudetect/4510-cpudetect.ref differ
diff --git a/test/asm/cpudetect/45GS02-cpudetect.ref b/test/asm/cpudetect/45GS02-cpudetect.ref
index b6e8e797f..3936f2902 100644
Binary files a/test/asm/cpudetect/45GS02-cpudetect.ref and b/test/asm/cpudetect/45GS02-cpudetect.ref differ
diff --git a/test/asm/cpudetect/65816-cpudetect.ref b/test/asm/cpudetect/65816-cpudetect.ref
index 4f6e767b0..e614b34c9 100644
Binary files a/test/asm/cpudetect/65816-cpudetect.ref and b/test/asm/cpudetect/65816-cpudetect.ref differ
diff --git a/test/asm/cpudetect/65ce02-cpudetect.ref b/test/asm/cpudetect/65ce02-cpudetect.ref
new file mode 100644
index 000000000..eca5a2b2a
Binary files /dev/null and b/test/asm/cpudetect/65ce02-cpudetect.ref differ
diff --git a/test/asm/cpudetect/allinst.inc b/test/asm/cpudetect/allinst.inc
index 8e27a5429..2ba44ff83 100644
--- a/test/asm/cpudetect/allinst.inc
+++ b/test/asm/cpudetect/allinst.inc
@@ -357,11 +357,10 @@ LABEL:
     .endscope
 .endif
 
-
 ;------------------------------------------------------------------------------
-; The 65c02 is the CMOS re-design of the 6502. It has a few improvements:
+; The 65sc02 is the original CMOS re-design of the 6502.
 ;
-;      65C02            65ce02
+;      65SC02           65ce02
 ;
 ; $04  tsb zp
 ; $0c  tsb abs16
@@ -391,69 +390,42 @@ LABEL:
 ; $f2  sbc (zp)         (-> sbc (zp), z)
 ; $fa  plx
 
-; FIXME: currently CPU_ISET_65SC02 and CPU_65SC02 really means "65C02"
-
-; FIXME: should really check for 65C02
-
 .if (.cpu .bitand CPU_ISET_65SC02)
     .scope
     ; 65c02 instruction set adds some extra legal instructions to 6502
     tsb $12         ; $04
     tsb $1234       ; $0c
-    ;ora ($12)       ; $12  FIXME: not working with 4510:ora (zp), z
+    ora ($12)       ; $12  FIXME: not working with 4510:ora (zp), z
     trb $12         ; $14
     inc a           ; $1a
     trb $1234       ; $1c
-    ;and ($12)       ; $32  FIXME: not working with 4510:and (zp), z
+    and ($12)       ; $32  FIXME: not working with 4510:and (zp), z
     bit $12,x       ; $34
     dec a           ; $3a
     bit $1234,x     ; $3c
-    ;eor ($12)       ; $52  FIXME: not working with 4510:eor (zp), z
+    eor ($12)       ; $52  FIXME: not working with 4510:eor (zp), z
     phy             ; $5a
     stz $12         ; $64
-    ;adc ($12)       ; $72  FIXME: not working with 4510:adc (zp), z
+    adc ($12)       ; $72  FIXME: not working with 4510:adc (zp), z
     stz $12,x       ; $74
     ply             ; $7a
     jmp ($1234)     ; $7c
 LABEL:
     bra LABEL       ; $80
     bit #$12        ; $89
-    ;sta ($12)       ; $92  FIXME: not working with 4510:sta (zp), z
+    sta ($12)       ; $92  FIXME: not working with 4510:sta (zp), z
     stz $1234       ; $9c
     stz $1234,x     ; $9e
-    ;lda ($12)       ; $b2  FIXME: not working with 4510:lda (zp), z
-    ;cmp ($12)       ; $d2  FIXME: not working with 4510:cmp (zp), z
+    lda ($12)       ; $b2  FIXME: not working with 4510:lda (zp), z
+    cmp ($12)       ; $d2  FIXME: not working with 4510:cmp (zp), z
     phx             ; $da
-    ;sbc ($12)       ; $f2  FIXME: not working with 4510:sbc (zp), z
+    sbc ($12)       ; $f2  FIXME: not working with 4510:sbc (zp), z
     plx             ; $fa
     .endscope
 .endif
 
-; FIXME: hack so these opcodes get tested anyway, while 4510 is still quirky
-.if (.cpu .bitand CPU_ISET_65SC02)
-.if (.not .cpu = CPU_4510)
-    ora ($12)       ; $12
-    and ($12)       ; $32
-    eor ($12)       ; $52
-    adc ($12)       ; $72
-    sta ($12)       ; $92
-    lda ($12)       ; $b2
-    cmp ($12)       ; $d2
-    sbc ($12)       ; $f2
-.endif
-.endif
 
-; TODO: R65C02
 ; The R65C02 is a superset of the 65C02. It adds bit manipulation instructions:
-;   smbB zp         set bit in zp location
-;   rmbB zp         reset bit in zp location
-;   bbsB zp, rel8   branch if bit is set in zp location
-;   bbrB zp, rel8   branch if bit is reset in zp location
-
-; FIXME: currently CPU_ISET_65C02 and CPU_65C02 really means "W65C02"
-
-; FIXME: should really check for R65C02
-
 .if (.cpu .bitand CPU_ISET_65C02)
 
     ; R65C02 instruction set adds some extra legal instructions to 65C02
@@ -494,88 +466,17 @@ LABEL3:
 .endif
 
 
-; TODO: W65C02
 ; The W65C02 is a superset of the R65C02. It only adds two instructions:
-;
-; $cb  wai             wait for interrupt
-; $db  stp             wait for reset
-
-; FIXME: currently CPU_ISET_65C02 and CPU_65C02 really means "W65C02"
-
-; FIXME: should really check for W65C02
-
-.if (.cpu = CPU_65C02)
+.if (.cpu .bitand CPU_ISET_W65C02)
     wai             ; $cb
     stp             ; $db
 .endif
 
 
-; TODO: 65CE02
 ; The 65CE02 is another superset of the R65C02. It has several improvements:
-;
-; $02  cle              clear stack extend disable
-; $03  see              set stack extend disable
-; $0b  tsy              transfer stack_ptr_high to Y
-; $12  ora (zp), z
-; $13  lbpl rel16
-; $1b  inz              increment Z
-; $22  jsr (abs16)
-; $23  jsr (abs16, x)
-; $2b  tys              transfer Y to stack_ptr_high
-; $32  and (zp), z
-; $33  lbmi rel16
-; $3b  dez              decrement Z
-; $42  neg              negate A
-; $43  asr
-; $44  asr zp
-; $4b  taz              transfer A to Z
-; $52  eor (zp), z
-; $53  lbvc rel16
-; $54  asr zp, x
-; $5b  tab
-; $5c  aug              "4-byte NOP reserved for future expansion"
-; $62  rtn #imm8
-; $63  lbsr rel16       relative jsr, "branch to subroutine"
-; $64  stz zp           store Z
-; $6b  tza              transfer Z to A
-; $72  adc (zp), z
-; $73  lbvs rel16
-; $74  stz zp, x        store Z
-; $7b  tba
-; $82  sta (off8, s), y
-; $83  lbra rel16       relative jmp
-; $8b  sty abs16, x
-; $92  sta (zp), z
-; $93  lbcc rel16
-; $9b  stx abs16, y
-; $9c  stz abs16        store Z
-; $9e  stz abs16, x     store Z
-; $a3  ldz #imm8
-; $ab  ldz abs16
-; $b2  lda (zp), z
-; $b3  lbcs rel16
-; $bb  ldz abs16, x
-; $c2  cpz #imm8
-; $c3  dew zp
-; $cb  asw abs16
-; $d2  cmp (zp), z
-; $d3  lbne rel16
-; $d4  cpz zp
-; $db  phz              push Z
-; $dc  cpz abs16
-; $e2  lda (off8, s), y
-; $e3  inw zp
-; $eb  row abs16
-; $f2  sbc (zp), z
-; $f3  lbeq rel16
-; $f4  phw #imm16
-; $fb  plz              pull Z
-; $fc  phw abs16
-
-; FIXME: should really check for 65CE02
-
-.if (.cpu .bitand CPU_ISET_4510)
+.if (.cpu .bitand CPU_ISET_65CE02)
     .scope
+
     ; 65CE02 adds the following:
     cle                         ; $02
     see                         ; $03
@@ -649,8 +550,6 @@ LABEL3:
 
     ; added to 65CE02
     map                         ; $5c   ("4-byte NOP reserved for future expansion" on 65CE02)
-    asw $1234                   ; $cb   (wai on W65C02)
-    phz                         ; $db   (stp on W65C02)
     eom                         ; $ea   "end of mapping" - but really just a NOP
 
     .endscope
@@ -896,3 +795,215 @@ LABEL:
     .endscope
 .endif
 
+.if (.cpu .bitand CPU_ISET_65816)
+
+    .smart  -                       ; Stop being smart
+
+    .A8 ; akku 8 bit
+    .I8 ; index registers 8 bit
+
+    .scope
+    cop $12             ; $02  coprocessor operation
+    ora $12, s          ; $03
+    ora [$12]           ; $07
+    phd                 ; $0b  push direct page register
+    ora $123456         ; $0f
+    ora ($12, s), y     ; $13
+    ora [$12], y        ; $17
+    tcs                 ; $1b  transfer C to stack pointer
+    ora $123456, x      ; $1f
+    jsl $123456         ; $22
+    and $12, s          ; $23
+    and [$12]           ; $27
+    pld                 ; $2b  pull direct page register
+    and $123456         ; $2f
+    and ($12, s), y     ; $33
+    and [$12], y        ; $37
+    tsc                 ; $3b  transfer stack pointer to C
+    and $123456, x      ; $3f
+    wdm $12             ; $42  (reserved for future expansion)
+    eor $12, s          ; $43
+    mvp $1234, $5678    ; $44
+    eor [$12]           ; $47
+    phk                 ; $4b  push program bank register
+    eor $123456         ; $4f
+    eor ($12, s), y     ; $53
+    mvn $1234, $5678    ; $54
+    eor [$12], y        ; $57
+    tcd                 ; $5b  transfer C to direct page register
+    jml $123456         ; $5c
+    eor $123456, x      ; $5f
+    per LABEL           ; $62  push effective relative address
+    adc $12, s          ; $63
+    adc [$12]           ; $67
+    rtl                 ; $6b  return long (fetches 24-bit address from stack)
+    adc $123456         ; $6f
+    adc ($12, s), y     ; $73
+    adc [$12], y        ; $77
+    tdc                 ; $7b  transfer direct page register to C
+    adc $123456, x      ; $7f
+LABEL:
+    brl LABEL           ; $82  branch long (16-bit offset)
+    sta $12, s          ; $83
+    sta [$12]           ; $87
+    phb                 ; $8b  push data bank register
+    sta $123456         ; $8f
+    sta ($12, s), y     ; $93
+    sta [$12], y        ; $97
+    txy                 ; $9b  transfer X to Y
+    sta $123456, x      ; $9f
+    lda $12, s          ; $a3
+    lda [$12]           ; $a7
+    plb                 ; $ab  pull data bank register
+    lda $123456         ; $af
+    lda ($12, s), y     ; $b3
+    lda [$12], y        ; $b7
+    tyx                 ; $bb  transfer Y to X
+    lda $123456, x      ; $bf
+    rep #$12            ; $c2  clear bits in status register
+    cmp $12, s          ; $c3
+    cmp [$12]           ; $c7
+    wai                 ; $cb  wait for interrupt
+    cmp $123456         ; $cf
+    cmp ($12, s), y     ; $d3
+    pei ($12)           ; $d4  push effective indirect address
+    cmp [$12], y        ; $d7
+    stp                 ; $db  wait for reset
+    jmp [$1234]         ; $dc
+    cmp $123456, x      ; $df
+    sep #$12            ; $e2  set bits in status register
+    sbc $12, s          ; $e3
+    sbc [$12]           ; $e7
+    xba                 ; $eb  exchange high and low bytes of accumulator
+    sbc $123456         ; $ef
+    sbc ($12, s), y     ; $f3
+    pea $1234           ; $f4  push effective absolute address
+    sbc [$12], y        ; $f7
+    xce                 ; $fb  exchange Carry and Emulation bits
+    jsr ($1234, x)      ; $fc
+    sbc $123456, x      ; $ff
+    .endscope
+
+    .A16 ; akku 16 bit
+    .I16 ; index registers 16 bit
+
+    .scope
+    cop $12             ; $02  coprocessor operation
+    ora $12, s          ; $03
+    ora [$12]           ; $07
+    phd                 ; $0b  push direct page register
+    ora $123456         ; $0f
+    ora ($12, s), y     ; $13
+    ora [$12], y        ; $17
+    tcs                 ; $1b  transfer C to stack pointer
+    ora $123456, x      ; $1f
+    jsl $123456         ; $22
+    and $12, s          ; $23
+    and [$12]           ; $27
+    pld                 ; $2b  pull direct page register
+    and $123456         ; $2f
+    and ($12, s), y     ; $33
+    and [$12], y        ; $37
+    tsc                 ; $3b  transfer stack pointer to C
+    and $123456, x      ; $3f
+    wdm $12             ; $42  (reserved for future expansion)
+    eor $12, s          ; $43
+    mvp $1234, $5678    ; $44
+    eor [$12]           ; $47
+    phk                 ; $4b  push program bank register
+    eor $123456         ; $4f
+    eor ($12, s), y     ; $53
+    mvn $1234, $5678    ; $54
+    eor [$12], y        ; $57
+    tcd                 ; $5b  transfer C to direct page register
+    jml $123456         ; $5c
+    eor $123456, x      ; $5f
+    per LABEL           ; $62  push effective relative address
+    adc $12, s          ; $63
+    adc [$12]           ; $67
+    rtl                 ; $6b  return long (fetches 24-bit address from stack)
+    adc $123456         ; $6f
+    adc ($12, s), y     ; $73
+    adc [$12], y        ; $77
+    tdc                 ; $7b  transfer direct page register to C
+    adc $123456, x      ; $7f
+LABEL:
+    brl LABEL           ; $82  branch long (16-bit offset)
+    sta $12, s          ; $83
+    sta [$12]           ; $87
+    phb                 ; $8b  push data bank register
+    sta $123456         ; $8f
+    sta ($12, s), y     ; $93
+    sta [$12], y        ; $97
+    txy                 ; $9b  transfer X to Y
+    sta $123456, x      ; $9f
+    lda $12, s          ; $a3
+    lda [$12]           ; $a7
+    plb                 ; $ab  pull data bank register
+    lda $123456         ; $af
+    lda ($12, s), y     ; $b3
+    lda [$12], y        ; $b7
+    tyx                 ; $bb  transfer Y to X
+    lda $123456, x      ; $bf
+    rep #$12            ; $c2  clear bits in status register
+    cmp $12, s          ; $c3
+    cmp [$12]           ; $c7
+    wai                 ; $cb  wait for interrupt
+    cmp $123456         ; $cf
+    cmp ($12, s), y     ; $d3
+    pei ($12)           ; $d4  push effective indirect address
+    cmp [$12], y        ; $d7
+    stp                 ; $db  wait for reset
+    jmp [$1234]         ; $dc
+    cmp $123456, x      ; $df
+    sep #$12            ; $e2  set bits in status register
+    sbc $12, s          ; $e3
+    sbc [$12]           ; $e7
+    xba                 ; $eb  exchange high and low bytes of accumulator
+    sbc $123456         ; $ef
+    sbc ($12, s), y     ; $f3
+    pea $1234           ; $f4  push effective absolute address
+    sbc [$12], y        ; $f7
+    xce                 ; $fb  exchange Carry and Emulation bits
+    jsr ($1234, x)      ; $fc
+    sbc $123456, x      ; $ff
+    .endscope
+
+.endif
+
+.if (.cpu .bitand CPU_ISET_SWEET16)
+
+    RTN                 ; $00      Return to 6502 code.
+    BR   LABEL          ; $01 ea   Unconditional Branch.
+    BNC  LABEL          ; $02 ea   Branch if Carry=0.
+    BC   LABEL          ; $03 ea   Branch if Carry=1.
+    BP   LABEL          ; $04 ea   Branch if last result positive.
+    BM   LABEL          ; $0S ea   Branch if last result negative.
+    BZ   LABEL          ; $06 ea   Branch if last result zero.
+    BNZ  LABEL          ; $07 ea   Branch if last result non-zero.
+    BM1  LABEL          ; $08 ea   Branch if last result = -1.
+    BNM1 LABEL          ; $09 ea   Branch if last result not -1.
+    BK                  ; $0A      Execute 6502 BRK instruction.
+    RS                  ; $0B      Return from SWEET-16 subroutine.
+    BS   LABEL          ; $0C ea   Call SWEET-16 subroutine.
+LABEL:
+
+.repeat 16, count
+    SET  count,$1234    ; $1n lo hi  Rn <-- value.
+    LD   count          ; $2n        R0 <-- (Rn).
+    ST   count          ; $3n        Rn <-- (R0).
+    LD   @count         ; $4n        MA = (Rn), ROL <-- (MA), Rn <-- MA+1, R0H <-- 0.
+    ST   @count         ; $5n        MA = (Rn), MA <-- (R0L), Rn <-- MA+1.
+    LDD  @count         ; $6n        MA = (Rn), R0 <-- (MA, MA+1), Rn <-- MA+2.
+    STD  @count         ; $7n        MA = (Rn), MA,MA+l <-- (R0), Rn <-- MA+2.
+    POP  @count         ; $8n        MA = (Rn)-1, R0L <-- (MA), R0H <-- 0, Rn <-- MA.
+    STP  @count         ; $9n        MA <-- (Rn)-1, (MA) <-- R0L, Rn <-- MA.
+    ADD  count          ; $An        R0 <-- (R0) + (Rn).
+    SUB  count          ; $Bn        R0 <-- (R0) - (Rn).
+    POPD @count         ; $Cn        MA = (Rn)-2, MA,MA+l <-- R0, Rn <-- MA.
+    CPR  count          ; $Dn        R13 <-- (R0) - (Rn), R14 <-- status flags.
+    INR  count          ; $En        Rn <-- (Rn) + 1.
+    DCR  count          ; $Fn        Rn <-- (Rn) - 1.
+.endrepeat
+
+.endif
diff --git a/test/asm/cpudetect/cpudetect.s b/test/asm/cpudetect/cpudetect.s
index 545e2fa56..3022038a2 100644
--- a/test/asm/cpudetect/cpudetect.s
+++ b/test/asm/cpudetect/cpudetect.s
@@ -12,6 +12,11 @@
    lax #$ea
 .endif
 
+.ifp6280
+   sax
+   cla
+.endif
+
 .ifpsc02
    jmp ($1234,x)
 .endif
@@ -20,8 +25,13 @@
    rmb0 $12
 .endif
 
-.ifp816
-   xba
+.ifpwc02
+   wai
+   stp
+.endif
+
+.ifpce02
+   ldz #$12
 .endif
 
 .ifp4510
@@ -40,6 +50,14 @@
    jsr $ff12
 .endif
 
+.ifp816
+   xba
+.endif
+
+.ifpsweet16
+   bk
+.endif
+
 
 ; step 2: check for bitwise compatibility of instructions sets
 ;         (made verbose for better reading with hexdump/hd(1))
@@ -56,6 +74,10 @@
    .byte 0,"CPU_ISET_6502X"
 .endif
 
+.if (.cpu .bitand CPU_ISET_6502DTV)
+   .byte 0,"CPU_ISET_6502DTV"
+.endif
+
 .if (.cpu .bitand CPU_ISET_65SC02)
    .byte 0,"CPU_ISET_65SC02"
 .endif
@@ -64,16 +86,12 @@
    .byte 0,"CPU_ISET_65C02"
 .endif
 
-.if (.cpu .bitand CPU_ISET_65816)
-   .byte 0,"CPU_ISET_65816"
+.if (.cpu .bitand CPU_ISET_W65C02)
+   .byte 0,"CPU_ISET_W65C02"
 .endif
 
-.if (.cpu .bitand CPU_ISET_SWEET16)
-   .byte 0,"CPU_ISET_SWEET16"
-.endif
-
-.if (.cpu .bitand CPU_ISET_HUC6280)
-   .byte 0,"CPU_ISET_HUC6280"
+.if (.cpu .bitand CPU_ISET_65CE02)
+   .byte 0,"CPU_ISET_65CE02"
 .endif
 
 .if (.cpu .bitand CPU_ISET_4510)
@@ -84,19 +102,25 @@
    .byte 0,"CPU_ISET_45GS02"
 .endif
 
-.if (.cpu .bitand CPU_ISET_6502DTV)
-   .byte 0,"CPU_ISET_6502DTV"
+.if (.cpu .bitand CPU_ISET_HUC6280)
+   .byte 0,"CPU_ISET_HUC6280"
 .endif
 
 .if (.cpu .bitand CPU_ISET_M740)
    .byte 0,"CPU_ISET_M740"
 .endif
 
-; FIXME: something with 65816 is quirky
-.if (.not .cpu .bitand CPU_ISET_65816)
-    .include "allinst.inc"
+.if (.cpu .bitand CPU_ISET_65816)
+   .byte 0,"CPU_ISET_65816"
 .endif
 
+.if (.cpu .bitand CPU_ISET_SWEET16)
+   .byte 0,"CPU_ISET_SWEET16"
+.endif
+
+
+.include "allinst.inc"
+
 
 ; step 3: switch through all supported cpus to verify the pseudo-op is there
 
@@ -104,8 +128,12 @@
 .p02X
 .psc02
 .pc02
-.p816
+.pwc02
+.pce02
 .p4510
 .p45GS02
 .pdtv
+.p6280
 .pm740
+.p816
+.psweet16
diff --git a/test/asm/cpudetect/huc6280-cpudetect.ref b/test/asm/cpudetect/huc6280-cpudetect.ref
index 646e0f48c..6ae287fdf 100644
Binary files a/test/asm/cpudetect/huc6280-cpudetect.ref and b/test/asm/cpudetect/huc6280-cpudetect.ref differ
diff --git a/test/asm/cpudetect/sweet16-cpudetect.ref b/test/asm/cpudetect/sweet16-cpudetect.ref
new file mode 100644
index 000000000..98d33127a
Binary files /dev/null and b/test/asm/cpudetect/sweet16-cpudetect.ref differ
diff --git a/test/asm/cpudetect/w65c02-cpudetect.ref b/test/asm/cpudetect/w65c02-cpudetect.ref
new file mode 100644
index 000000000..094210464
Binary files /dev/null and b/test/asm/cpudetect/w65c02-cpudetect.ref differ
diff --git a/test/asm/opcodes/65ce02-opcodes.ref b/test/asm/opcodes/65ce02-opcodes.ref
new file mode 100644
index 000000000..b65b12e61
Binary files /dev/null and b/test/asm/opcodes/65ce02-opcodes.ref differ
diff --git a/test/asm/opcodes/65ce02-opcodes.s b/test/asm/opcodes/65ce02-opcodes.s
new file mode 100644
index 000000000..ecdd7d747
--- /dev/null
+++ b/test/asm/opcodes/65ce02-opcodes.s
@@ -0,0 +1,278 @@
+.setcpu "65CE02"
+
+   brk
+   ora ($05,x)
+   cle
+   see
+   tsb $02
+   ora $02
+   asl $02
+   rmb0 $02
+   php
+   ora #$01
+   asl
+   tsy
+   tsb $1234
+   ora $1234
+   asl $1234
+   bbr0 $02,*+$34
+
+   bpl *+$32
+   ora ($06),y
+   ora ($07),z
+   lbpl *+$3133 ; bpl *+$3133
+   trb $02
+   ora $03,x
+   asl $03,x
+   rmb1 $02
+   clc
+   ora $1456,y
+   inc
+   inz
+   trb $1234
+   ora $1345,x
+   asl $1345,x
+   bbr1 $02,*+$34
+
+   jsr $1234
+   and ($05,x)
+   jsr ($2345)
+   jsr ($2456,x)
+   bit $02
+   and $02
+   rol $02
+   rmb2 $02
+   plp
+   and #$01
+   rol
+   tys
+   bit $1234
+   and $1234
+   rol $1234
+   bbr2 $02,*+$34
+
+   bmi *+$32
+   and ($06),y
+   and ($07),z
+   lbmi *+$3133 ; bmi *+$3133
+   bit $03,x
+   and $03,x
+   rol $03,x
+   rmb3 $02
+   sec
+   and $1456,y
+   dec
+   dez
+   bit $1345,x
+   and $1345,x
+   rol $1345,x
+   bbr3 $02,*+$34
+
+   rti
+   eor ($05,x)
+   neg
+   asr
+   asr $02
+   eor $02
+   lsr $02
+   rmb4 $02
+   pha
+   eor #$01
+   lsr
+   taz
+   jmp $1234
+   eor $1234
+   lsr $1234
+   bbr4 $02,*+$34
+
+   bvc *+$32
+   eor ($06),y
+   eor ($07),z
+   lbvc *+$3133 ; bvc *+$3133
+   asr $03,x
+   eor $03,x
+   lsr $03,x
+   rmb5 $02
+   cli
+   eor $1456,y
+   phy
+   tab
+   aug
+   eor $1345,x
+   lsr $1345,x
+   bbr5 $02,*+$34
+
+   rts
+   adc ($05,x)
+   rtn #$09
+   bsr *+$3133
+   stz $02
+   adc $02
+   ror $02
+   rmb6 $02
+   pla
+   adc #$01
+   ror
+   tza
+   jmp ($2345)
+   adc $1234
+   ror $1234
+   bbr6 $02,*+$34
+
+   bvs *+$32
+   adc ($06),y
+   adc ($07),z
+   lbvs *+$3133 ; bvs *+$3133
+   stz $03,x
+   adc $03,x
+   ror $03,x
+   rmb7 $02
+   sei
+   adc $1456,y
+   ply
+   tba
+   jmp ($2456,x)
+   adc $1345,x
+   ror $1345,x
+   bbr7 $02,*+$34
+
+   bra *+$32
+   sta ($05,x)
+   sta ($0f,s),y
+   sta ($0f,sp),y
+   lbra *+$3133 ; bra *+$3133
+   sty $02
+   sta $02
+   stx $02
+   smb0 $02
+   dey
+   bit #$01
+   txa
+   sty $1345,x
+   sty $1234
+   sta $1234
+   stx $1234
+   bbs0 $02,*+$34
+
+   bcc *+$32
+   sta ($06),y
+   sta ($07),z
+   lbcc *+$3133 ; bcc *+$3133
+   sty $03,x
+   sta $03,x
+   stx $04,y
+   smb1 $02
+   tya
+   sta $1456,y
+   txs
+   stx $1456,y
+   stz $1234
+   sta $1345,x
+   stz $1345,x
+   bbs1 $02,*+$34
+
+   ldy #$01
+   lda ($05,x)
+   ldx #$01
+   ldz #$01
+   ldy $02
+   lda $02
+   ldx $02
+   smb2 $02
+   tay
+   lda #$01
+   tax
+   ldz $1234
+   ldy $1234
+   lda $1234
+   ldx $1234
+   bbs2 $02,*+$34
+
+   bcs *+$32
+   lda ($06),y
+   lda ($07),z
+   lbcs *+$3133 ; bcs *+$3133
+   ldy $03,x
+   lda $03,x
+   ldx $04,y
+   smb3 $02
+   clv
+   lda $1456,y
+   tsx
+   ldz $1345,x
+   ldy $1345,x
+   lda $1345,x
+   ldx $1456,y
+   bbs3 $02,*+$34
+
+   cpy #$01
+   cmp ($05,x)
+   cpz #$01
+   dew $02
+   cpy $02
+   cmp $02
+   dec $02
+   smb4 $02
+   iny
+   cmp #$01
+   dex
+   asw $1234
+   cpy $1234
+   cmp $1234
+   dec $1234
+   bbs4 $02,*+$34
+
+   bne *+$32
+   cmp ($06),y
+   cmp ($07),z
+   lbne *+$3133 ; bne *+$3133
+   cpz $02
+   cmp $03,x
+   dec $03,x
+   smb5 $02
+   cld
+   cmp $1456,y
+   phx
+   phz
+   cpz $1234
+   cmp $1345,x
+   dec $1345,x
+   bbs5 $02,*+$34
+
+   cpx #$01
+   sbc ($05,x)
+   lda ($0f,s),y
+   lda ($0f,sp),y
+   inw $02
+   cpx $02
+   sbc $02
+   inc $02
+   smb6 $02
+   inx
+   sbc #$01
+   eom
+   nop
+   row $1234
+   cpx $1234
+   sbc $1234
+   inc $1234
+   bbs6 $02,*+$34
+
+   beq *+$32
+   sbc ($06),y
+   sbc ($07),z
+   lbeq *+$3133 ; beq *+$3133
+   phd #$089a
+   phw #$089a
+   sbc $03,x
+   inc $03,x
+   smb7 $02
+   sed
+   sbc $1456,y
+   plx
+   plz
+   phd $1234
+   phw $1234
+   sbc $1345,x
+   inc $1345,x
+   bbs7 $02,*+$34
diff --git a/test/asm/opcodes/sweet16-opcodes.ref b/test/asm/opcodes/sweet16-opcodes.ref
new file mode 100644
index 000000000..af128b55f
Binary files /dev/null and b/test/asm/opcodes/sweet16-opcodes.ref differ
diff --git a/test/asm/opcodes/sweet16-opcodes.s b/test/asm/opcodes/sweet16-opcodes.s
new file mode 100644
index 000000000..f283c6093
--- /dev/null
+++ b/test/asm/opcodes/sweet16-opcodes.s
@@ -0,0 +1,34 @@
+.setcpu "SWEET16"
+
+    RTN                 ; $00      Return to 6502 code.
+    BR   LABEL          ; $01 ea   Unconditional Branch.
+    BNC  LABEL          ; $02 ea   Branch if Carry=0.
+    BC   LABEL          ; $03 ea   Branch if Carry=1.
+    BP   LABEL          ; $04 ea   Branch if last result positive.
+    BM   LABEL          ; $0S ea   Branch if last result negative.
+    BZ   LABEL          ; $06 ea   Branch if last result zero.
+    BNZ  LABEL          ; $07 ea   Branch if last result non-zero.
+    BM1  LABEL          ; $08 ea   Branch if last result = -1.
+    BNM1 LABEL          ; $09 ea   Branch if last result not -1.
+    BK                  ; $0A      Execute 6502 BRK instruction.
+    RS                  ; $0B      Return from SWEET-16 subroutine.
+    BS   LABEL          ; $0C ea   Call SWEET-16 subroutine.
+LABEL:
+
+.repeat 16, count
+    SET  count,$1234    ; $1n lo hi  Rn <-- value.
+    LD   count          ; $2n        R0 <-- (Rn).
+    ST   count          ; $3n        Rn <-- (R0).
+    LD   @count         ; $4n        MA = (Rn), ROL <-- (MA), Rn <-- MA+1, R0H <-- 0.
+    ST   @count         ; $5n        MA = (Rn), MA <-- (R0L), Rn <-- MA+1.
+    LDD  @count         ; $6n        MA = (Rn), R0 <-- (MA, MA+1), Rn <-- MA+2.
+    STD  @count         ; $7n        MA = (Rn), MA,MA+l <-- (R0), Rn <-- MA+2.
+    POP  @count         ; $8n        MA = (Rn)-1, R0L <-- (MA), R0H <-- 0, Rn <-- MA.
+    STP  @count         ; $9n        MA <-- (Rn)-1, (MA) <-- R0L, Rn <-- MA.
+    ADD  count          ; $An        R0 <-- (R0) + (Rn).
+    SUB  count          ; $Bn        R0 <-- (R0) - (Rn).
+    POPD @count         ; $Cn        MA = (Rn)-2, MA,MA+l <-- R0, Rn <-- MA.
+    CPR  count          ; $Dn        R13 <-- (R0) - (Rn), R14 <-- status flags.
+    INR  count          ; $En        Rn <-- (Rn) + 1.
+    DCR  count          ; $Fn        Rn <-- (Rn) - 1.
+.endrepeat
diff --git a/test/asm/opcodes/w65c02-opcodes.ref b/test/asm/opcodes/w65c02-opcodes.ref
new file mode 100644
index 000000000..2d44045cb
Binary files /dev/null and b/test/asm/opcodes/w65c02-opcodes.ref differ
diff --git a/test/asm/opcodes/w65c02-opcodes.s b/test/asm/opcodes/w65c02-opcodes.s
new file mode 100644
index 000000000..0fe741518
--- /dev/null
+++ b/test/asm/opcodes/w65c02-opcodes.s
@@ -0,0 +1,258 @@
+.setcpu "W65C02"
+
+   brk
+   ora     ($12,x)
+   .byte   $02
+   .byte   $03
+   tsb     $12
+   ora     $12
+   asl     $12
+   rmb0    $12
+   php
+   ora     #$12
+   asl     a
+   .byte   $0B
+   tsb     $3456
+   ora     $3456
+   asl     $3456
+   bbr0    $12,*+122
+   bpl     *+122
+   ora     ($12),y
+   ora     ($12)
+   .byte   $13
+   trb     $12
+   ora     $12,x
+   asl     $12,x
+   rmb1    $12
+   clc
+   ora     $3456,y
+   inc     a
+   .byte   $1B
+   trb     $3456
+   ora     $3456,x
+   asl     $3456,x
+   bbr1    $12,*+122
+   jsr     $3456
+   and     ($12,x)
+   .byte   $22
+   .byte   $23
+   bit     $12
+   and     $12
+   rol     $12
+   rmb2    $12
+   plp
+   and     #$12
+   rol     a
+   .byte   $2B
+   bit     $3456
+   and     $3456
+   rol     $3456
+   bbr2    $12,*+122
+   bmi     *+122
+   and     ($12),y
+   and     ($12)
+   .byte   $33
+   bit     $12,x
+   and     $12,x
+   rol     $12,x
+   rmb3    $12
+   sec
+   and     $3456,y
+   dec     a
+   .byte   $3B
+   bit     $3456,x
+   and     $3456,x
+   rol     $3456,x
+   bbr3    $12,*+122
+   rti
+   eor     ($12,x)
+   .byte   $42
+   .byte   $43
+   .byte   $44
+   eor     $12
+   lsr     $12
+   rmb4    $12
+   pha
+   eor     #$12
+   lsr     a
+   .byte   $4B
+   jmp     $3456
+   eor     $3456
+   lsr     $3456
+   bbr4    $12,*+122
+   bvc     *+122
+   eor     ($12),y
+   eor     ($12)
+   .byte   $53
+   .byte   $54
+   eor     $12,x
+   lsr     $12,x
+   rmb5    $12
+   cli
+   eor     $3456,y
+   phy
+   .byte   $5B
+   .byte   $5C
+   eor     $3456,x
+   lsr     $3456,x
+   bbr5    $12,*+122
+   rts
+   adc     ($12,x)
+   .byte   $62
+   .byte   $63
+   stz     $12
+   adc     $12
+   ror     $12
+   rmb6    $12
+   pla
+   adc     #$12
+   ror     a
+   .byte   $6B
+   jmp     ($3456)
+   adc     $3456
+   ror     $3456
+   bbr6    $12,*+122
+   bvs     *+122
+   adc     ($12),y
+   adc     ($12)
+   .byte   $73
+   stz     $12,x
+   adc     $12,x
+   ror     $12,x
+   rmb7    $12
+   sei
+   adc     $3456,y
+   ply
+   .byte   $7B
+   jmp     ($3456,x)
+   adc     $3456,x
+   ror     $3456,x
+   bbr7    $12,*+122
+   bra     *+122
+   sta     ($12,x)
+   .byte   $82
+   .byte   $83
+   sty     $12
+   sta     $12
+   stx     $12
+   smb0    $12
+   dey
+   bit     #$12
+   txa
+   .byte   $8B
+   sty     $3456
+   sta     $3456
+   stx     $3456
+   bbs0    $12,*+122
+   bcc     *+122
+   sta     ($12),y
+   sta     ($12)
+   .byte   $93
+   sty     $12,x
+   sta     $12,x
+   stx     $12,y
+   smb1    $12
+   tya
+   sta     $3456,y
+   txs
+   .byte   $9B
+   stz     $3456
+   sta     $3456,x
+   stz     $3456,x
+   bbs1    $12,*+122
+   ldy     #$12
+   lda     ($12,x)
+   ldx     #$12
+   .byte   $A3
+   ldy     $12
+   lda     $12
+   ldx     $12
+   smb2    $12
+   tay
+   lda     #$12
+   tax
+   .byte   $AB
+   ldy     $3456
+   lda     $3456
+   ldx     $3456
+   bbs2    $12,*+122
+   bcs     *+122
+   lda     ($12),y
+   lda     ($12)
+   .byte   $B3
+   ldy     $12,x
+   lda     $12,x
+   ldx     $12,y
+   smb3    $12
+   clv
+   lda     $3456,y
+   tsx
+   .byte   $BB
+   ldy     $3456,x
+   lda     $3456,x
+   ldx     $3456,y
+   bbs3    $12,*+122
+   cpy     #$12
+   cmp     ($12,x)
+   .byte   $C2
+   .byte   $C3
+   cpy     $12
+   cmp     $12
+   dec     $12
+   smb4    $12
+   iny
+   cmp     #$12
+   dex
+   wai
+   cpy     $3456
+   cmp     $3456
+   dec     $3456
+   bbs4    $12,*+122
+   bne     *+122
+   cmp     ($12),y
+   cmp     ($12)
+   .byte   $D3
+   .byte   $D4
+   cmp     $12,x
+   dec     $12,x
+   smb5    $12
+   cld
+   cmp     $3456,y
+   phx
+   stp
+   .byte   $DC
+   cmp     $3456,x
+   dec     $3456,x
+   bbs5    $12,*+122
+   cpx     #$12
+   sbc     ($12,x)
+   .byte   $E2
+   .byte   $E3
+   cpx     $12
+   sbc     $12
+   inc     $12
+   smb6    $12
+   inx
+   sbc     #$12
+   nop
+   .byte   $EB
+   cpx     $3456
+   sbc     $3456
+   inc     $3456
+   bbs6    $12,*+122
+   beq     *+122
+   sbc     ($12),y
+   sbc     ($12)
+   .byte   $F3
+   .byte   $F4
+   sbc     $12,x
+   inc     $12,x
+   smb7    $12
+   sed
+   sbc     $3456,y
+   plx
+   .byte   $FB
+   .byte   $FC
+   sbc     $3456,x
+   inc     $3456,x
+   bbs7    $12,*+122
diff --git a/test/asm/val/ismnemonic.s b/test/asm/val/ismnemonic.s
index 2d131e7a9..831a8a3c7 100644
--- a/test/asm/val/ismnemonic.s
+++ b/test/asm/val/ismnemonic.s
@@ -8,7 +8,10 @@
 ;    "6502DTV"
 ;    "65SC02"
 ;    "65C02"
+;    "65CE02"
+;    "W65C02"
 ;    "4510"
+;    "45GS02"
 ;    "huc6280"
 ;    "65816"
 ;    "sweet16"
@@ -415,6 +418,107 @@ test_Ismnemonic smb5
 test_Ismnemonic smb6
 test_Ismnemonic smb7
 test_Ismnemonic sta
+test_Ismnemonic stx
+test_Ismnemonic sty
+test_Ismnemonic stz
+test_Ismnemonic tax
+test_Ismnemonic tay
+test_Ismnemonic trb
+test_Ismnemonic tsb
+test_Ismnemonic tsx
+test_Ismnemonic txa
+test_Ismnemonic txs
+test_Ismnemonic tya
+
+
+.setcpu "W65C02"
+test_Ismnemonic adc
+test_Ismnemonic and
+test_Ismnemonic asl
+test_Ismnemonic bbr0
+test_Ismnemonic bbr1
+test_Ismnemonic bbr2
+test_Ismnemonic bbr3
+test_Ismnemonic bbr4
+test_Ismnemonic bbr5
+test_Ismnemonic bbr6
+test_Ismnemonic bbr7
+test_Ismnemonic bbs0
+test_Ismnemonic bbs1
+test_Ismnemonic bbs2
+test_Ismnemonic bbs3
+test_Ismnemonic bbs4
+test_Ismnemonic bbs5
+test_Ismnemonic bbs6
+test_Ismnemonic bbs7
+test_Ismnemonic bcc
+test_Ismnemonic bcs
+test_Ismnemonic beq
+test_Ismnemonic bit
+test_Ismnemonic bmi
+test_Ismnemonic bne
+test_Ismnemonic bpl
+test_Ismnemonic bra
+test_Ismnemonic brk
+test_Ismnemonic bvc
+test_Ismnemonic bvs
+test_Ismnemonic clc
+test_Ismnemonic cld
+test_Ismnemonic cli
+test_Ismnemonic clv
+test_Ismnemonic cmp
+test_Ismnemonic cpx
+test_Ismnemonic cpy
+test_Ismnemonic dea
+test_Ismnemonic dec
+test_Ismnemonic dex
+test_Ismnemonic dey
+test_Ismnemonic eor
+test_Ismnemonic ina
+test_Ismnemonic inc
+test_Ismnemonic inx
+test_Ismnemonic iny
+test_Ismnemonic jmp
+test_Ismnemonic jsr
+test_Ismnemonic lda
+test_Ismnemonic ldx
+test_Ismnemonic ldy
+test_Ismnemonic lsr
+test_Ismnemonic nop
+test_Ismnemonic ora
+test_Ismnemonic pha
+test_Ismnemonic php
+test_Ismnemonic phx
+test_Ismnemonic phy
+test_Ismnemonic pla
+test_Ismnemonic plp
+test_Ismnemonic plx
+test_Ismnemonic ply
+test_Ismnemonic rmb0
+test_Ismnemonic rmb1
+test_Ismnemonic rmb2
+test_Ismnemonic rmb3
+test_Ismnemonic rmb4
+test_Ismnemonic rmb5
+test_Ismnemonic rmb6
+test_Ismnemonic rmb7
+test_Ismnemonic rol
+test_Ismnemonic ror
+test_Ismnemonic rti
+test_Ismnemonic rts
+test_Ismnemonic sbc
+test_Ismnemonic sec
+test_Ismnemonic sed
+test_Ismnemonic sei
+test_Ismnemonic smb0
+test_Ismnemonic smb1
+test_Ismnemonic smb2
+test_Ismnemonic smb3
+test_Ismnemonic smb4
+test_Ismnemonic smb5
+test_Ismnemonic smb6
+test_Ismnemonic smb7
+test_Ismnemonic sta
 test_Ismnemonic stp
 test_Ismnemonic stx
 test_Ismnemonic sty
@@ -429,6 +533,141 @@ test_Ismnemonic txs
 test_Ismnemonic tya
 test_Ismnemonic wai
 
+.setcpu "65CE02"
+test_Ismnemonic adc
+test_Ismnemonic and
+test_Ismnemonic asl
+test_Ismnemonic asr
+test_Ismnemonic asw
+test_Ismnemonic aug
+test_Ismnemonic bbr0
+test_Ismnemonic bbr1
+test_Ismnemonic bbr2
+test_Ismnemonic bbr3
+test_Ismnemonic bbr4
+test_Ismnemonic bbr5
+test_Ismnemonic bbr6
+test_Ismnemonic bbr7
+test_Ismnemonic bbs0
+test_Ismnemonic bbs1
+test_Ismnemonic bbs2
+test_Ismnemonic bbs3
+test_Ismnemonic bbs4
+test_Ismnemonic bbs5
+test_Ismnemonic bbs6
+test_Ismnemonic bbs7
+test_Ismnemonic bcc
+test_Ismnemonic bcs
+test_Ismnemonic beq
+test_Ismnemonic bit
+test_Ismnemonic bmi
+test_Ismnemonic bne
+test_Ismnemonic bpl
+test_Ismnemonic bra
+test_Ismnemonic brk
+test_Ismnemonic bsr
+test_Ismnemonic bvc
+test_Ismnemonic bvs
+test_Ismnemonic clc
+test_Ismnemonic cld
+test_Ismnemonic cle
+test_Ismnemonic cli
+test_Ismnemonic clv
+test_Ismnemonic cmp
+test_Ismnemonic cpx
+test_Ismnemonic cpy
+test_Ismnemonic cpz
+test_Ismnemonic dea
+test_Ismnemonic dec
+test_Ismnemonic dew
+test_Ismnemonic dex
+test_Ismnemonic dey
+test_Ismnemonic dez
+test_Ismnemonic eom
+test_Ismnemonic eor
+test_Ismnemonic ina
+test_Ismnemonic inc
+test_Ismnemonic inw
+test_Ismnemonic inx
+test_Ismnemonic iny
+test_Ismnemonic inz
+test_Ismnemonic jmp
+test_Ismnemonic jsr
+test_Ismnemonic lbcc
+test_Ismnemonic lbcs
+test_Ismnemonic lbeq
+test_Ismnemonic lbmi
+test_Ismnemonic lbne
+test_Ismnemonic lbpl
+test_Ismnemonic lbra
+test_Ismnemonic lbvc
+test_Ismnemonic lbvs
+test_Ismnemonic lda
+test_Ismnemonic ldx
+test_Ismnemonic ldy
+test_Ismnemonic ldz
+test_Ismnemonic lsr
+test_Ismnemonic neg
+test_Ismnemonic nop
+test_Ismnemonic ora
+test_Ismnemonic pha
+test_Ismnemonic phd
+test_Ismnemonic php
+test_Ismnemonic phw
+test_Ismnemonic phx
+test_Ismnemonic phy
+test_Ismnemonic phz
+test_Ismnemonic pla
+test_Ismnemonic plp
+test_Ismnemonic plx
+test_Ismnemonic ply
+test_Ismnemonic plz
+test_Ismnemonic rmb0
+test_Ismnemonic rmb1
+test_Ismnemonic rmb2
+test_Ismnemonic rmb3
+test_Ismnemonic rmb4
+test_Ismnemonic rmb5
+test_Ismnemonic rmb6
+test_Ismnemonic rmb7
+test_Ismnemonic rol
+test_Ismnemonic ror
+test_Ismnemonic row
+test_Ismnemonic rti
+test_Ismnemonic rtn
+test_Ismnemonic rts
+test_Ismnemonic sbc
+test_Ismnemonic sec
+test_Ismnemonic sed
+test_Ismnemonic see
+test_Ismnemonic sei
+test_Ismnemonic smb0
+test_Ismnemonic smb1
+test_Ismnemonic smb2
+test_Ismnemonic smb3
+test_Ismnemonic smb4
+test_Ismnemonic smb5
+test_Ismnemonic smb6
+test_Ismnemonic smb7
+test_Ismnemonic sta
+test_Ismnemonic stx
+test_Ismnemonic sty
+test_Ismnemonic stz
+test_Ismnemonic tab
+test_Ismnemonic tax
+test_Ismnemonic tay
+test_Ismnemonic taz
+test_Ismnemonic tba
+test_Ismnemonic trb
+test_Ismnemonic tsb
+test_Ismnemonic tsx
+test_Ismnemonic tsy
+test_Ismnemonic txa
+test_Ismnemonic txs
+test_Ismnemonic tya
+test_Ismnemonic tys
+test_Ismnemonic tza
+
 .setcpu "4510"
 test_Ismnemonic adc
 test_Ismnemonic and
@@ -564,6 +803,159 @@ test_Ismnemonic tya
 test_Ismnemonic tys
 test_Ismnemonic tza
 
+.setcpu "45GS02"
+test_Ismnemonic adc
+test_Ismnemonic and
+test_Ismnemonic asl
+test_Ismnemonic asr
+test_Ismnemonic asw
+test_Ismnemonic bbr0
+test_Ismnemonic bbr1
+test_Ismnemonic bbr2
+test_Ismnemonic bbr3
+test_Ismnemonic bbr4
+test_Ismnemonic bbr5
+test_Ismnemonic bbr6
+test_Ismnemonic bbr7
+test_Ismnemonic bbs0
+test_Ismnemonic bbs1
+test_Ismnemonic bbs2
+test_Ismnemonic bbs3
+test_Ismnemonic bbs4
+test_Ismnemonic bbs5
+test_Ismnemonic bbs6
+test_Ismnemonic bbs7
+test_Ismnemonic bcc
+test_Ismnemonic bcs
+test_Ismnemonic beq
+test_Ismnemonic bit
+test_Ismnemonic bmi
+test_Ismnemonic bne
+test_Ismnemonic bpl
+test_Ismnemonic bra
+test_Ismnemonic brk
+test_Ismnemonic bsr
+test_Ismnemonic bvc
+test_Ismnemonic bvs
+test_Ismnemonic clc
+test_Ismnemonic cld
+test_Ismnemonic cle
+test_Ismnemonic cli
+test_Ismnemonic clv
+test_Ismnemonic cmp
+test_Ismnemonic cpx
+test_Ismnemonic cpy
+test_Ismnemonic cpz
+test_Ismnemonic dea
+test_Ismnemonic dec
+test_Ismnemonic dew
+test_Ismnemonic dex
+test_Ismnemonic dey
+test_Ismnemonic dez
+test_Ismnemonic eom
+test_Ismnemonic eor
+test_Ismnemonic ina
+test_Ismnemonic inc
+test_Ismnemonic inw
+test_Ismnemonic inx
+test_Ismnemonic iny
+test_Ismnemonic inz
+test_Ismnemonic jmp
+test_Ismnemonic jsr
+test_Ismnemonic lbcc
+test_Ismnemonic lbcs
+test_Ismnemonic lbeq
+test_Ismnemonic lbmi
+test_Ismnemonic lbne
+test_Ismnemonic lbpl
+test_Ismnemonic lbra
+test_Ismnemonic lbvc
+test_Ismnemonic lbvs
+test_Ismnemonic lda
+test_Ismnemonic ldx
+test_Ismnemonic ldy
+test_Ismnemonic ldz
+test_Ismnemonic lsr
+test_Ismnemonic map
+test_Ismnemonic neg
+test_Ismnemonic nop
+test_Ismnemonic ora
+test_Ismnemonic pha
+test_Ismnemonic phd
+test_Ismnemonic php
+test_Ismnemonic phw
+test_Ismnemonic phx
+test_Ismnemonic phy
+test_Ismnemonic phz
+test_Ismnemonic pla
+test_Ismnemonic plp
+test_Ismnemonic plx
+test_Ismnemonic ply
+test_Ismnemonic plz
+test_Ismnemonic rmb0
+test_Ismnemonic rmb1
+test_Ismnemonic rmb2
+test_Ismnemonic rmb3
+test_Ismnemonic rmb4
+test_Ismnemonic rmb5
+test_Ismnemonic rmb6
+test_Ismnemonic rmb7
+test_Ismnemonic rol
+test_Ismnemonic ror
+test_Ismnemonic row
+test_Ismnemonic rti
+test_Ismnemonic rtn
+test_Ismnemonic rts
+test_Ismnemonic sbc
+test_Ismnemonic sec
+test_Ismnemonic sed
+test_Ismnemonic see
+test_Ismnemonic sei
+test_Ismnemonic smb0
+test_Ismnemonic smb1
+test_Ismnemonic smb2
+test_Ismnemonic smb3
+test_Ismnemonic smb4
+test_Ismnemonic smb5
+test_Ismnemonic smb6
+test_Ismnemonic smb7
+test_Ismnemonic sta
+test_Ismnemonic stx
+test_Ismnemonic sty
+test_Ismnemonic stz
+test_Ismnemonic tab
+test_Ismnemonic tax
+test_Ismnemonic tay
+test_Ismnemonic taz
+test_Ismnemonic tba
+test_Ismnemonic trb
+test_Ismnemonic tsb
+test_Ismnemonic tsx
+test_Ismnemonic tsy
+test_Ismnemonic txa
+test_Ismnemonic txs
+test_Ismnemonic tya
+test_Ismnemonic tys
+test_Ismnemonic tza
+
+test_Ismnemonic adcq
+test_Ismnemonic andq
+test_Ismnemonic aslq
+test_Ismnemonic asrq
+test_Ismnemonic bitq
+test_Ismnemonic cmpq
+test_Ismnemonic deq
+test_Ismnemonic eorq
+test_Ismnemonic inq
+test_Ismnemonic ldq
+test_Ismnemonic lsrq
+test_Ismnemonic orq
+test_Ismnemonic sbcq
+test_Ismnemonic stq
+test_Ismnemonic rolq
+test_Ismnemonic rorq
+
+
 .setcpu "HuC6280"
 test_Ismnemonic adc
 test_Ismnemonic and