Input format
+Input format
Assembler syntax
@@ -426,20 +437,26 @@ Here are some examples for valid input lines:
The assembler accepts
-- all valid 6502 mnemonics when in 6502 mode (the default or after the
+
- all valid 6502 mnemonics when in
[
+ (the default or after the
]- all valid 6502 mnemonics plus a set of illegal instructions when in
-
[.
-]- all valid 6502DTV mnemonics when in 6502DTV mode (after the
+
- all valid 6502 mnemonics, plus a set of illegal instructions, when in
+
[ (after the
+ ]- all valid 6502DTV mnemonics when in
[ (after the
]- all valid 65SC02 mnemonics when in 65SC02 mode (after the
+
- all valid 65SC02 mnemonics when in
[ (after the
]- all valid 65C02 mnemonics when in 65C02 mode (after the
+
- all valid 65C02 mnemonics when in
[ (after the
]- all valid 65816 mnemonics when in 65816 mode (after the
+
- all valid 65816 mnemonics when in
[ (after the
]- all valid 4510 mnemonics when in 4510 mode (after the
+
- all valid 4510 mnemonics when in
[ (after the
]- all valid 45GS02 mnemonics when in
[ (after the
+ ]- all valid M740 mnemonics when in
[ (after the
+ ]
On 6502-derived platforms the
+6502 mode
-65816 mode
+In 6502 mode (which is the default) the assembler accepts all regular "legal"
+6502 mnemonics and addressing modes.
+
+6502X mode
+
+6502X mode is an extension to the normal 6502 mode. In this mode, several
+mnemonics for undocumented instructions of the NMOS 6502 CPUs are accepted.
+
+Note: Since these instructions are undocumented, there are no official mnemonics
+for them.
+
+
+ALR: A:=(A and #{imm})/2;
+ANC: A:= A and #{imm}; Generates opcode $0B.
+ANE: A:= (A or CONST) and X and #{imm};
+ARR: A:=(A and #{imm})/2;
+AXS: X:=A and X-#{imm};
+DCP: {addr}:={addr}-1; A-{addr};
+ISC: {addr}:={addr}+1; A:=A-{addr};
+JAM:
+LAS: A,X,S:={addr} and S;
+LAX: A,X:={addr};
+NOP: #{imm}; zp; zp,x; abs; abs,x
+RLA: {addr}:={addr}rol; A:=A and {addr};
+RRA: {addr}:={addr}ror; A:=A adc {addr};
+SAX: {addr}:=A and X;
+SHA: {addr}:=A and X and {addr hi +1};
+SHX: {addr}:=X and {addr hi +1};
+SHY: {addr}:=Y and {addr hi +1};
+SLO: {addr}:={addr}*2; A:=A or {addr};
+SRE: {addr}:={addr}/2; A:=A xor {addr};
+TAS: {addr}:=A and X and {addr hi +1}; SP:=A and X;
+
+
+
+DTV mode
+
+The C64DTV CPU is based on the 6510, but adds some instructions, and does not
+support all undocumented instructions.
+
+
+bra {rel} Generates opcode $12.
+sac #{imm} Generates opcode $32.
+sir #{imm} Generates opcode $42.
+
+
+Supported undocumented instructions:
+
+
+ALR: A:=(A and #{imm})/2;
+ANC: A:=A and #{imm}; Generates opcode $0B.
+ARR: A:=(A and #{imm})/2;
+AXS: X:=A and X-#{imm};
+LAS: A,X,S:={addr} and S;
+LAX: A,X:={addr};
+NOP: #{imm}; zp; zp,x; abs; abs,x
+RLA: {addr}:={addr}rol; A:=A and {addr};
+RRA: {addr}:={addr}ror; A:=A adc {addr};
+SHX: {addr}:=X and {addr hi +1};
+SHY: {addr}:=y and {addr hi +1};
+
+
+
+65SC02 mode
+
+65SC02 mode supports all regular 6502 instructions, plus the following:
+
+
+$04 tsb zp
+$0c tsb abs16
+$12 ora (zp)
+$14 trb zp
+$1a inc
+$1c trb abs16
+$32 and (zp)
+$34 bit zp, x
+$3a dec
+$3c bit abs16, x
+$52 eor (zp)
+$5a phy
+$64 stz zp
+$72 adc (zp)
+$74 stz zp, x
+$7a ply
+$7c jmp (abs16, x)
+$80 bra rel8
+$89 bit #imm8
+$92 sta (zp)
+$9c stz abs16
+$9e stz abs16, x
+$b2 lda (zp)
+$d2 cmp (zp)
+$da phx
+$f2 sbc (zp)
+$fa plx
+ 65C02 mode
+
+65C02 mode supports all "official" W65C02 opcodes.
+
+The R65C02 adds bit manipulation instructions:
+
+
+smbB zp set bit in zp location
+rmbB zp reset bit in zp location
+bbsB zp, rel8 branch if bit is set in zp location
+bbrB zp, rel8 branch if bit is reset in zp location
+
+$cb wai wait for interrupt
+$db stp wait for reset
+ 4510 mode
+
+The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX.
+It contains among other functions a slightly modified 65CE02/4502 CPU, to allow
+address mapping for 20 bits of address space (1 megabyte addressable area).
+
+The 4510 mode supports the complete (legal) 65CE02 instruction set, plus these
+three, which were changed/added:
+
+$5c map "4-byte NOP reserved for future expansion" on 65CE02
+$cb asw $1234 wai on W65C02
+$db phz stp on W65C02
+
+ uses these changes:
+
+LDA (d,SP),Y may also be written as LDA (d,S),Y
+(matching the 65816 notation).
+- All branch instruction allow now 16 bit offsets. To use a 16 bit
+branch you have to prefix these with an "L" (e.g. "
LBNE " instead of
+"BNE "). This might change at a later implementation of the assembler.
+
+
+For more information about the Commodore C65/C64DX and the 4510 CPU, see
+ and
+.
+
+45GS02 mode
+
+The 45GS02 is a microcontroller that is the core of the MEGA65.
+It is an extension of the 4510 CPU and adds 32-bit addressing and a 32-bit
+pseudo register Q that is comprised of the four registers A, X, Y, and Z.
+
+HUC6280 mode
+
+The HUC6280 is a superset of the R65C02. It adds some other instructions:
+
+
+$02 sxy
+$03 st0 #{imm}
+$13 st1 #{imm}
+$22 sax
+$23 st2 #{imm}
+$42 say
+$43 tma #{imm}
+$44 bsr {rel}
+$53 tam #{imm}
+$54 csl
+$62 cla
+$73 tii {addr}, {addr}, {addr}
+$82 clx
+$83 tst #{imm}, {zp}
+$82 clx
+$83 tst #{imm}, {zp}
+$93 tst #{imm}, {addr}
+$a3 tst #{imm}, {zp}, x
+$b3 tst #{imm}, {addr}, x
+$c2 cly
+$c3 tdd {addr}, {addr}, {addr}
+$d3 tin {addr}, {addr}, {addr}
+$d4 csh
+$e3 tia {addr}, {addr}, {addr}
+$f3 tai {addr}, {addr}, {addr}
+$f4 set
+ wai and stp .
+
+
+M740 mode
+
+The M740 is a microcontroller by Mitsubishi, which was marketed for embedded
+devices in the mid 80s. It is a superset of 6502, and a subset of 65SC02, plus
+some new instructions.
+
+For more information about the M740 Controllers, see
+.
+
+
+65816 mode
In 65816 mode, several aliases are accepted, in addition to the official
mnemonics:
@@ -480,56 +700,7 @@ or two far addresses whose high byte will be used.
-6502X mode
-
-6502X mode is an extension to the normal 6502 mode. In this mode, several
-mnemonics for illegal instructions of the NMOS 6502 CPUs are accepted. Since
-these instructions are illegal, there are no official mnemonics for them. The
-unofficial ones are taken from . Please note that only the
-ones marked as "stable" are supported. The following table uses information
-from the mentioned web page, for more information, see there.
-
-
-ALR: A:=(A and #{imm})/2;
-ANC: A:=A and #{imm}; Generates opcode $0B.
-ARR: A:=(A and #{imm})/2;
-AXS: X:=A and X-#{imm};
-DCP: {adr}:={adr}-1; A-{adr};
-ISC: {adr}:={adr}+1; A:=A-{adr};
-LAS: A,X,S:={adr} and S;
-LAX: A,X:={adr};
-RLA: {adr}:={adr}rol; A:=A and {adr};
-RRA: {adr}:={adr}ror; A:=A adc {adr};
-SAX: {adr}:=A and X;
-SLO: {adr}:={adr}*2; A:=A or {adr};
-SRE: {adr}:={adr}/2; A:=A xor {adr};
-
-
-
-4510 mode
-
-The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX.
-It contains among other functions a slightly modified 65CE02/4502 CPU, to allow
-address mapping for 20 bits of address space (1 megabyte addressable area).
-As compared to the description of the CPU in the
-
- uses these changes:
-
-LDA (d,SP),Y may also be written as LDA (d,S),Y
-(matching the 65816 notataion).
-- All branch instruction allow now 16 bit offsets. To use a 16 bit
-branch you have to prefix these with an "L" (e.g. "
LBNE " instead of
-"BNE "). This might change at a later implementation of the assembler.
-
-For more information about the Commodore C65/C64DX and the 4510 CPU, see
- and
-.
-
-
-sweet16 mode
+sweet16 mode
SWEET 16 is an interpreter for a pseudo 16 bit CPU written by Steve Wozniak
for the Apple ][ machines. It is available in the Apple ][ ROM. ca65 can
@@ -3246,6 +3417,12 @@ See: .IFP45GS02
+
+ Conditional assembly: Check if the assembler is currently in 45GS02 mode
+ (see .IFP816
Conditional assembly: Check if the assembler is currently in 65816 mode
@@ -3264,6 +3441,12 @@ See: .IFPM740
+
+ Conditional assembly: Check if the assembler is currently in M740 mode
+ (see .IFPSC02
Conditional assembly: Check if the assembler is currently in 65SC02 mode
@@ -3623,8 +3806,9 @@ See:
, .P02X
@@ -3643,19 +3827,30 @@ See: .P45GS02
+
+ Enable the 45GS02 instruction set. This is a superset of the 4510, 65C02, and
+ 6502 instruction sets.
+
+ See: .P816
Enable the 65816 instruction set. This is a superset of the 65SC02 and
6502 instruction sets.
See: .PAGELEN, .PAGELENGTH
@@ -3682,9 +3877,9 @@ See: .PDTV
@@ -3694,6 +3889,14 @@ See: .PM740
+
+ Enable the M740 instruction set. This is a superset of the 6502
+ instruction set.
+
+ See: .POPCHARMAP
Pop the last character mapping from the stack, and activate it.
@@ -3779,9 +3982,9 @@ See: .PUSHCHARMAP
@@ -4028,7 +4231,7 @@ See: / pseudo variable may
@@ -4822,6 +5032,7 @@ it is possible to determine if the
instruction is supported, which is the case for the 65SC02, 65C02 and 65816
CPUs (the latter two are upwards compatible to the 65SC02).
+see section [ and following.
].MACPACK module
diff --git a/doc/da65.sgml b/doc/da65.sgml
index 94fbfbd29..7300d3d71 100644
--- a/doc/da65.sgml
+++ b/doc/da65.sgml
@@ -110,20 +110,18 @@ Here is a description of all the command line options:
Set the CPU type. The option takes a parameter, which may be one of
- - 6502
-
- 6502x
-
- 6502dtv
-
- 65sc02
-
- 65c02
-
- 65816
-
- huc6280
-
- 4510
+
- 6502 - NMOS 6502 (all legal instructions)
+
- 6502X - NMOS 6502 with all undocumented instructions
+
- 6502DTV - the emulated CPU of the C64DTV device
+
- 65SC02 - first CMOS instruction set (no bit manipulation, no wai/stp)
+
- 65C02 - full CMOS instruction set (has bit manipulation and wai/stp)
+
- 65816 - the CPU of the SNES, and the SCPU
+
- HuC6280 - the CPU of the PC engine
+
- 4510 - the CPU of the Commodore C65
+
- 45GS02 - the CPU of the Commodore MEGA65
+
- M740 - a Microcontroller by Mitsubishi
- 6502x is for the NMOS 6502 with unofficial opcodes. 6502dtv is for the
- emulated CPU of the C64DTV device. huc6280 is the CPU of the PC engine.
- 4510 is the CPU of the Commodore C65. 65816 is the CPU of the SNES.
-
-F, --formfeeds Supported CPUs
+With the command line option
+ [ - NMOS 6502 (all legal instructions)
+ ][ - NMOS 6502 with all undocumented instructions
+ ][ - the emulated CPU of the C64DTV device
+ ][ - first CMOS instruction set (no bit manipulation, no wai/stp)
+ ][ - full CMOS instruction set (has bit manipulation and wai/stp)
+ ][ - the CPU of the SNES, and the SCPU
+ ][ - the CPU of the PC engine
+ ][ - the CPU of the Commodore C65
+ ][ - the CPU of the Commodore MEGA65
+ ][ - a Microcontroller by Mitsubishi
+ ]
+
+for more details on the various CPUs, see 6502 mode
+
The default (no CPU given on the command line or in the 6502X mode
+Using 6502X as CPU the illegal opcodes of 6502 CPU are detected and displayed.
+
+
+DTV mode
+
+6502DTV setting recognizes the emulated CPU instructions of the C64DTV device.
+
+
+65SC02 mode
+
+The first CMOS instruction set, without bit manipulation or wai/stp.
+
+
+65C02 mode
+
+The 65C02 understands the same opcodes as the 65SC02, plus 16 additional bit
+manipulation and bit test-and-branch commands.
+
+This mode also supports wai/stp.
+
+
+4510 mode
When disassembling 4510 code, due to handling of 16-bit wide branches, da65
can produce output that can not be re-assembled, when one or more of those
branches point outside of the disassembled memory. This can happen when text
or binary data is processed.
+
+45GS02 mode
+
+All compound instructions are supported.
+
+
+HUC6280 mode
+
+All special opcodes are supported.
+
+
+M740 mode
+
+All special opcodes are supported.
+
+
+65816 mode
+
The 65816 support requires annotating ranges with the M and X flag states.
This can be recorded with an emulator that supports Code and Data Logging,
for example. Disassemble one bank at a time.
diff --git a/libsrc/Makefile b/libsrc/Makefile
index 2f1b604d7..1ec0bcfea 100644
--- a/libsrc/Makefile
+++ b/libsrc/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
ifneq ($(shell echo),)
CMD_EXE = 1
endif
diff --git a/libsrc/apple2/tgi/a2.hi.s b/libsrc/apple2/tgi/a2.hi.s
index 27c494421..0398701eb 100644
--- a/libsrc/apple2/tgi/a2.hi.s
+++ b/libsrc/apple2/tgi/a2.hi.s
@@ -222,14 +222,9 @@ DONE:
bit TXTSET
bit LOWSCR
- .ifndef __APPLE2ENH__
- bit machinetype
- bpl reset_wndtop
- .endif
; Limit SET80COL-HISCR to text
bit LORES
-reset_wndtop:
; Reset the text window top
lda #$00
sta WNDTOP
diff --git a/samples/Makefile b/samples/Makefile
index d9bda45d4..0a56af3c1 100644
--- a/samples/Makefile
+++ b/samples/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
#
# Makefile for cc65 samples
#
diff --git a/samples/apple2/Makefile b/samples/apple2/Makefile
index 55e84aed6..d9fa40f66 100644
--- a/samples/apple2/Makefile
+++ b/samples/apple2/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/samples/atari2600/Makefile b/samples/atari2600/Makefile
index bd2ebc41a..71264792d 100644
--- a/samples/atari2600/Makefile
+++ b/samples/atari2600/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/samples/atari5200/Makefile b/samples/atari5200/Makefile
index 2fbda11d9..1bdf1b75d 100644
--- a/samples/atari5200/Makefile
+++ b/samples/atari5200/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/samples/cbm/Makefile b/samples/cbm/Makefile
index 4b89722d2..a593569b0 100644
--- a/samples/cbm/Makefile
+++ b/samples/cbm/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/samples/disasm/Makefile b/samples/disasm/Makefile
index f1d93f5da..6599915f6 100644
--- a/samples/disasm/Makefile
+++ b/samples/disasm/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Sample makefile using a preprocessor against info files
# and the --sync-lines option
diff --git a/samples/gamate/Makefile b/samples/gamate/Makefile
index cfb8505cc..35aef293d 100644
--- a/samples/gamate/Makefile
+++ b/samples/gamate/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/samples/geos/Makefile b/samples/geos/Makefile
index 578927760..ad4033f80 100644
--- a/samples/geos/Makefile
+++ b/samples/geos/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/samples/geos/grc/Makefile b/samples/geos/grc/Makefile
index ef30a6e03..360c7bc7d 100644
--- a/samples/geos/grc/Makefile
+++ b/samples/geos/grc/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/samples/kim1/Makefile b/samples/kim1/Makefile
index 08bb2a780..dbdbcec8d 100644
--- a/samples/kim1/Makefile
+++ b/samples/kim1/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/samples/lynx/Makefile b/samples/lynx/Makefile
index b4ef64af0..078ea129a 100644
--- a/samples/lynx/Makefile
+++ b/samples/lynx/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/samples/sim65/Makefile b/samples/sim65/Makefile
index 865594736..3a06321ee 100644
--- a/samples/sim65/Makefile
+++ b/samples/sim65/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/samples/supervision/Makefile b/samples/supervision/Makefile
index 097329384..9396be63d 100644
--- a/samples/supervision/Makefile
+++ b/samples/supervision/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/samples/sym1/Makefile b/samples/sym1/Makefile
index 281b5bcd0..8abcfb5aa 100644
--- a/samples/sym1/Makefile
+++ b/samples/sym1/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/samples/tutorial/Makefile b/samples/tutorial/Makefile
index eb8627c29..7b3286e27 100644
--- a/samples/tutorial/Makefile
+++ b/samples/tutorial/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/src/Makefile b/src/Makefile
index c5d91ce5a..085a50f9d 100644
--- a/src/Makefile
+++ b/src/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
ifneq ($(shell echo),)
CMD_EXE = 1
endif
diff --git a/src/ca65/condasm.c b/src/ca65/condasm.c
index 60e8ab0c1..c63e54e3a 100644
--- a/src/ca65/condasm.c
+++ b/src/ca65/condasm.c
@@ -414,6 +414,16 @@ void DoConditionals (void)
CalcOverallIfCond ();
break;
+ case TOK_IFP45GS02:
+ D = AllocIf (".IFP45GS02", 1);
+ NextTok ();
+ if (IfCond) {
+ SetIfCond (D, GetCPU() == CPU_45GS02);
+ }
+ ExpectSep ();
+ CalcOverallIfCond ();
+ break;
+
case TOK_IFP816:
D = AllocIf (".IFP816", 1);
NextTok ();
@@ -444,6 +454,16 @@ void DoConditionals (void)
CalcOverallIfCond ();
break;
+ case TOK_IFPM740:
+ D = AllocIf (".IFPM740", 1);
+ NextTok ();
+ if (IfCond) {
+ SetIfCond (D, GetCPU() == CPU_M740);
+ }
+ ExpectSep ();
+ CalcOverallIfCond ();
+ break;
+
case TOK_IFPSC02:
D = AllocIf (".IFPSC02", 1);
NextTok ();
@@ -497,9 +517,11 @@ int CheckConditionals (void)
case TOK_IFP02:
case TOK_IFP02X:
case TOK_IFP4510:
+ case TOK_IFP45GS02:
case TOK_IFP816:
case TOK_IFPC02:
case TOK_IFPDTV:
+ case TOK_IFPM740:
case TOK_IFPSC02:
case TOK_IFREF:
DoConditionals ();
diff --git a/src/ca65/ea65.c b/src/ca65/ea65.c
index 5bd2ba82b..898b344ca 100644
--- a/src/ca65/ea65.c
+++ b/src/ca65/ea65.c
@@ -101,6 +101,9 @@ void GetEA (EffAddr* A)
if (TokIsSep (CurTok.Tok)) {
A->AddrModeSet = AM65_IMPLICIT;
+ if (GetCPU () == CPU_45GS02) {
+ A->AddrModeSet |= AM65_Q;
+ }
} else if (CurTok.Tok == TOK_HASH) {
@@ -114,6 +117,11 @@ void GetEA (EffAddr* A)
NextTok ();
A->AddrModeSet = AM65_ACCU;
+ } else if (CurTok.Tok == TOK_Q) {
+
+ NextTok ();
+ A->AddrModeSet = AM65_Q;
+
} else if (CurTok.Tok == IndirectEnter) {
/* One of the indirect modes */
@@ -160,8 +168,19 @@ void GetEA (EffAddr* A)
}
} else {
/* (adr) */
- A->AddrModeSet = (CPU == CPU_4510) ? AM65_ABS_IND
- : AM65_ABS_IND | AM65_ABS_IND_LONG | AM65_DIR_IND;
+ switch (CPU) {
+ case CPU_4510:
+ A->AddrModeSet = AM65_ABS_IND;
+ break;
+
+ case CPU_45GS02:
+ A->AddrModeSet = AM65_ABS_IND | AM65_DIR_IND;
+ break;
+
+ default:
+ A->AddrModeSet = AM65_ABS_IND | AM65_ABS_IND_LONG | AM65_DIR_IND;
+ break;
+ }
}
}
@@ -175,8 +194,14 @@ void GetEA (EffAddr* A)
if (CurTok.Tok == TOK_COMMA) {
/* [dir],y */
NextTok ();
- Consume (TOK_Y, "'Y' expected");
- A->AddrModeSet = AM65_DIR_IND_LONG_Y;
+ if (GetCPU () == CPU_45GS02) {
+ Consume (TOK_Z, "'Z' expected");
+ A->AddrModeSet = AM65_32BIT_BASE_IND_Z;
+ }
+ else {
+ Consume (TOK_Y, "'Y' expected");
+ A->AddrModeSet = AM65_DIR_IND_LONG_Y;
+ }
} else {
/* [dir] */
A->AddrModeSet = AM65_DIR_IND_LONG | AM65_ABS_IND_LONG;
@@ -186,10 +211,11 @@ void GetEA (EffAddr* A)
/* Remaining stuff:
**
- ** adr
- ** adr,x
- ** adr,y
- ** adr,s
+ ** addr
+ ** addr, x
+ ** addr, y
+ ** addr, s
+ ** addr, relative addr
*/
A->Expr = Expression ();
@@ -214,7 +240,9 @@ void GetEA (EffAddr* A)
break;
default:
- Error ("Syntax error");
+ /* FIXME: syntax error if not zp, ind */
+ A->AddrModeSet = AM65_ZP_REL;
+ break;
}
diff --git a/src/ca65/instr.c b/src/ca65/instr.c
index c7a68006c..c19be11b2 100644
--- a/src/ca65/instr.c
+++ b/src/ca65/instr.c
@@ -85,6 +85,12 @@ static void PutBlockTransfer (const InsDesc* Ins);
static void PutBitBranch (const InsDesc* Ins);
/* Handle 65C02 branch on bit condition */
+static void PutBitBranch_m740 (const InsDesc* Ins);
+/* Handle m740 branch on bit condition */
+
+static void PutLDM_m740 (const InsDesc* Ins);
+/* Handle m740 LDM instruction */
+
static void PutREP (const InsDesc* Ins);
/* Emit a REP instruction, track register sizes */
@@ -132,6 +138,11 @@ static void PutJSR816 (const InsDesc* Ins);
** Allowing the long_jsr_jmp_rts feature to permit a long JSR.
*/
+static void PutJSR_m740 (const InsDesc* Ins);
+/* Handle the JSR instruction for the m740
+** Allowing the special page feature.
+*/
+
static void PutRTS (const InsDesc* Ins attribute ((unused)));
/* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if
** the enclosing scope is FAR, but only if the long_jsr_jmp_rts feature applies.
@@ -143,6 +154,12 @@ static void PutAll (const InsDesc* Ins);
static void Put4510 (const InsDesc* Ins);
/* Handle instructions of 4510 not matching any EATab */
+static void Put45GS02 (const InsDesc* Ins);
+/* Handle [adr],z instructions of 45GS02 */
+
+static void Put45GS02_Q (const InsDesc* Ins);
+/* Handle Q instructions of 45GS02 */
+
static void PutSweet16 (const InsDesc* Ins);
/* Handle a generic sweet16 instruction */
@@ -747,6 +764,170 @@ static const struct {
}
};
+
+/* Instruction table for the 45GS02 */
+static const struct {
+ unsigned Count;
+ InsDesc Ins[149];
+} InsTab45GS02 = {
+ /* CAUTION: table must be sorted for bsearch */
+ sizeof (InsTab45GS02.Ins) / sizeof (InsTab45GS02.Ins[0]),
+ {
+/* BEGIN SORTED.SH */
+ { "ADC", 0x4080A66C, 0x60, 0, Put45GS02 },
+ { "ADCQ", 0x0000140C, 0x60, 13, Put45GS02_Q },
+ { "AND", 0x4080A66C, 0x20, 0, Put45GS02 },
+ { "ANDQ", 0x0000140C, 0x20, 13, Put45GS02_Q },
+ { "ASL", 0x0000006e, 0x02, 1, PutAll },
+ { "ASLQ", 0x800000ee, 0x00, 14, Put45GS02_Q },
+ { "ASR", 0x00000026, 0x43, 0, Put4510 },
+ { "ASRQ", 0x80000026, 0x40, 15, Put45GS02_Q },
+ { "ASW", 0x00000008, 0xcb, 6, PutAll },
+ { "BBR0", 0x00000000, 0x0F, 0, PutBitBranch },
+ { "BBR1", 0x00000000, 0x1F, 0, PutBitBranch },
+ { "BBR2", 0x00000000, 0x2F, 0, PutBitBranch },
+ { "BBR3", 0x00000000, 0x3F, 0, PutBitBranch },
+ { "BBR4", 0x00000000, 0x4F, 0, PutBitBranch },
+ { "BBR5", 0x00000000, 0x5F, 0, PutBitBranch },
+ { "BBR6", 0x00000000, 0x6F, 0, PutBitBranch },
+ { "BBR7", 0x00000000, 0x7F, 0, PutBitBranch },
+ { "BBS0", 0x00000000, 0x8F, 0, PutBitBranch },
+ { "BBS1", 0x00000000, 0x9F, 0, PutBitBranch },
+ { "BBS2", 0x00000000, 0xAF, 0, PutBitBranch },
+ { "BBS3", 0x00000000, 0xBF, 0, PutBitBranch },
+ { "BBS4", 0x00000000, 0xCF, 0, PutBitBranch },
+ { "BBS5", 0x00000000, 0xDF, 0, PutBitBranch },
+ { "BBS6", 0x00000000, 0xEF, 0, PutBitBranch },
+ { "BBS7", 0x00000000, 0xFF, 0, PutBitBranch },
+ { "BCC", 0x00020000, 0x90, 0, PutPCRel8 },
+ { "BCS", 0x00020000, 0xb0, 0, PutPCRel8 },
+ { "BEQ", 0x00020000, 0xf0, 0, PutPCRel8 },
+ { "BIT", 0x00A0006C, 0x00, 2, PutAll },
+ { "BITQ", 0x0000000c, 0x20, 15, Put45GS02_Q },
+ { "BMI", 0x00020000, 0x30, 0, PutPCRel8 },
+ { "BNE", 0x00020000, 0xd0, 0, PutPCRel8 },
+ { "BPL", 0x00020000, 0x10, 0, PutPCRel8 },
+ { "BRA", 0x00020000, 0x80, 0, PutPCRel8 },
+ { "BRK", 0x00000001, 0x00, 0, PutAll },
+ { "BSR", 0x00040000, 0x63, 0, PutPCRel4510 },
+ { "BVC", 0x00020000, 0x50, 0, PutPCRel8 },
+ { "BVS", 0x00020000, 0x70, 0, PutPCRel8 },
+ { "CLC", 0x00000001, 0x18, 0, PutAll },
+ { "CLD", 0x00000001, 0xd8, 0, PutAll },
+ { "CLE", 0x00000001, 0x02, 0, PutAll },
+ { "CLI", 0x00000001, 0x58, 0, PutAll },
+ { "CLV", 0x00000001, 0xb8, 0, PutAll },
+ { "CMP", 0x4080A66C, 0xc0, 0, Put45GS02 },
+ { "CMPQ", 0x0000140C, 0xC0, 13, Put45GS02_Q },
+ { "CPX", 0x0080000C, 0xe0, 1, PutAll },
+ { "CPY", 0x0080000C, 0xc0, 1, PutAll },
+ { "CPZ", 0x0080000C, 0xd0, 1, Put4510 },
+ { "DEA", 0x00000001, 0x00, 3, PutAll }, /* == DEC */
+ { "DEC", 0x0000006F, 0x00, 3, PutAll },
+ { "DEQ", 0x800000ee, 0xc0, 14, Put45GS02_Q },
+ { "DEW", 0x00000004, 0xc3, 9, PutAll },
+ { "DEX", 0x00000001, 0xca, 0, PutAll },
+ { "DEY", 0x00000001, 0x88, 0, PutAll },
+ { "DEZ", 0x00000001, 0x3B, 0, PutAll },
+ { "EOM", 0x00000001, 0xea, 0, PutAll },
+ { "EOR", 0x4080A66C, 0x40, 0, Put45GS02 },
+ { "EORQ", 0x0000140C, 0x40, 13, Put45GS02_Q },
+ { "INA", 0x00000001, 0x00, 4, PutAll }, /* == INC */
+ { "INC", 0x0000006f, 0x00, 4, PutAll },
+ { "INQ", 0x800000ee, 0xe0, 14, Put45GS02_Q },
+ { "INW", 0x00000004, 0xe3, 9, PutAll },
+ { "INX", 0x00000001, 0xe8, 0, PutAll },
+ { "INY", 0x00000001, 0xc8, 0, PutAll },
+ { "INZ", 0x00000001, 0x1B, 0, PutAll },
+ { "JMP", 0x00010808, 0x4c, 6, PutAll },
+ { "JSR", 0x00010808, 0x20, 7, Put4510 },
+ { "LBCC", 0x00040000, 0x93, 0, PutPCRel4510 },
+ { "LBCS", 0x00040000, 0xb3, 0, PutPCRel4510 },
+ { "LBEQ", 0x00040000, 0xf3, 0, PutPCRel4510 },
+ { "LBMI", 0x00040000, 0x33, 0, PutPCRel4510 },
+ { "LBNE", 0x00040000, 0xd3, 0, PutPCRel4510 },
+ { "LBPL", 0x00040000, 0x13, 0, PutPCRel4510 },
+ { "LBRA", 0x00040000, 0x83, 0, PutPCRel4510 },
+ { "LBVC", 0x00040000, 0x53, 0, PutPCRel4510 },
+ { "LBVS", 0x00040000, 0x73, 0, PutPCRel4510 },
+ { "LDA", 0x4090A66C, 0xa0, 0, Put45GS02 },
+ { "LDQ", 0x4000140C, 0xa0, 13, Put45GS02_Q },
+ { "LDX", 0x0080030C, 0xa2, 1, PutAll },
+ { "LDY", 0x0080006C, 0xa0, 1, PutAll },
+ { "LDZ", 0x00800048, 0xa3, 1, Put4510 },
+ { "LSR", 0x0000006F, 0x42, 1, PutAll },
+ { "LSRQ", 0x800000ee, 0x40, 14, Put45GS02_Q },
+ { "MAP", 0x00000001, 0x5C, 0, PutAll },
+ { "NEG", 0x00000001, 0x42, 0, PutAll },
+ { "NOP", 0x00000001, 0xea, 0, PutAll }, /* == EOM */
+ { "ORA", 0x4080A66C, 0x00, 0, Put45GS02 },
+ { "ORQ", 0x0000140C, 0x00, 13, Put45GS02_Q },
+ { "PHA", 0x00000001, 0x48, 0, PutAll },
+ { "PHD", 0x08000008, 0xf4, 1, PutAll }, /* == PHW */
+ { "PHP", 0x00000001, 0x08, 0, PutAll },
+ { "PHW", 0x08000008, 0xf4, 1, PutAll },
+ { "PHX", 0x00000001, 0xda, 0, PutAll },
+ { "PHY", 0x00000001, 0x5a, 0, PutAll },
+ { "PHZ", 0x00000001, 0xdb, 0, PutAll },
+ { "PLA", 0x00000001, 0x68, 0, PutAll },
+ { "PLP", 0x00000001, 0x28, 0, PutAll },
+ { "PLX", 0x00000001, 0xfa, 0, PutAll },
+ { "PLY", 0x00000001, 0x7a, 0, PutAll },
+ { "PLZ", 0x00000001, 0xfb, 0, PutAll },
+ { "RMB0", 0x00000004, 0x07, 1, PutAll },
+ { "RMB1", 0x00000004, 0x17, 1, PutAll },
+ { "RMB2", 0x00000004, 0x27, 1, PutAll },
+ { "RMB3", 0x00000004, 0x37, 1, PutAll },
+ { "RMB4", 0x00000004, 0x47, 1, PutAll },
+ { "RMB5", 0x00000004, 0x57, 1, PutAll },
+ { "RMB6", 0x00000004, 0x67, 1, PutAll },
+ { "RMB7", 0x00000004, 0x77, 1, PutAll },
+ { "ROL", 0x0000006F, 0x22, 1, PutAll },
+ { "ROLQ", 0x800000ee, 0x20, 14, Put45GS02_Q },
+ { "ROR", 0x0000006F, 0x62, 1, PutAll },
+ { "RORQ", 0x800000ee, 0x60, 14, Put45GS02_Q },
+ { "ROW", 0x00000008, 0xeb, 6, PutAll },
+ { "RTI", 0x00000001, 0x40, 0, PutAll },
+ { "RTN", 0x00800000, 0x62, 1, PutAll },
+ { "RTS", 0x00000001, 0x60, 0, PutAll },
+ { "SBC", 0x4080A66C, 0xe0, 0, Put45GS02 },
+ { "SBCQ", 0x0000140C, 0xe0, 13, Put45GS02_Q },
+ { "SEC", 0x00000001, 0x38, 0, PutAll },
+ { "SED", 0x00000001, 0xf8, 0, PutAll },
+ { "SEE", 0x00000001, 0x03, 0, PutAll },
+ { "SEI", 0x00000001, 0x78, 0, PutAll },
+ { "SMB0", 0x00000004, 0x87, 1, PutAll },
+ { "SMB1", 0x00000004, 0x97, 1, PutAll },
+ { "SMB2", 0x00000004, 0xA7, 1, PutAll },
+ { "SMB3", 0x00000004, 0xB7, 1, PutAll },
+ { "SMB4", 0x00000004, 0xC7, 1, PutAll },
+ { "SMB5", 0x00000004, 0xD7, 1, PutAll },
+ { "SMB6", 0x00000004, 0xE7, 1, PutAll },
+ { "SMB7", 0x00000004, 0xF7, 1, PutAll },
+ { "STA", 0x4010A66C, 0x80, 0, Put45GS02 },
+ { "STQ", 0x0000140C, 0x80, 13, Put45GS02_Q },
+ { "STX", 0x0000030c, 0x82, 1, Put4510 },
+ { "STY", 0x0000006c, 0x80, 1, Put4510 },
+ { "STZ", 0x0000006c, 0x04, 5, PutAll },
+ { "TAB", 0x00000001, 0x5b, 0, PutAll },
+ { "TAX", 0x00000001, 0xaa, 0, PutAll },
+ { "TAY", 0x00000001, 0xa8, 0, PutAll },
+ { "TAZ", 0x00000001, 0x4b, 0, PutAll },
+ { "TBA", 0x00000001, 0x7b, 0, PutAll },
+ { "TRB", 0x0000000c, 0x10, 1, PutAll },
+ { "TSB", 0x0000000c, 0x00, 1, PutAll },
+ { "TSX", 0x00000001, 0xba, 0, PutAll },
+ { "TSY", 0x00000001, 0x0b, 0, PutAll },
+ { "TXA", 0x00000001, 0x8a, 0, PutAll },
+ { "TXS", 0x00000001, 0x9a, 0, PutAll },
+ { "TYA", 0x00000001, 0x98, 0, PutAll },
+ { "TYS", 0x00000001, 0x2b, 0, PutAll },
+ { "TZA", 0x00000001, 0x6b, 0, PutAll },
+/* END SORTED.SH */
+ }
+};
+
+
/* Instruction table for the 65816 */
static const struct {
unsigned Count;
@@ -1047,7 +1228,126 @@ static const struct {
}
};
+/* CAUTION: in the pdf $1a is dec a, and $3a is inc a - if that is really the case,
+ * the table below (and the handler) should be fixed and this notice removed */
+/* Instruction table for the m740 CPU */
+static const struct {
+ unsigned Count;
+ InsDesc Ins[106];
+} InsTabm740 = {
+ sizeof (InsTabm740.Ins) / sizeof (InsTabm740.Ins[0]),
+ {
+/* BEGIN SORTED.SH */
+ { "ADC", 0x0080A26C, 0x60, 0, PutAll },
+ { "AND", 0x0080A26C, 0x20, 0, PutAll },
+ { "ASL", 0x0000006e, 0x02, 1, PutAll },
+ { "BBC0", 0x10000002, 0x13, 10, PutBitBranch_m740 },
+ { "BBC1", 0x10000002, 0x33, 10, PutBitBranch_m740 },
+ { "BBC2", 0x10000002, 0x53, 10, PutBitBranch_m740 },
+ { "BBC3", 0x10000002, 0x73, 10, PutBitBranch_m740 },
+ { "BBC4", 0x10000002, 0x93, 10, PutBitBranch_m740 },
+ { "BBC5", 0x10000002, 0xb3, 10, PutBitBranch_m740 },
+ { "BBC6", 0x10000002, 0xd3, 10, PutBitBranch_m740 },
+ { "BBC7", 0x10000002, 0xf3, 10, PutBitBranch_m740 },
+ { "BBS0", 0x10000002, 0x03, 10, PutBitBranch_m740 },
+ { "BBS1", 0x10000002, 0x23, 10, PutBitBranch_m740 },
+ { "BBS2", 0x10000002, 0x43, 10, PutBitBranch_m740 },
+ { "BBS3", 0x10000002, 0x63, 10, PutBitBranch_m740 },
+ { "BBS4", 0x10000002, 0x83, 10, PutBitBranch_m740 },
+ { "BBS5", 0x10000002, 0xa3, 10, PutBitBranch_m740 },
+ { "BBS6", 0x10000002, 0xc3, 10, PutBitBranch_m740 },
+ { "BBS7", 0x10000002, 0xe3, 10, PutBitBranch_m740 },
+ { "BCC", 0x00020000, 0x90, 0, PutPCRel8 },
+ { "BCS", 0x00020000, 0xb0, 0, PutPCRel8 },
+ { "BEQ", 0x00020000, 0xf0, 0, PutPCRel8 },
+ { "BIT", 0x0000000C, 0x00, 2, PutAll },
+ { "BMI", 0x00020000, 0x30, 0, PutPCRel8 },
+ { "BNE", 0x00020000, 0xd0, 0, PutPCRel8 },
+ { "BPL", 0x00020000, 0x10, 0, PutPCRel8 },
+ { "BRA", 0x00020000, 0x80, 0, PutPCRel8 },
+ { "BRK", 0x00000001, 0x00, 0, PutAll },
+ { "BVC", 0x00020000, 0x50, 0, PutPCRel8 },
+ { "BVS", 0x00020000, 0x70, 0, PutPCRel8 },
+ { "CLB0", 0x00000006, 0x1b, 10, PutAll },
+ { "CLB1", 0x00000006, 0x3b, 10, PutAll },
+ { "CLB2", 0x00000006, 0x5b, 10, PutAll },
+ { "CLB3", 0x00000006, 0x7b, 10, PutAll },
+ { "CLB4", 0x00000006, 0x9b, 10, PutAll },
+ { "CLB5", 0x00000006, 0xbb, 10, PutAll },
+ { "CLB6", 0x00000006, 0xdb, 10, PutAll },
+ { "CLB7", 0x00000006, 0xfb, 10, PutAll },
+ { "CLC", 0x00000001, 0x18, 0, PutAll },
+ { "CLD", 0x00000001, 0xd8, 0, PutAll },
+ { "CLI", 0x00000001, 0x58, 0, PutAll },
+ { "CLT", 0x00000001, 0x12, 0, PutAll },
+ { "CLV", 0x00000001, 0xb8, 0, PutAll },
+ { "CMP", 0x0080A26C, 0xc0, 0, PutAll },
+ { "COM", 0x00000004, 0x44, 1, PutAll },
+ { "CPX", 0x0080000C, 0xe0, 1, PutAll },
+ { "CPY", 0x0080000C, 0xc0, 1, PutAll },
+ { "DEC", 0x0000006F, 0x00, 3, PutAll },
+ { "DEX", 0x00000001, 0xca, 0, PutAll },
+ { "DEY", 0x00000001, 0x88, 0, PutAll },
+ { "EOR", 0x0080A26C, 0x40, 0, PutAll },
+ { "FST", 0x00000001, 0xe2, 0, PutAll },
+ { "INC", 0x0000006f, 0x00, 4, PutAll },
+ { "INX", 0x00000001, 0xe8, 0, PutAll },
+ { "INY", 0x00000001, 0xc8, 0, PutAll },
+ { "JMP", 0x00000C08, 0x00, 12, PutAll },
+ { "JSR", 0x20000408, 0x00, 0, PutJSR_m740 },
+ { "LDA", 0x0080A26C, 0xa0, 0, PutAll },
+ { "LDM", 0x10000000, 0x3c, 0, PutLDM_m740 },
+ { "LDX", 0x0080030C, 0xa2, 1, PutAll },
+ { "LDY", 0x0080006C, 0xa0, 1, PutAll },
+ { "LSR", 0x0000006F, 0x42, 1, PutAll },
+ { "NOP", 0x00000001, 0xea, 0, PutAll },
+ { "ORA", 0x0080A26C, 0x00, 0, PutAll },
+ { "PHA", 0x00000001, 0x48, 0, PutAll },
+ { "PHP", 0x00000001, 0x08, 0, PutAll },
+ { "PLA", 0x00000001, 0x68, 0, PutAll },
+ { "PLP", 0x00000001, 0x28, 0, PutAll },
+ { "RMB0", 0x00000006, 0x1b, 10, PutAll },
+ { "RMB1", 0x00000006, 0x3b, 10, PutAll },
+ { "RMB2", 0x00000006, 0x5b, 10, PutAll },
+ { "RMB3", 0x00000006, 0x7b, 10, PutAll },
+ { "RMB4", 0x00000006, 0x9b, 10, PutAll },
+ { "RMB5", 0x00000006, 0xbb, 10, PutAll },
+ { "RMB6", 0x00000006, 0xdb, 10, PutAll },
+ { "RMB7", 0x00000006, 0xfb, 10, PutAll },
+ { "ROL", 0x0000006F, 0x22, 1, PutAll },
+ { "ROR", 0x0000006F, 0x62, 1, PutAll },
+ { "RRF", 0x00000004, 0x82, 6, PutAll },
+ { "RTI", 0x00000001, 0x40, 0, PutAll },
+ { "RTS", 0x00000001, 0x60, 0, PutAll },
+ { "SBC", 0x0080A26C, 0xe0, 0, PutAll },
+ { "SEB0", 0x00000006, 0x0b, 10, PutAll },
+ { "SEB1", 0x00000006, 0x2b, 10, PutAll },
+ { "SEB2", 0x00000006, 0x4b, 10, PutAll },
+ { "SEB3", 0x00000006, 0x6b, 10, PutAll },
+ { "SEB4", 0x00000006, 0x8b, 10, PutAll },
+ { "SEB5", 0x00000006, 0xab, 10, PutAll },
+ { "SEB6", 0x00000006, 0xcb, 10, PutAll },
+ { "SEB7", 0x00000006, 0xeb, 10, PutAll },
+ { "SEC", 0x00000001, 0x38, 0, PutAll },
+ { "SED", 0x00000001, 0xf8, 0, PutAll },
+ { "SEI", 0x00000001, 0x78, 0, PutAll },
+ { "SET", 0x00000001, 0x32, 0, PutAll },
+ { "SLW", 0x00000001, 0xC2, 0, PutAll },
+ { "STA", 0x0000A26C, 0x80, 0, PutAll },
+ { "STP", 0x00000001, 0x42, 0, PutAll },
+ { "STX", 0x0000010c, 0x82, 1, PutAll },
+ { "STY", 0x0000002c, 0x80, 1, PutAll },
+ { "TAX", 0x00000001, 0xaa, 0, PutAll },
+ { "TAY", 0x00000001, 0xa8, 0, PutAll },
+ { "TST", 0x00000004, 0x64, 1, PutAll },
+ { "TSX", 0x00000001, 0xba, 0, PutAll },
+ { "TXA", 0x00000001, 0x8a, 0, PutAll },
+ { "TXS", 0x00000001, 0x9a, 0, PutAll },
+ { "TYA", 0x00000001, 0x98, 0, PutAll }
+/* END SORTED.SH */
+ }
+};
/* An array with instruction tables */
static const InsTable* InsTabs[CPU_COUNT] = {
@@ -1060,87 +1360,113 @@ static const InsTable* InsTabs[CPU_COUNT] = {
(const InsTable*) &InsTab65816,
(const InsTable*) &InsTabSweet16,
(const InsTable*) &InsTabHuC6280,
- 0, /* Mitsubishi 740 */
+ (const InsTable*) &InsTabm740, /* Mitsubishi 740 */
(const InsTable*) &InsTab4510,
+ (const InsTable*) &InsTab45GS02,
};
const InsTable* InsTab = (const InsTable*) &InsTab6502;
/* Table to build the effective 65xx opcode from a base opcode and an
** addressing mode. (The value in the table is ORed with the base opcode)
+** NOTE: each table has one entry per addressing mode!
*/
-static unsigned char EATab[12][AM65I_COUNT] = {
- { /* Table 0 */
+static unsigned char EATab[16][AM65I_COUNT] = {
+ { /* Table 0 (sec, sed, seo, set, slw, sta, stp, tax, tay, tsx, txa, txs, tya) */
0x00, 0x00, 0x05, 0x0D, 0x0F, 0x15, 0x1D, 0x1F,
0x00, 0x19, 0x12, 0x00, 0x07, 0x11, 0x17, 0x01,
0x00, 0x00, 0x00, 0x03, 0x13, 0x09, 0x00, 0x09,
- 0x00, 0x00, 0x00, 0x00
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00
},
- { /* Table 1 */
+ { /* Table 1 (rol, ror, stx, sty, tst, cpx, cpy) */
0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x80, 0x00
+ 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00
},
- { /* Table 2 */
+ { /* Table 2 (bit) */
0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
- { /* Table 3 */
+ { /* Table 3 (dec, dea) */
0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
- { /* Table 4 */
+ { /* Table 4 (inc) */
0x1A, 0x1A, 0xE6, 0xEE, 0x00, 0xF6, 0xFE, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
- { /* Table 5 */
+ { /* Table 5 (stz) */
0x00, 0x00, 0x60, 0x98, 0x00, 0x70, 0x9E, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
- { /* Table 6 */
+ { /* Table 6 (jmp, rrf) */
0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x90, 0x00
+ 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00
},
- { /* Table 7 (Subroutine opcodes) */
+ { /* Table 7 (jsr) */
0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 8 */
0x00, 0x40, 0x01, 0x41, 0x00, 0x09, 0x49, 0x00,
0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
- { /* Table 9 */
+ { /* Table 9 (dew, inw) */
0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x30, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
- { /* Table 10 (NOPs) */
+ { /* Table 10 (NOPs, clbX, sebX) */
0xea, 0x00, 0x04, 0x0c, 0x00, 0x14, 0x1c, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
- 0x00, 0x00, 0x00, 0x00
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 11 (LAX) */
0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
- 0x00, 0x00, 0x80, 0x00
+ 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00
},
+ { /* Table 12 (m740: JMP) */
+ 0x00, 0x00, 0x00, 0x4c, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xb2, 0x6c, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ },
+ { /* Table 13 (Q) */
+ 0x00, 0x00, 0x05, 0x0D, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x12, 0x00, 0x12, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00
+ },
+ { /* Table 14 (45GS02: ASLQ) */
+ 0x0a, 0x0a, 0x06, 0x0e, 0x00, 0x16, 0x1e, 0x00,
+ 0x00, 0x00, 0x12, 0x00, 0x12, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a
+ },
+ { /* Table 15 (45GS02: ASRQ) */
+ 0x03, 0x03, 0x04, 0x0c, 0x00, 0x14, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03
+ }
};
/* Table to build the effective SWEET16 opcode from a base opcode and an
@@ -1156,6 +1482,7 @@ static unsigned char Sweet16EATab[2][AMSW16I_COUNT] = {
};
/* Table that encodes the additional bytes for each 65xx instruction */
+/* NOTE: one entry per addressing mode! */
unsigned char ExtBytes[AM65I_COUNT] = {
0, /* Implicit */
0, /* Accu */
@@ -1185,6 +1512,10 @@ unsigned char ExtBytes[AM65I_COUNT] = {
7, /* Block transfer (HuC6280) */
2, /* Absolute Indirect long */
2, /* Immidiate word */
+ 2, /* Direct, Relative short */
+ 1, /* Special Page */
+ 1, /* [Direct],z */
+ 0, /* Q */
};
/* Table that encodes the additional bytes for each SWEET16 instruction */
@@ -1361,6 +1692,20 @@ static void EmitCode (EffAddr* A)
}
+static void PutLDM_m740 (const InsDesc* Ins)
+{
+ EffAddr A;
+ /* Evaluate the addressing mode */
+ if (EvalEA (Ins, &A) == 0) {
+ /* An error occurred */
+ return;
+ }
+ Emit0 (Ins->BaseCode);
+ EmitByte (A.Expr);
+ Consume (TOK_HASH, "'#' expected");
+ EmitByte (Expression ());
+}
+
static long PutImmed8 (const InsDesc* Ins)
/* Parse and emit an immediate 8 bit instruction. Return the value of the
@@ -1481,6 +1826,42 @@ static void PutBitBranch (const InsDesc* Ins)
EmitSigned (GenBranchExpr (1), 1);
}
+static void PutBitBranch_m740 (const InsDesc* Ins)
+/* Handle m740 branch on bit condition */
+{
+ EffAddr A;
+
+ /* Evaluate the addressing mode used */
+ GetEA(&A);
+
+ /* From the possible addressing modes, remove the ones that are invalid
+ ** for this instruction or CPU.
+ */
+ A.AddrModeSet &= Ins->AddrMode;
+
+ /* Check if we have any adressing modes left */
+ if (A.AddrModeSet == 0) {
+ Error ("Illegal addressing mode");
+ return;
+ }
+ A.AddrMode = BitFind (A.AddrModeSet);
+
+ A.Opcode = Ins->BaseCode;
+
+ if (A.AddrMode == AM65I_ACCU) {
+ /* Accu */
+ Emit0 (A.Opcode);
+ ConsumeComma ();
+ EmitSigned (GenBranchExpr (2), 1);
+ } else if (A.AddrMode == AM65I_ZP_REL) {
+ /* FIXME: hacky, the comma was already consumed here */
+ A.Opcode += 0x04;
+ /* Zeropage */
+ Emit0 (A.Opcode);
+ EmitByte (A.Expr);
+ EmitSigned (GenBranchExpr (1), 1);
+ }
+}
static void PutREP (const InsDesc* Ins)
@@ -1584,7 +1965,6 @@ static void PutTMAn (const InsDesc* Ins)
** an immediate argument.
*/
{
- /* Emit the TMA opcode itself */
Emit0 (0x43);
/* Emit the argument, which is the opcode from the table */
@@ -1640,10 +2020,8 @@ static void PutJMP (const InsDesc* Ins)
*/
{
EffAddr A;
-
/* Evaluate the addressing mode used */
if (EvalEA (Ins, &A)) {
-
/* Check for indirect addressing */
if ((A.AddrModeBit & AM65_ABS_IND) && (CPU < CPU_65SC02) && (RelaxChecks == 0)) {
@@ -1701,6 +2079,57 @@ static void PutJSR816 (const InsDesc* Ins)
}
+static void PutJSR_m740 (const InsDesc* Ins)
+/* Handle a JSR instruction for m740 */
+{
+ EffAddr A;
+
+ /* Evaluate the addressing mode used */
+ GetEA (&A);
+
+ /* From the possible addressing modes, remove the ones that are invalid
+ ** for this instruction or CPU.
+ */
+ A.AddrModeSet &= Ins->AddrMode;
+
+ /* Check if we have any adressing modes left */
+ if (A.AddrModeSet == 0) {
+ Error ("Illegal addressing mode");
+ return;
+ }
+ A.AddrMode = BitFind (A.AddrModeSet);
+
+ /* Build the opcode */
+ A.Opcode = Ins->BaseCode;
+
+ switch (A.AddrMode) {
+ case AM65I_DIR_IND:
+ A.Opcode = 0x02;
+ Emit1 (A.Opcode, A.Expr);
+ break;
+ case AM65I_ABS:
+ /* If we have an expression and it's const, get it's value */
+ if (A.Expr) {
+ long Val = -1;
+ if (IsConstExpr (A.Expr, &Val)) {
+ if ((Val & 0xff00) == 0xff00) {
+ /* direct page */
+ A.Opcode = 0x22;
+ Emit0 (A.Opcode);
+ EmitByte(GenByteExpr(A.Expr));
+ return;
+ }
+ }
+ }
+ A.Opcode = 0x20;
+ Emit2 (A.Opcode, A.Expr);
+ break;
+ default:
+ Internal ("Invalid Opcode 0x%02x", A.Opcode);
+ }
+
+}
+
static void PutRTS (const InsDesc* Ins attribute ((unused)))
/* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if
@@ -1730,9 +2159,7 @@ static void PutAll (const InsDesc* Ins)
-static void Put4510 (const InsDesc* Ins)
-/* Handle all other instructions, with modifications for 4510 */
-{
+static void Emit4510 (EffAddr* A) {
/* The 4510 uses all 256 possible opcodes, so the last ones were crammed
** in where an opcode was still undefined. As a result, some of those
** don't follow any rules for encoding the addressmodes. So the EATab
@@ -1752,25 +2179,91 @@ static void Put4510 (const InsDesc* Ins)
** $d0 -> $c2 : CPZ #$00
** $fc -> $23 : JSR ($1234,X)
*/
+ switch (A->Opcode) {
+ case 0x47:
+ A->Opcode = 0x44;
+ break;
+ case 0x57:
+ A->Opcode = 0x54;
+ break;
+ case 0x93:
+ A->Opcode = 0x82;
+ break;
+ case 0x9C:
+ A->Opcode = 0x8B;
+ break;
+ case 0x9E:
+ A->Opcode = 0x9B;
+ break;
+ case 0xAF:
+ A->Opcode = 0xAB;
+ break;
+ case 0xBF:
+ A->Opcode = 0xBB;
+ break;
+ case 0xB3:
+ A->Opcode = 0xE2;
+ break;
+ case 0xD0:
+ A->Opcode = 0xC2;
+ break;
+ case 0xFC:
+ A->Opcode = 0x23;
+ break;
+ default: /* Keep opcode as it is */ break;
+ }
+
+ /* No error, output code */
+ EmitCode (A);
+}
+
+
+
+static void Put4510 (const InsDesc* Ins)
+/* Handle all other instructions, with modifications for 4510 */
+{
EffAddr A;
/* Evaluate the addressing mode used */
if (EvalEA (Ins, &A)) {
- switch (A.Opcode) {
- case 0x47: A.Opcode = 0x44; break;
- case 0x57: A.Opcode = 0x54; break;
- case 0x93: A.Opcode = 0x82; break;
- case 0x9C: A.Opcode = 0x8B; break;
- case 0x9E: A.Opcode = 0x9B; break;
- case 0xAF: A.Opcode = 0xAB; break;
- case 0xBF: A.Opcode = 0xBB; break;
- case 0xB3: A.Opcode = 0xE2; break;
- case 0xD0: A.Opcode = 0xC2; break;
- case 0xFC: A.Opcode = 0x23; break;
- default: /* Keep opcode as it is */ break;
- }
+ Emit4510 (&A);
+ }
+}
- /* No error, output code */
+
+
+static void Put45GS02 (const InsDesc* Ins)
+/* Handle all other instructions, with modifications for 45GS02 */
+{
+ EffAddr A;
+
+ if (EvalEA (Ins, &A)) {
+ if (A.AddrModeSet == AM65_32BIT_BASE_IND_Z) {
+ Emit0 (0xEA); /* NOP prefix */
+ }
+ Emit4510 (&A);
+ }
+}
+
+
+
+static void Put45GS02_Q (const InsDesc* Ins)
+{
+ EffAddr A;
+
+ if (EvalEA (Ins, &A)) {
+ Emit0 (0x42);
+ Emit0 (0x42);
+ if ((A.AddrModeBit == AM65_DIR_IND_LONG) ||
+ (A.AddrModeBit == AM65_32BIT_BASE_IND_Z)) {
+ Emit0 (0xEA); /* NOP prefix */
+ }
+ if (A.Opcode == 0xea) {
+ A.Opcode = 0x1a;
+ }
+ else if (A.Opcode == 0xca) {
+ A.Opcode = 0x3a;
+ }
EmitCode (&A);
}
}
diff --git a/src/ca65/instr.h b/src/ca65/instr.h
index fe18d2110..9c91fd0cf 100644
--- a/src/ca65/instr.h
+++ b/src/ca65/instr.h
@@ -58,34 +58,38 @@
** When assembling for the 6502 or 65C02, all addressing modes that are not
** available on these CPUs are removed before doing any checks.
*/
-#define AM65_IMPLICIT 0x00000003UL
-#define AM65_ACCU 0x00000002UL
-#define AM65_DIR 0x00000004UL
-#define AM65_ABS 0x00000008UL
-#define AM65_ABS_LONG 0x00000010UL
-#define AM65_DIR_X 0x00000020UL
-#define AM65_ABS_X 0x00000040UL
-#define AM65_ABS_LONG_X 0x00000080UL
-#define AM65_DIR_Y 0x00000100UL
-#define AM65_ABS_Y 0x00000200UL
-#define AM65_DIR_IND 0x00000400UL
-#define AM65_ABS_IND 0x00000800UL
-#define AM65_DIR_IND_LONG 0x00001000UL
-#define AM65_DIR_IND_Y 0x00002000UL
-#define AM65_DIR_IND_LONG_Y 0x00004000UL
-#define AM65_DIR_X_IND 0x00008000UL
-#define AM65_ABS_X_IND 0x00010000UL
-#define AM65_REL 0x00020000UL
-#define AM65_REL_LONG 0x00040000UL
-#define AM65_STACK_REL 0x00080000UL
-#define AM65_STACK_REL_IND_Y 0x00100000UL
+#define AM65_IMPLICIT 0x00000003UL /* IMP */
+#define AM65_ACCU 0x00000002UL /* A */
+#define AM65_DIR 0x00000004UL /* ZP */
+#define AM65_ABS 0x00000008UL /* ABS */
+#define AM65_ABS_LONG 0x00000010UL /* adr */
+#define AM65_DIR_X 0x00000020UL /* ZP,X */
+#define AM65_ABS_X 0x00000040UL /* ABS, X */
+#define AM65_ABS_LONG_X 0x00000080UL /* adr,x */
+#define AM65_DIR_Y 0x00000100UL /* ZP, Y */
+#define AM65_ABS_Y 0x00000200UL /* ABS, Y */
+#define AM65_DIR_IND 0x00000400UL /* (ZP) or (ZP),z (4510 / 45GS02) */
+#define AM65_ABS_IND 0x00000800UL /* (ABS) */
+#define AM65_DIR_IND_LONG 0x00001000UL /* [ABS] (65816) */
+#define AM65_DIR_IND_Y 0x00002000UL /* (ZP),y */
+#define AM65_DIR_IND_LONG_Y 0x00004000UL /* [adr],y (not 45GS02) */
+#define AM65_DIR_X_IND 0x00008000UL /* (ZP,x) */
+#define AM65_ABS_X_IND 0x00010000UL /* (ABS,x) */
+#define AM65_REL 0x00020000UL /* REL */
+#define AM65_REL_LONG 0x00040000UL /* LONGREL */
+#define AM65_STACK_REL 0x00080000UL /* adr,s */
+#define AM65_STACK_REL_IND_Y 0x00100000UL /* (rel,s),y */
#define AM65_IMM_ACCU 0x00200000UL
#define AM65_IMM_INDEX 0x00400000UL
-#define AM65_IMM_IMPLICIT 0x00800000UL
+#define AM65_IMM_IMPLICIT 0x00800000UL /* IMM */
#define AM65_BLOCKMOVE 0x01000000UL
#define AM65_BLOCKXFER 0x02000000UL
-#define AM65_ABS_IND_LONG 0x04000000UL
+#define AM65_ABS_IND_LONG 0x04000000UL /* (adr) [dir] */
#define AM65_IMM_IMPLICIT_WORD 0x08000000UL /* PHW #$1234 (4510 only) */
+#define AM65_ZP_REL 0x10000000UL /* ZP, REL (m740) */
+#define AM65_SPECIAL_PAGE 0x20000000UL /* $FFxx (m740) */
+#define AM65_32BIT_BASE_IND_Z 0x40000000UL /* LDA [$nn],Z (45GS02 only) */
+#define AM65_Q 0x80000000UL /* Q (45GS02 only) */
/* Bitmask for all ZP operations that have correspondent ABS ops */
#define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
@@ -106,11 +110,39 @@
#define AM65_ALL_IMM (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT | AM65_IMM_IMPLICIT_WORD)
/* Bit numbers and count */
-#define AM65I_IMM_ACCU 21
-#define AM65I_IMM_INDEX 22
-#define AM65I_IMM_IMPLICIT 23
-#define AM65I_IMM_IMPLICIT_WORD 27
-#define AM65I_COUNT 28
+#define AM65I_IMPLICIT 0
+#define AM65I_ACCU 1
+#define AM65I_DIR 2
+#define AM65I_ABS 3
+#define AM65I_ABS_LONG 4
+#define AM65I_DIR_X 5
+#define AM65I_ABS_X 6
+#define AM65I_ABS_LONG_X 7
+#define AM65I_DIR_Y 8
+#define AM65I_ABS_Y 9
+#define AM65I_DIR_IND 10
+#define AM65I_ABS_IND 11
+#define AM65I_DIR_IND_LONG 12
+#define AM65I_DIR_IND_Y 13
+#define AM65I_DIR_IND_LONG_Y 14
+#define AM65I_DIR_X_IND 15
+#define AM65I_ABS_X_IND 16
+#define AM65I_REL 17
+#define AM65I_REL_LONG 18
+#define AM65I_STACK_REL 19
+#define AM65I_STACK_REL_IND_Y 20
+#define AM65I_IMM_ACCU 21
+#define AM65I_IMM_INDEX 22
+#define AM65I_IMM_IMPLICIT 23
+#define AM65I_BLOCKMOVE 24
+#define AM65I_BLOCKXFER 25
+#define AM65I_ABS_IND_LONG 26
+#define AM65I_IMM_IMPLICIT_WORD 27
+#define AM65I_ZP_REL 28
+#define AM65I_SPECIAL_PAGE 29
+#define AM65I_32BIT_BASE_IND_Z 30
+#define AM65I_Q 31
+#define AM65I_COUNT 32
diff --git a/src/ca65/pseudo.c b/src/ca65/pseudo.c
index 37dcd78da..7e52ecb5e 100644
--- a/src/ca65/pseudo.c
+++ b/src/ca65/pseudo.c
@@ -1563,7 +1563,7 @@ static void DoP02 (void)
static void DoP02X (void)
-/* Switch to 6502 CPU */
+/* Switch to 6502X CPU */
{
SetCPU (CPU_6502X);
}
@@ -1594,6 +1594,14 @@ static void DoP4510 (void)
+static void DoP45GS02 (void)
+/* Switch to 45GS02 CPU */
+{
+ SetCPU (CPU_45GS02);
+}
+
+
+
static void DoPDTV (void)
/* Switch to C64DTV CPU */
{
@@ -1602,6 +1610,14 @@ static void DoPDTV (void)
+static void DoPM740 (void)
+/* Switch to M740 CPU */
+{
+ SetCPU (CPU_M740);
+}
+
+
+
static void DoPageLength (void)
/* Set the page length for the listing */
{
@@ -2143,9 +2159,11 @@ static CtrlDesc CtrlCmdTab [] = {
{ ccKeepToken, DoConditionals }, /* .IFP02 */
{ ccKeepToken, DoConditionals }, /* .IFP02X */
{ ccKeepToken, DoConditionals }, /* .IFP4510 */
+ { ccKeepToken, DoConditionals }, /* .IFP45GS02 */
{ ccKeepToken, DoConditionals }, /* .IFP816 */
{ ccKeepToken, DoConditionals }, /* .IFPC02 */
{ ccKeepToken, DoConditionals }, /* .IFPDTV */
+ { ccKeepToken, DoConditionals }, /* .IFPM740 */
{ ccKeepToken, DoConditionals }, /* .IFPSC02 */
{ ccKeepToken, DoConditionals }, /* .IFREF */
{ ccNone, DoImport }, /* .IMPORT */
@@ -2177,11 +2195,13 @@ static CtrlDesc CtrlCmdTab [] = {
{ ccNone, DoP02 }, /* .P02 */
{ ccNone, DoP02X }, /* .P02X */
{ ccNone, DoP4510 }, /* .P4510 */
+ { ccNone, DoP45GS02 }, /* .P45GS02 */
{ ccNone, DoP816 }, /* .P816 */
{ ccNone, DoPageLength }, /* .PAGELEN, .PAGELENGTH */
{ ccNone, DoUnexpected }, /* .PARAMCOUNT */
{ ccNone, DoPC02 }, /* .PSC02 */
{ ccNone, DoPDTV }, /* .PDTV */
+ { ccNone, DoPM740 }, /* .PM740 */
{ ccNone, DoPopCharmap }, /* .POPCHARMAP */
{ ccNone, DoPopCPU }, /* .POPCPU */
{ ccNone, DoPopSeg }, /* .POPSEG */
diff --git a/src/ca65/scanner.c b/src/ca65/scanner.c
index 157702897..dd0209856 100644
--- a/src/ca65/scanner.c
+++ b/src/ca65/scanner.c
@@ -223,9 +223,11 @@ struct DotKeyword {
{ ".IFP02", TOK_IFP02 },
{ ".IFP02X", TOK_IFP02X },
{ ".IFP4510", TOK_IFP4510 },
+ { ".IFP45GS02", TOK_IFP45GS02 },
{ ".IFP816", TOK_IFP816 },
{ ".IFPC02", TOK_IFPC02 },
{ ".IFPDTV", TOK_IFPDTV },
+ { ".IFPM740", TOK_IFPM740 },
{ ".IFPSC02", TOK_IFPSC02 },
{ ".IFREF", TOK_IFREF },
{ ".IMPORT", TOK_IMPORT },
@@ -262,12 +264,14 @@ struct DotKeyword {
{ ".P02", TOK_P02 },
{ ".P02X", TOK_P02X },
{ ".P4510", TOK_P4510 },
+ { ".P45GS02", TOK_P45GS02 },
{ ".P816", TOK_P816 },
{ ".PAGELEN", TOK_PAGELENGTH },
{ ".PAGELENGTH", TOK_PAGELENGTH },
{ ".PARAMCOUNT", TOK_PARAMCOUNT },
{ ".PC02", TOK_PC02 },
{ ".PDTV", TOK_PDTV },
+ { ".PM740", TOK_PM740 },
{ ".POPCHARMAP", TOK_POPCHARMAP },
{ ".POPCPU", TOK_POPCPU },
{ ".POPSEG", TOK_POPSEG },
@@ -1277,12 +1281,19 @@ Again:
break;
case 'S':
- if ((CPU == CPU_4510) || (CPU == CPU_65816)) {
+ if ((CPU == CPU_4510) || (CPU == CPU_45GS02) || (CPU == CPU_65816)) {
CurTok.Tok = TOK_S;
return;
}
break;
+ case 'Q':
+ if (CPU == CPU_45GS02) {
+ CurTok.Tok = TOK_Q;
+ return;
+ }
+ break;
+
case 'X':
CurTok.Tok = TOK_X;
return;
@@ -1297,7 +1308,7 @@ Again:
CurTok.Tok = TOK_OVERRIDE_ZP;
return;
} else {
- if (CPU == CPU_4510) {
+ if ((CPU == CPU_4510) || (CPU == CPU_45GS02)) {
CurTok.Tok = TOK_Z;
return;
}
@@ -1309,7 +1320,7 @@ Again:
}
break;
case 2:
- if ((CPU == CPU_4510) &&
+ if ((CPU == CPU_4510 || CPU == CPU_45GS02) &&
(toupper (SB_AtUnchecked (&CurTok.SVal, 0)) == 'S') &&
(toupper (SB_AtUnchecked (&CurTok.SVal, 1)) == 'P')) {
diff --git a/src/ca65/symentry.c b/src/ca65/symentry.c
index 1048bfbc2..c57fcff2a 100644
--- a/src/ca65/symentry.c
+++ b/src/ca65/symentry.c
@@ -211,6 +211,8 @@ static void SymReplaceExprRefs (SymEntry* S)
void SymDef (SymEntry* S, ExprNode* Expr, unsigned char AddrSize, unsigned Flags)
/* Define a new symbol */
{
+ int Redef = 0; /* Flag for symbol redefinition */
+
if (S->Flags & SF_IMPORT) {
/* Defined symbol is marked as imported external symbol */
Error ("Symbol '%m%p' is already an import", GetSymName (S));
@@ -238,6 +240,7 @@ void SymDef (SymEntry* S, ExprNode* Expr, unsigned char AddrSize, unsigned Flags
*/
FreeExpr (S->Expr);
S->Expr = 0;
+ Redef = 1;
}
}
@@ -291,8 +294,10 @@ void SymDef (SymEntry* S, ExprNode* Expr, unsigned char AddrSize, unsigned Flags
}
}
- /* If this is not a local symbol, remember it as the last global one */
- if ((S->Flags & SF_LOCAL) == 0) {
+ /* If this is not a local symbol and not a redefinition for a variable
+ ** symbol, remember it as the last global one.
+ */
+ if ((S->Flags & SF_LOCAL) == 0 && !Redef) {
SymLast = S;
}
}
diff --git a/src/ca65/token.h b/src/ca65/token.h
index aeae7166a..9ca7ea657 100644
--- a/src/ca65/token.h
+++ b/src/ca65/token.h
@@ -68,6 +68,7 @@ typedef enum token_t {
TOK_Y, /* Y register */
TOK_Z, /* Z register */
TOK_S, /* S register */
+ TOK_Q, /* Q pseudo register */
TOK_REG, /* Sweet16 R.. register (in sweet16 mode) */
TOK_ASSIGN, /* := */
@@ -195,9 +196,11 @@ typedef enum token_t {
TOK_IFP02,
TOK_IFP02X,
TOK_IFP4510,
+ TOK_IFP45GS02,
TOK_IFP816,
TOK_IFPC02,
TOK_IFPDTV,
+ TOK_IFPM740,
TOK_IFPSC02,
TOK_IFREF,
TOK_IMPORT,
@@ -229,11 +232,13 @@ typedef enum token_t {
TOK_P02,
TOK_P02X,
TOK_P4510,
+ TOK_P45GS02,
TOK_P816,
TOK_PAGELENGTH,
TOK_PARAMCOUNT,
TOK_PC02,
TOK_PDTV,
+ TOK_PM740,
TOK_POPCHARMAP,
TOK_POPCPU,
TOK_POPSEG,
diff --git a/src/cc65/codeopt.c b/src/cc65/codeopt.c
index d42b0b1a5..e3869d786 100644
--- a/src/cc65/codeopt.c
+++ b/src/cc65/codeopt.c
@@ -119,7 +119,8 @@ static OptFunc DOptBNegAX1 = { OptBNegAX1, "OptBNegAX1", 100, 0,
static OptFunc DOptBNegAX2 = { OptBNegAX2, "OptBNegAX2", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptBNegAX3 = { OptBNegAX3, "OptBNegAX3", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptBNegAX4 = { OptBNegAX4, "OptBNegAX4", 100, 0, 0, 0, 0, 0 };
-static OptFunc DOptBinOps = { OptBinOps, "OptBinOps", 0, 0, 0, 0, 0, 0 };
+static OptFunc DOptBinOps1 = { OptBinOps1, "OptBinOps1", 0, 0, 0, 0, 0, 0 };
+static OptFunc DOptBinOps2 = { OptBinOps2, "OptBinOps2", 0, 0, 0, 0, 0, 0 };
static OptFunc DOptBoolCmp = { OptBoolCmp, "OptBoolCmp", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptBoolTrans = { OptBoolTrans, "OptBoolTrans", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptBoolUnary1 = { OptBoolUnary1, "OptBoolUnary1", 40, 0, 0, 0, 0, 0 };
@@ -154,6 +155,8 @@ static OptFunc DOptJumpTarget3 = { OptJumpTarget3, "OptJumpTarget3", 100, 0,
static OptFunc DOptLoad1 = { OptLoad1, "OptLoad1", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptLoad2 = { OptLoad2, "OptLoad2", 200, 0, 0, 0, 0, 0 };
static OptFunc DOptLoad3 = { OptLoad3, "OptLoad3", 0, 0, 0, 0, 0, 0 };
+static OptFunc DOptLoadStore1 = { OptLoadStore1, "OptLoadStore1", 0, 0, 0, 0, 0, 0 };
+static OptFunc DOptLoadStore2 = { OptLoadStore2, "OptLoadStore2", 0, 0, 0, 0, 0, 0 };
static OptFunc DOptLoadStoreLoad= { OptLoadStoreLoad,"OptLoadStoreLoad", 0, 0, 0, 0, 0, 0 };
static OptFunc DOptLongAssign = { OptLongAssign, "OptLongAssign", 100, 0, 0, 0, 0, 0 };
static OptFunc DOptLongCopy = { OptLongCopy, "OptLongCopy", 100, 0, 0, 0, 0, 0 };
@@ -238,7 +241,8 @@ static OptFunc* OptFuncs[] = {
&DOptBNegAX2,
&DOptBNegAX3,
&DOptBNegAX4,
- &DOptBinOps,
+ &DOptBinOps1,
+ &DOptBinOps2,
&DOptBoolCmp,
&DOptBoolTrans,
&DOptBoolUnary1,
@@ -273,6 +277,8 @@ static OptFunc* OptFuncs[] = {
&DOptLoad1,
&DOptLoad2,
&DOptLoad3,
+ &DOptLoadStore1,
+ &DOptLoadStore2,
&DOptLoadStoreLoad,
&DOptLongAssign,
&DOptLongCopy,
@@ -649,6 +655,7 @@ static unsigned RunOptGroup1 (CodeSeg* S)
Changes += RunOptFunc (S, &DOptSub1, 1);
Changes += RunOptFunc (S, &DOptSub3, 1);
Changes += RunOptFunc (S, &DOptLongAssign, 1);
+ Changes += RunOptFunc (S, &DOptLoadStore2, 1);
Changes += RunOptFunc (S, &DOptStore4, 1);
Changes += RunOptFunc (S, &DOptStore5, 1);
Changes += RunOptFunc (S, &DOptShift1, 1);
@@ -741,9 +748,10 @@ static unsigned RunOptGroup3 (CodeSeg* S)
C += RunOptFunc (S, &DOptJumpTarget3, 1); /* After OptCondBranches2 */
C += RunOptFunc (S, &DOptUnusedLoads, 1);
C += RunOptFunc (S, &DOptUnusedStores, 1);
- C += RunOptFunc (S, &DOptDupLoads, 1);
C += RunOptFunc (S, &DOptStoreLoad, 1);
C += RunOptFunc (S, &DOptLoadStoreLoad, 1);
+ C += RunOptFunc (S, &DOptDupLoads, 1);
+ C += RunOptFunc (S, &DOptLoadStore1, 1);
C += RunOptFunc (S, &DOptTransfers1, 1);
C += RunOptFunc (S, &DOptTransfers3, 1);
C += RunOptFunc (S, &DOptTransfers4, 1);
@@ -755,7 +763,8 @@ static unsigned RunOptGroup3 (CodeSeg* S)
C += RunOptFunc (S, &DOptPrecalc, 1);
C += RunOptFunc (S, &DOptShiftBack, 1);
C += RunOptFunc (S, &DOptSignExtended, 1);
- C += RunOptFunc (S, &DOptBinOps, 1);
+ C += RunOptFunc (S, &DOptBinOps1, 1);
+ C += RunOptFunc (S, &DOptBinOps2, 1);
Changes += C;
diff --git a/src/cc65/coptind.c b/src/cc65/coptind.c
index 52c47481e..99fc101a9 100644
--- a/src/cc65/coptind.c
+++ b/src/cc65/coptind.c
@@ -590,6 +590,49 @@ unsigned OptStoreLoad (CodeSeg* S)
+unsigned OptLoadStore1 (CodeSeg* S)
+/* Remove an 8 bit load followed by a store into the same location. */
+{
+ unsigned Changes = 0;
+
+ /* Walk over the entries */
+ unsigned I = 0;
+ while (I < CS_GetEntryCount (S)) {
+
+ CodeEntry* N;
+
+ /* Get next entry */
+ CodeEntry* E = CS_GetEntry (S, I);
+
+ /* Check if it is a load instruction followed by a store into the
+ ** same address.
+ */
+ if ((E->Info & OF_LOAD) != 0 &&
+ (N = CS_GetNextEntry (S, I)) != 0 &&
+ !CE_HasLabel (N) &&
+ E->AM == N->AM &&
+ ((E->OPC == OP65_LDA && N->OPC == OP65_STA) ||
+ (E->OPC == OP65_LDX && N->OPC == OP65_STX) ||
+ (E->OPC == OP65_LDY && N->OPC == OP65_STY)) &&
+ strcmp (E->Arg, N->Arg) == 0) {
+
+ /* Memory cell has already the correct value, remove the store */
+ CS_DelEntry (S, I+1);
+
+ /* Remember, we had changes */
+ ++Changes;
+ }
+
+ /* Next entry */
+ ++I;
+ }
+
+ /* Return the number of changes made */
+ return Changes;
+}
+
+
+
unsigned OptLoadStoreLoad (CodeSeg* S)
/* Search for the sequence
**
@@ -626,7 +669,7 @@ unsigned OptLoadStoreLoad (CodeSeg* S)
strcmp (L[0]->Arg, L[2]->Arg) == 0) {
/* Remove the second load */
- CS_DelEntries (S, I+2, 1);
+ CS_DelEntry (S, I+2);
/* Remember, we had changes */
++Changes;
diff --git a/src/cc65/coptind.h b/src/cc65/coptind.h
index 3493543a4..e54ba37d2 100644
--- a/src/cc65/coptind.h
+++ b/src/cc65/coptind.h
@@ -66,6 +66,9 @@ unsigned OptDupLoads (CodeSeg* S);
unsigned OptStoreLoad (CodeSeg* S);
/* Remove a store followed by a load from the same location. */
+unsigned OptLoadStore1 (CodeSeg* S);
+/* Remove an 8 bit load followed by a store into the same location. */
+
unsigned OptLoadStoreLoad (CodeSeg* S);
/* Remove a load, store followed by a reload of the same location. */
diff --git a/src/cc65/coptmisc.c b/src/cc65/coptmisc.c
index 6560ccc26..a2cda7495 100644
--- a/src/cc65/coptmisc.c
+++ b/src/cc65/coptmisc.c
@@ -582,11 +582,57 @@ unsigned OptGotoSPAdj (CodeSeg* S)
/*****************************************************************************/
-/* Optimize stack load ops */
+/* Optimize stack load/store ops */
/*****************************************************************************/
+unsigned OptLoadStore2 (CodeSeg* S)
+/* Remove 16 bit stack loads followed by a store into the same location. */
+{
+ unsigned Changes = 0;
+
+ /* Walk over the entries */
+ unsigned I = 0;
+ while (I < CS_GetEntryCount (S)) {
+
+ CodeEntry* N;
+
+ /* Get next entry */
+ CodeEntry* E = CS_GetEntry (S, I);
+
+ /* Check if this is a 16 bit load followed by a store into the same
+ ** address.
+ */
+ if (CE_IsCallTo (E, "ldaxysp") && /* Stack load ... */
+ RegValIsKnown (E->RI->In.RegY) && /* ... with known offs */
+ (N = CS_GetNextEntry (S, I)) != 0 && /* Next insn ... */
+ !CE_HasLabel (N) && /* ... without label ... */
+ N->OPC == OP65_LDY && /* ... is LDY */
+ CE_IsKnownImm (N, E->RI->In.RegY-1) && /* Same offset as load */
+ (N = CS_GetNextEntry (S, I+1)) != 0 && /* Next insn ... */
+ !CE_HasLabel (N) && /* ... without label ... */
+ CE_IsCallTo (N, "staxysp")) { /* ... is store */
+
+ /* Found - remove it. Leave the load in place. If it's unused, it
+ ** will get removed by later steps.
+ */
+ CS_DelEntries (S, I+1, 2);
+
+ /* Remember, we had changes */
+ ++Changes;
+ }
+
+ /* Next entry */
+ ++I;
+ }
+
+ /* Return the number of changes made */
+ return Changes;
+}
+
+
+
unsigned OptLoad1 (CodeSeg* S)
/* Search for a call to ldaxysp where X is not used later and replace it by
** a load of just the A register.
@@ -736,7 +782,7 @@ unsigned OptLoad2 (CodeSeg* S)
-unsigned OptBinOps (CodeSeg* S)
+unsigned OptBinOps1 (CodeSeg* S)
/* Search for an AND/EOR/ORA where the value of A or the operand is known and
** replace it by something simpler.
*/
@@ -902,3 +948,59 @@ unsigned OptBinOps (CodeSeg* S)
/* Return the number of changes made */
return Changes;
}
+
+
+
+unsigned OptBinOps2 (CodeSeg* S)
+/* Search for an AND/EOR/ORA for identical memory locations and replace it
+** by something simpler.
+*/
+{
+ unsigned Changes = 0;
+
+ /* Walk over the entries */
+ unsigned I = 0;
+ while (I < CS_GetEntryCount (S)) {
+
+ CodeEntry* N;
+
+ /* Get next entry */
+ CodeEntry* E = CS_GetEntry (S, I);
+
+ /* Check if this is an 8 bit load followed by a bit operation with the
+ ** same memory cell.
+ */
+ if (E->OPC == OP65_LDA &&
+ (N = CS_GetNextEntry (S, I)) != 0 && /* Next insn ... */
+ !CE_HasLabel (N) && /* ... without label ... */
+ (N->OPC == OP65_AND || /* ... is AND/EOR/ORA ... */
+ N->OPC == OP65_EOR ||
+ N->OPC == OP65_ORA) &&
+ E->AM == N->AM && /* ... with same addr mode ... */
+ strcmp (E->Arg, N->Arg) == 0) { /* ... and same argument */
+
+ /* For an EOR, the result is zero. For the other instructions, the
+ ** result doesn't change so they can be removed.
+ */
+ if (N->OPC == OP65_EOR) {
+ /* Simply insert a load of the now known value. The flags will
+ ** be correct because of the load and the preceeding
+ ** instructions will be removed by later steps.
+ */
+ CodeEntry* X = NewCodeEntry (OP65_LDA, AM65_IMM, "$00", 0, N->LI);
+ CS_InsertEntry (S, X, I+2);
+ } else {
+ CS_DelEntry (S, I+1);
+ }
+
+ /* Remember, we had changes */
+ ++Changes;
+ }
+
+ /* Next entry */
+ ++I;
+ }
+
+ /* Return the number of changes made */
+ return Changes;
+}
diff --git a/src/cc65/coptmisc.h b/src/cc65/coptmisc.h
index 418b61e94..aceaa55d3 100644
--- a/src/cc65/coptmisc.h
+++ b/src/cc65/coptmisc.h
@@ -99,6 +99,9 @@ unsigned OptStackPtrOps (CodeSeg* S);
unsigned OptGotoSPAdj (CodeSeg* S);
/* Optimize SP adjustment for forward 'goto' */
+unsigned OptLoadStore2 (CodeSeg* S);
+/* Remove 16 bit stack loads followed by a store into the same location. */
+
unsigned OptLoad1 (CodeSeg* S);
/* Search for a call to ldaxysp where X is not used later and replace it by
** a load of just the A register.
@@ -107,11 +110,16 @@ unsigned OptLoad1 (CodeSeg* S);
unsigned OptLoad2 (CodeSeg* S);
/* Replace calls to ldaxysp by inline code */
-unsigned OptBinOps (CodeSeg* S);
+unsigned OptBinOps1 (CodeSeg* S);
/* Search for an AND/EOR/ORA where the value of A or the operand is known and
** replace it by something simpler.
*/
+unsigned OptBinOps2 (CodeSeg* S);
+/* Search for an AND/EOR/ORA for identical memory locations and replace it
+** by something simpler.
+*/
+
/* End of coptmisc.h */
diff --git a/src/cl65/main.c b/src/cl65/main.c
index 528e64e56..6f2fe03df 100644
--- a/src/cl65/main.c
+++ b/src/cl65/main.c
@@ -1715,10 +1715,14 @@ int main (int argc, char* argv [])
/* Link the given files if requested and if we have any */
if (DoLink && LD65.FileCount > 0) {
+ /*
+ ** Link() may not return if there's an error, so we install
+ ** RemoveTempFiles() as an atexit() handler.
+ */
+ atexit (RemoveTempFiles);
Link ();
}
- RemoveTempFiles ();
if (OutputDirectory != NULL) {
xfree(OutputDirectory);
}
diff --git a/src/common/cpu.c b/src/common/cpu.c
index b55a5ab00..2c29eb1c4 100644
--- a/src/common/cpu.c
+++ b/src/common/cpu.c
@@ -63,6 +63,7 @@ const char* CPUNames[CPU_COUNT] = {
"huc6280",
"m740",
"4510",
+ "45GS02"
};
/* Tables with CPU instruction sets */
@@ -78,6 +79,7 @@ const unsigned CPUIsets[CPU_COUNT] = {
CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02 | CPU_ISET_HUC6280,
CPU_ISET_6502 | CPU_ISET_M740,
CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02 | CPU_ISET_4510,
+ CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02 | CPU_ISET_4510 | CPU_ISET_45GS02,
};
diff --git a/src/common/cpu.h b/src/common/cpu.h
index 2e75feaaf..6d8b72469 100644
--- a/src/common/cpu.h
+++ b/src/common/cpu.h
@@ -58,6 +58,7 @@ typedef enum {
CPU_HUC6280, /* Used in PC engine */
CPU_M740, /* Mitsubishi 740 series MCUs */
CPU_4510, /* CPU of C65 */
+ CPU_45GS02, /* CPU of MEGA65 */
CPU_COUNT /* Number of different CPUs */
} cpu_t;
@@ -74,6 +75,7 @@ enum {
CPU_ISET_HUC6280 = 1 << CPU_HUC6280,
CPU_ISET_M740 = 1 << CPU_M740,
CPU_ISET_4510 = 1 << CPU_4510,
+ CPU_ISET_45GS02 = 1 << CPU_45GS02
};
/* CPU used */
diff --git a/src/da65.vcxproj b/src/da65.vcxproj
index 9d2b0ded6..6610f907c 100644
--- a/src/da65.vcxproj
+++ b/src/da65.vcxproj
@@ -94,6 +94,7 @@
-
\ No newline at end of file
+
diff --git a/src/da65/attrtab.c b/src/da65/attrtab.c
index e35530afd..002965dff 100644
--- a/src/da65/attrtab.c
+++ b/src/da65/attrtab.c
@@ -146,8 +146,7 @@ unsigned GetGranularity (attr_t Style)
case atAddrTab: return 2;
case atRtsTab: return 2;
case atTextTab: return 1;
-
- case atSkip:
+ case atSkip: return 1;
default:
Internal ("GetGranularity called for style = %d", Style);
return 0;
diff --git a/src/da65/handler.c b/src/da65/handler.c
index 79b3192de..84229594f 100644
--- a/src/da65/handler.c
+++ b/src/da65/handler.c
@@ -47,6 +47,7 @@
#include "handler.h"
#include "labels.h"
#include "opctable.h"
+#include "opc45GS02.h"
#include "output.h"
@@ -226,6 +227,82 @@ void OH_Implicit (const OpcDesc* D)
+void OH_Implicit_ea_45GS02 (const OpcDesc* D)
+/* handle disassembling EOM prefixed opcodes, $ea $xx */
+{
+ /* Get byte after EOM */
+ unsigned opc = GetCodeByte (PC+1);
+ static const char *mnemonics[8] = {
+ "ora", "and", "eor", "adc", "sta", "lda", "cmp", "sbc"
+ };
+
+ if ((opc & 0x1f) == 0x12) {
+ unsigned zp = GetCodeByte (PC+2);
+
+ Indent (MCol);
+ Output ("%s", mnemonics[(opc >> 5) & 7]);
+
+ Indent (ACol);
+ Output ("[$%02X],z", zp);
+
+ /* Add the code stuff as comment */
+ LineComment (PC, 3);
+
+ /* End the line */
+ LineFeed ();
+ } else {
+ OH_Implicit (D);
+ }
+}
+
+
+
+void OH_Implicit_42_45GS02 (const OpcDesc* D)
+/* handle disassembling NEG NEG prefixed opcodes, $42 42 ($ea) $xx */
+{
+ /* Get bytes after NEG */
+ unsigned n1 = GetCodeByte (PC+1);
+ unsigned opc = GetCodeByte (PC+2);
+ /* NEG:NEG:NOP (42 42 ea) prefix */
+ static const char *mnemonics[8] = {
+ "orq", "andq", "eorq", "adcq", "stq", "ldq", "cmpq", "sbcq"
+ };
+
+ if (n1 == 0x42) {
+ /* detected 0x42 0x42 */
+ if (opc == 0xea) {
+ /* detected 0x42 0x42 0xea */
+ unsigned opc = GetCodeByte (PC+3);
+ if ((opc & 0x1f) == 0x12) {
+ unsigned zp = GetCodeByte (PC+4);
+
+ Indent (MCol);
+ Output ("%s", mnemonics[(opc >> 5) & 7]);
+
+ Indent (ACol);
+ Output ("[$%02X]", zp); /* with or without ,z ? */
+
+ /* Add the code stuff as comment */
+ LineComment (PC, 5);
+
+ /* End the line */
+ LineFeed ();
+ return;
+ }
+ } else {
+ /* use another table for these */
+ const OpcDesc* NewDesc = &OpcTable_45GS02_extended[opc];
+ NewDesc->Handler (NewDesc);
+ return;
+ }
+ }
+
+ /* no prefix detected */
+ OH_Implicit (D);
+}
+
+
+
void OH_Immediate (const OpcDesc* D)
{
OneLine (D, "#$%02X", GetCodeByte (PC+1));
@@ -276,6 +353,20 @@ void OH_Direct (const OpcDesc* D)
+void OH_Direct_Q (const OpcDesc* D)
+{
+ /* Get the operand */
+ unsigned Addr = GetCodeByte (PC+3);
+
+ /* Generate a label in pass 1 */
+ GenerateLabel (D->Flags, Addr);
+
+ /* Output the line */
+ OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
+}
+
+
+
void OH_DirectX (const OpcDesc* D)
{
/* Get the operand */
@@ -290,6 +381,20 @@ void OH_DirectX (const OpcDesc* D)
+void OH_DirectX_Q (const OpcDesc* D)
+{
+ /* Get the operand */
+ unsigned Addr = GetCodeByte (PC+3);
+
+ /* Generate a label in pass 1 */
+ GenerateLabel (D->Flags, Addr);
+
+ /* Output the line */
+ OneLine (D, "%s,x", GetAddrArg (D->Flags, Addr));
+}
+
+
+
void OH_DirectY (const OpcDesc* D)
{
/* Get the operand */
@@ -318,6 +423,20 @@ void OH_Absolute (const OpcDesc* D)
+void OH_Absolute_Q (const OpcDesc* D)
+{
+ /* Get the operand */
+ unsigned Addr = GetCodeWord (PC+3);
+
+ /* Generate a label in pass 1 */
+ GenerateLabel (D->Flags, Addr);
+
+ /* Output the line */
+ OneLine (D, "%s%s", GetAbsOverride (D->Flags, Addr), GetAddrArg (D->Flags, Addr));
+}
+
+
+
void OH_AbsoluteX (const OpcDesc* D)
{
/* Get the operand */
@@ -332,6 +451,20 @@ void OH_AbsoluteX (const OpcDesc* D)
+void OH_AbsoluteX_Q (const OpcDesc* D)
+{
+ /* Get the operand */
+ unsigned Addr = GetCodeWord (PC+3);
+
+ /* Generate a label in pass 1 */
+ GenerateLabel (D->Flags, Addr);
+
+ /* Output the line */
+ OneLine (D, "%s%s,x", GetAbsOverride (D->Flags, Addr), GetAddrArg (D->Flags, Addr));
+}
+
+
+
void OH_AbsoluteY (const OpcDesc* D)
{
/* Get the operand */
@@ -472,6 +605,20 @@ void OH_DirectIndirectZ (const OpcDesc* D)
+void OH_DirectIndirectZ_Q (const OpcDesc* D)
+{
+ /* Get the operand */
+ unsigned Addr = GetCodeByte (PC+3);
+
+ /* Generate a label in pass 1 */
+ GenerateLabel (D->Flags, Addr);
+
+ /* Output the line */
+ OneLine (D, "(%s),z", GetAddrArg (D->Flags, Addr));
+}
+
+
+
void OH_DirectXIndirect (const OpcDesc* D)
{
/* Get the operand */
@@ -533,6 +680,26 @@ void OH_BitBranch (const OpcDesc* D)
+void OH_BitBranch_m740 (const OpcDesc* D)
+/* zp, rel
+** NOTE: currently is part of the instruction
+*/
+{
+ /* unsigned Bit = GetCodeByte (PC) >> 5; */
+ unsigned Addr = GetCodeByte (PC+1);
+ signed char BranchOffs = GetCodeByte (PC+2);
+
+ /* Calculate the target address for the branch */
+ unsigned BranchAddr = (((int) PC+3) + BranchOffs) & 0xFFFF;
+
+ /* Generate a label in pass 1 */
+ GenerateLabel (D->Flags, Addr);
+ GenerateLabel (flLabel, BranchAddr);
+
+ /* Output the line */
+ OneLine (D, "%s, %s", GetAddrArg (D->Flags, Addr), GetAddrArg (flLabel, BranchAddr));
+}
+
void OH_ImmediateDirect (const OpcDesc* D)
{
/* Get the operand */
@@ -720,32 +887,36 @@ void OH_DirectImmediate (const OpcDesc* D)
void OH_ZeroPageBit (const OpcDesc* D)
+/* zp
+** NOTE: currently is part of the instruction
+*/
{
- unsigned Bit = GetCodeByte (PC) >> 5;
unsigned Addr = GetCodeByte (PC+1);
/* Generate a label in pass 1 */
GenerateLabel (D->Flags, Addr);
/* Output the line */
- OneLine (D, "%01X,%s", Bit, GetAddrArg (D->Flags, Addr));
+ OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
}
void OH_AccumulatorBit (const OpcDesc* D)
+/* A
+** NOTE: currently is part of the instruction
+*/
{
- unsigned Bit = GetCodeByte (PC) >> 5;
-
/* Output the line */
- OneLine (D, "%01X,a", Bit);
+ OneLine (D, "a");
}
-
void OH_AccumulatorBitBranch (const OpcDesc* D)
+/* A, rel
+** NOTE: currently is part of the instruction
+*/
{
- unsigned Bit = GetCodeByte (PC) >> 5;
signed char BranchOffs = GetCodeByte (PC+1);
/* Calculate the target address for the branch */
@@ -755,7 +926,7 @@ void OH_AccumulatorBitBranch (const OpcDesc* D)
GenerateLabel (flLabel, BranchAddr);
/* Output the line */
- OneLine (D, "%01X,a,%s", Bit, GetAddrArg (flLabel, BranchAddr));
+ OneLine (D, "a, %s", GetAddrArg (flLabel, BranchAddr));
}
@@ -770,17 +941,16 @@ void OH_JmpDirectIndirect (const OpcDesc* D)
}
-
void OH_SpecialPage (const OpcDesc* D)
+/* m740 "special page" address mode */
{
- /* Get the operand */
- unsigned Addr = 0xFF00 + GetCodeByte (PC+1);
+ /* Get the operand */
+ unsigned Addr = 0xFF00 + GetCodeByte (PC+1);
- /* Generate a label in pass 1 */
- GenerateLabel (D->Flags, Addr);
+ /* Generate a label in pass 1 */
+ GenerateLabel (D->Flags, Addr);
- /* OneLine (D, "$FF%02X", (CodeByte (PC+1)); */
- OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
+ OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
}
diff --git a/src/da65/handler.h b/src/da65/handler.h
index ee9b18bbc..fc82595c6 100644
--- a/src/da65/handler.h
+++ b/src/da65/handler.h
@@ -78,6 +78,7 @@ void OH_DirectXIndirect (const OpcDesc*);
void OH_AbsoluteIndirect (const OpcDesc*);
void OH_BitBranch (const OpcDesc*);
+void OH_BitBranch_m740 (const OpcDesc*);
void OH_ImmediateDirect (const OpcDesc*);
void OH_ImmediateDirectX (const OpcDesc*);
@@ -102,6 +103,15 @@ void OH_AccumulatorBitBranch (const OpcDesc*);
void OH_JmpDirectIndirect (const OpcDesc* D);
void OH_SpecialPage (const OpcDesc*);
+/* 45GS02 */
+void OH_Direct_Q (const OpcDesc*);
+void OH_DirectIndirectZ_Q (const OpcDesc* D);
+void OH_Absolute_Q (const OpcDesc* D);
+void OH_AbsoluteX_Q (const OpcDesc* D);
+void OH_DirectX_Q (const OpcDesc* D);
+void OH_Implicit_ea_45GS02 (const OpcDesc* D);
+void OH_Implicit_42_45GS02 (const OpcDesc* D);
+
/* Handlers for special instructions */
void OH_Rts (const OpcDesc*);
void OH_JmpAbsolute (const OpcDesc*);
diff --git a/src/da65/main.c b/src/da65/main.c
index 67a01dc3b..545cc657b 100644
--- a/src/da65/main.c
+++ b/src/da65/main.c
@@ -59,6 +59,7 @@
#include "infofile.h"
#include "labels.h"
#include "opctable.h"
+#include "opc45GS02.h"
#include "output.h"
#include "scanner.h"
#include "segment.h"
@@ -360,6 +361,51 @@ static void OptVersion (const char* Opt attribute ((unused)),
+static unsigned HandleChangedLength(const OpcDesc* D, unsigned PC)
+/* Instructions that have flSizeChanges set may use a different size than what
+** the table says. This function adjusts the PC accordingly, so after this only
+** the size from the table needs to be added to make up for the correct value
+*/
+{
+ if (D->Flags & flSizeChanges) {
+ if (CPU == CPU_45GS02) {
+ if (D->Handler == OH_Implicit_42_45GS02) {
+ if (GetCodeByte (PC+1) == 0x42) {
+ /* NEG:NEG prefix (0x42 0x42) */
+ unsigned opc = GetCodeByte (PC+2);
+ if (opc == 0xea) {
+ /* 42 42 ea */
+ if ((GetCodeByte (PC+3) & 0x1f) == 0x12) {
+ PC += 4;
+ }
+ } else {
+ /* 42 42 xx */
+ const OpcDesc* ED = &OpcTable_45GS02_extended[opc];
+ if (ED->Handler != OH_Illegal) {
+ PC += (ED->Size - 1);
+ }
+ }
+ }
+ } else if (D->Handler == OH_Implicit_ea_45GS02) {
+ /* NOP prefix (0xea) */
+ if ((GetCodeByte (PC+1) & 0x1f) == 0x12) {
+ PC += 2;
+ }
+ }
+ } else if (CPU == CPU_65816) {
+ if ((D->Handler == OH_Immediate65816M &&
+ GetAttr (PC) & atMem16) ||
+ (D->Handler == OH_Immediate65816X &&
+ GetAttr (PC) & atIdx16)) {
+ PC++;
+ }
+ }
+ }
+ return PC;
+}
+
+
+
static void OneOpcode (unsigned RemainingBytes)
/* Disassemble one opcode */
{
@@ -435,6 +481,7 @@ static void OneOpcode (unsigned RemainingBytes)
++PC;
} else {
D->Handler (D);
+ PC = HandleChangedLength (D, PC);
PC += D->Size;
}
break;
@@ -466,14 +513,8 @@ static void OneOpcode (unsigned RemainingBytes)
}
/* Output the insn */
D->Handler (D);
- if (CPU == CPU_65816 && (D->Flags & flSizeChanges)) {
- if ((D->Handler == OH_Immediate65816M &&
- GetAttr (PC) & atMem16) ||
- (D->Handler == OH_Immediate65816X &&
- GetAttr (PC) & atIdx16)) {
- PC++;
- }
- }
+
+ PC = HandleChangedLength (D, PC);
PC += D->Size;
break;
}
diff --git a/src/da65/opc45GS02.c b/src/da65/opc45GS02.c
new file mode 100644
index 000000000..21650f53d
--- /dev/null
+++ b/src/da65/opc45GS02.c
@@ -0,0 +1,565 @@
+/*****************************************************************************/
+/* */
+/* opc45GS02.c */
+/* */
+/* 45GS10 opcode description table */
+/* */
+/* */
+/* */
+/* (C) 2003-2011, Ullrich von Bassewitz */
+/* Roemerstrasse 52 */
+/* D-70794 Filderstadt */
+/* EMail: uz@cc65.org */
+/* */
+/* */
+/* This software is provided 'as-is', without any expressed or implied */
+/* warranty. In no event will the authors be held liable for any damages */
+/* arising from the use of this software. */
+/* */
+/* Permission is granted to anyone to use this software for any purpose, */
+/* including commercial applications, and to alter it and redistribute it */
+/* freely, subject to the following restrictions: */
+/* */
+/* 1. The origin of this software must not be misrepresented; you must not */
+/* claim that you wrote the original software. If you use this software */
+/* in a product, an acknowledgment in the product documentation would be */
+/* appreciated but is not required. */
+/* 2. Altered source versions must be plainly marked as such, and must not */
+/* be misrepresented as being the original software. */
+/* 3. This notice may not be removed or altered from any source */
+/* distribution. */
+/* */
+/*****************************************************************************/
+
+
+
+/* da65 */
+#include "handler.h"
+#include "opc45GS02.h"
+
+
+
+/*****************************************************************************/
+/* Data */
+/*****************************************************************************/
+
+
+
+/* Descriptions for all compound instructions with NEG:NEG prefix (0x42 0x42) */
+const OpcDesc OpcTable_45GS02_extended[256] = {
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $00 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $01 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $02 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $03 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $04 */
+ { "orq", 2+2, flUseLabel, OH_Direct_Q }, /* $05 */
+ { "aslq", 2+2, flUseLabel, OH_Direct_Q }, /* $06 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $07 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $08 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $09 */
+ { "aslq", 1+2, flNone, OH_Accumulator }, /* $0a */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $0b */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $0c */
+ { "orq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $0d */
+ { "aslq", 3+2, flUseLabel, OH_Absolute_Q }, /* $0e */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $0f */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $10 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $11 */
+ { "orq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $12 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $13 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $14 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $15 */
+ { "aslq", 2+2, flUseLabel, OH_DirectX_Q }, /* $16 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $17 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $18 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $19 */
+ { "inq", 1+2, flNone, OH_Accumulator }, /* $1a */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $1b */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $1c */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $1d */
+ { "aslq", 3+2, flUseLabel|flAbsOverride, OH_AbsoluteX_Q }, /* $1e */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $1f */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $20 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $21 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $22 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $23 */
+ { "bitq", 2+2, flUseLabel, OH_Direct_Q }, /* $24 */
+ { "andq", 2+2, flUseLabel, OH_Direct_Q }, /* $25 */
+ { "rolq", 2+2, flUseLabel, OH_Direct_Q }, /* $26 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $27 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $28 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $29 */
+ { "rolq", 1+2, flNone, OH_Accumulator }, /* $2a */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $2b */
+ { "bitq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $2c */
+ { "andq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $2d */
+ { "rolq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $2e */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $2f */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $30 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $31 */
+ { "andq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $32 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $33 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $34 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $35 */
+ { "rolq", 2+2, flUseLabel, OH_DirectX_Q }, /* $36 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $37 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $38 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $39 */
+ { "deq", 1+2, flNone, OH_Accumulator }, /* $3a */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $3b */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $3c */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $3d */
+ { "rolq", 3+2, flUseLabel|flAbsOverride, OH_AbsoluteX_Q }, /* $3e */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $3f */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $40 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $41 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $42 */
+ { "asrq", 1+2, flNone, OH_Accumulator }, /* $43 */
+ { "asrq", 2+2, flUseLabel, OH_Direct_Q }, /* $44 */
+ { "eorq", 2+2, flUseLabel, OH_Direct_Q }, /* $45 */
+ { "lsrq", 2+2, flUseLabel, OH_Direct_Q }, /* $46 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $47 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $48 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $49 */
+ { "lsrq", 1+2, flNone, OH_Accumulator }, /* $4a */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $4b */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $4c */
+ { "eorq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $4d */
+ { "lsrq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $4e */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $4f */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $50 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $51 */
+ { "eorq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $52 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $53 */
+ { "asrq", 2+2, flUseLabel, OH_DirectX_Q }, /* $54 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $55 */
+ { "lsrq", 2+2, flUseLabel, OH_DirectX_Q }, /* $56 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $57 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $58 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $59 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $5a */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $5b */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $5c */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $5d */
+ { "lsrq", 3+2, flUseLabel|flAbsOverride, OH_AbsoluteX_Q }, /* $5e */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $5f */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $60 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $61 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $62 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $63 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $64 */
+ { "adcq", 2+2, flUseLabel, OH_Direct_Q }, /* $65 */
+ { "rorq", 2+2, flUseLabel, OH_Direct_Q }, /* $66 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $67 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $68 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $69 */
+ { "rorq", 1+2, flNone, OH_Accumulator }, /* $6a */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $6b */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $6c */
+ { "adcq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $6d */
+ { "rorq", 3+2, flUseLabel, OH_Absolute_Q }, /* $6e */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $6f */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $70 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $71 */
+ { "adcq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $72 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $73 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $74 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $75 */
+ { "rorq", 2+2, flUseLabel, OH_DirectX_Q }, /* $76 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $77 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $78 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $79 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $7a */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $7b */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $7c */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $7d */
+ { "rorq", 3+2, flUseLabel|flAbsOverride, OH_AbsoluteX_Q }, /* $7e */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $7f */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $80 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $81 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $82 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $83 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $84 */
+ { "stq", 2+2, flUseLabel, OH_Direct_Q }, /* $85 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $86 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $87 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $88 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $89 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $8a */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $8b */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $8c */
+ { "stq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $8d */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $8e */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $8f */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $90 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $91 */
+ { "stq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $92 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $93 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $94 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $95 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $96 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $97 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $98 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $99 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $9a */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $9b */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $9c */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $9d */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $9e */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $9f */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $a0 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $a1 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $a2 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $a3 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $a4 */
+ { "ldq", 2+2, flUseLabel, OH_Direct_Q }, /* $a5 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $a6 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $a7 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $a8 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $a9 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $aa */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $ab */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $ac */
+ { "ldq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $ad */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $ae */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $af */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $b0 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $b1 */
+ { "ldq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $b2 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $b3 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $b4 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $b5 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $b6 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $b7 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $b8 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $b9 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $ba */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $bb */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $bc */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $bd */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $be */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $bf */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $c0 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $c1 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $c2 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $c3 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $c4 */
+ { "cmpq", 2+2, flUseLabel, OH_Direct_Q }, /* $c5 */
+ { "deq", 2+2, flUseLabel, OH_Direct_Q }, /* $c6 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $c7 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $c8 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $c9 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $ca */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $cb */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $cc */
+ { "cmpq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $cd */
+ { "deq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $ce */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $cf */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $d0 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $d1 */
+ { "cmpq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $d2 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $d3 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $d4 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $d5 */
+ { "deq", 2+2, flUseLabel, OH_DirectX_Q }, /* $d6 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $d7 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $d8 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $d9 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $da */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $db */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $dc */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $dd */
+ { "deq", 3+2, flUseLabel|flAbsOverride, OH_AbsoluteX_Q }, /* $de */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $df */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $e0 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $e1 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $e2 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $e3 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $e4 */
+ { "sbcq", 2+2, flUseLabel, OH_Direct_Q }, /* $e5 */
+ { "inq", 2+2, flUseLabel, OH_Direct_Q }, /* $e6 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $e7 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $e8 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $e9 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $ea */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $eb */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $ec */
+ { "sbcq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $ed */
+ { "inq", 3+2, flUseLabel|flAbsOverride, OH_Absolute_Q }, /* $ee */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $ef */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $f0 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $f1 */
+ { "sbcq", 2+2, flUseLabel, OH_DirectIndirectZ_Q }, /* $f2 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $f3 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $f4 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $f5 */
+ { "inq", 2+2, flUseLabel, OH_DirectX_Q }, /* $f6 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $f7 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $f8 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $f9 */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $fa */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $fb */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $fc */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $fd */
+ { "inq", 3+2, flUseLabel|flAbsOverride, OH_AbsoluteX_Q }, /* $fe */
+ { "", 1+2, flIllegal, OH_Illegal, }, /* $ff */
+};
+
+const OpcDesc OpcTable_45GS02[256] = {
+ { "brk", 1, flNone, OH_Implicit }, /* $00 */
+ { "ora", 2, flUseLabel, OH_DirectXIndirect }, /* $01 */
+ { "cle", 1, flNone, OH_Implicit }, /* $02 */
+ { "see", 1, flNone, OH_Implicit }, /* $03 */
+ { "tsb", 2, flUseLabel, OH_Direct }, /* $04 */
+ { "ora", 2, flUseLabel, OH_Direct }, /* $05 */
+ { "asl", 2, flUseLabel, OH_Direct }, /* $06 */
+ { "rmb0", 2, flUseLabel, OH_Direct }, /* $07 */
+ { "php", 1, flNone, OH_Implicit }, /* $08 */
+ { "ora", 2, flNone, OH_Immediate }, /* $09 */
+ { "asl", 1, flNone, OH_Accumulator }, /* $0a */
+ { "tsy", 1, flNone, OH_Implicit }, /* $0b */
+ { "tsb", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0c */
+ { "ora", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0d */
+ { "asl", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0e */
+ { "bbr0", 3, flUseLabel, OH_BitBranch }, /* $0f */
+ { "bpl", 2, flLabel, OH_Relative }, /* $10 */
+ { "ora", 2, flUseLabel, OH_DirectIndirectY }, /* $11 */
+ { "ora", 2, flUseLabel, OH_DirectIndirectZ }, /* $12 */
+ { "lbpl", 3, flLabel, OH_RelativeLong4510 }, /* $13 */
+ { "trb", 2, flUseLabel, OH_Direct }, /* $14 */
+ { "ora", 2, flUseLabel, OH_DirectX }, /* $15 */
+ { "asl", 2, flUseLabel, OH_DirectX }, /* $16 */
+ { "rmb1", 2, flUseLabel, OH_Direct }, /* $17 */
+ { "clc", 1, flNone, OH_Implicit }, /* $18 */
+ { "ora", 3, flUseLabel, OH_AbsoluteY }, /* $19 */
+ { "inc", 1, flNone, OH_Accumulator }, /* $1a */
+ { "inz", 1, flNone, OH_Implicit }, /* $1b */
+ { "trb", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $1c */
+ { "ora", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1d */
+ { "asl", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1e */
+ { "bbr1", 3, flUseLabel, OH_BitBranch }, /* $1f */
+ { "jsr", 3, flLabel, OH_Absolute }, /* $20 */
+ { "and", 2, flUseLabel, OH_DirectXIndirect }, /* $21 */
+ { "jsr", 3, flLabel, OH_JmpAbsoluteIndirect }, /* $22 */
+ { "jsr", 3, flLabel, OH_JmpAbsoluteXIndirect }, /* $23 */
+ { "bit", 2, flUseLabel, OH_Direct }, /* $24 */
+ { "and", 2, flUseLabel, OH_Direct }, /* $25 */
+ { "rol", 2, flUseLabel, OH_Direct }, /* $26 */
+ { "rmb2", 2, flUseLabel, OH_Direct }, /* $27 */
+ { "plp", 1, flNone, OH_Implicit }, /* $28 */
+ { "and", 2, flNone, OH_Immediate }, /* $29 */
+ { "rol", 1, flNone, OH_Accumulator }, /* $2a */
+ { "tys", 1, flNone, OH_Implicit }, /* $2b */
+ { "bit", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2c */
+ { "and", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2d */
+ { "rol", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2e */
+ { "bbr2", 3, flUseLabel, OH_BitBranch }, /* $2f */
+ { "bmi", 2, flLabel, OH_Relative }, /* $30 */
+ { "and", 2, flUseLabel, OH_DirectIndirectY }, /* $31 */
+ { "and", 2, flUseLabel, OH_DirectIndirectZ }, /* $32 */
+ { "lbmi", 3, flLabel, OH_RelativeLong4510 }, /* $33 */
+ { "bit", 2, flUseLabel, OH_DirectX }, /* $34 */
+ { "and", 2, flUseLabel, OH_DirectX }, /* $35 */
+ { "rol", 2, flUseLabel, OH_DirectX }, /* $36 */
+ { "rmb3", 2, flUseLabel, OH_Direct }, /* $37 */
+ { "sec", 1, flNone, OH_Implicit }, /* $38 */
+ { "and", 3, flUseLabel, OH_AbsoluteY }, /* $39 */
+ { "dec", 1, flNone, OH_Accumulator }, /* $3a */
+ { "dez", 1, flNone, OH_Implicit }, /* $3b */
+ { "bit", 3, flUseLabel, OH_AbsoluteX }, /* $3c */
+ { "and", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3d */
+ { "rol", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3e */
+ { "bbr3", 3, flUseLabel, OH_BitBranch }, /* $3f */
+ { "rti", 1, flNone, OH_Rts }, /* $40 */
+ { "eor", 2, flUseLabel, OH_DirectXIndirect }, /* $41 */
+ { "neg", 1, flSizeChanges, OH_Implicit_42_45GS02 }, /* $42 */
+ { "asr", 1, flNone, OH_Accumulator }, /* $43 */
+ { "asr", 2, flUseLabel, OH_Direct }, /* $44 */
+ { "eor", 2, flUseLabel, OH_Direct }, /* $45 */
+ { "lsr", 2, flUseLabel, OH_Direct }, /* $46 */
+ { "rmb4", 2, flUseLabel, OH_Direct }, /* $47 */
+ { "pha", 1, flNone, OH_Implicit }, /* $48 */
+ { "eor", 2, flNone, OH_Immediate }, /* $49 */
+ { "lsr", 1, flNone, OH_Accumulator }, /* $4a */
+ { "taz", 1, flNone, OH_Implicit }, /* $4b */
+ { "jmp", 3, flLabel, OH_JmpAbsolute }, /* $4c */
+ { "eor", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $4d */
+ { "lsr", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $4e */
+ { "bbr4", 3, flUseLabel, OH_BitBranch }, /* $4f */
+ { "bvc", 2, flLabel, OH_Relative }, /* $50 */
+ { "eor", 2, flUseLabel, OH_DirectIndirectY }, /* $51 */
+ { "eor", 2, flUseLabel, OH_DirectIndirectZ }, /* $52 */
+ { "lbvc", 3, flLabel, OH_RelativeLong4510 }, /* $53 */
+ { "asr", 2, flUseLabel, OH_DirectX }, /* $54 */
+ { "eor", 2, flUseLabel, OH_DirectX }, /* $55 */
+ { "lsr", 2, flUseLabel, OH_DirectX }, /* $56 */
+ { "rmb5", 2, flUseLabel, OH_Direct }, /* $57 */
+ { "cli", 1, flNone, OH_Implicit }, /* $58 */
+ { "eor", 3, flUseLabel, OH_AbsoluteY }, /* $59 */
+ { "phy", 1, flNone, OH_Implicit }, /* $5a */
+ { "tab", 1, flNone, OH_Implicit }, /* $5b */
+ { "map", 1, flNone, OH_Implicit }, /* $5c */
+ { "eor", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $5d */
+ { "lsr", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $5e */
+ { "bbr5", 3, flUseLabel, OH_BitBranch }, /* $5f */
+ { "rts", 1, flNone, OH_Rts }, /* $60 */
+ { "adc", 2, flUseLabel, OH_DirectXIndirect }, /* $61 */
+ { "rtn", 2, flNone, OH_Immediate }, /* $62 */
+ { "bsr", 3, flLabel, OH_RelativeLong4510 }, /* $63 */
+ { "stz", 2, flUseLabel, OH_Direct }, /* $64 */
+ { "adc", 2, flUseLabel, OH_Direct }, /* $65 */
+ { "ror", 2, flUseLabel, OH_Direct }, /* $66 */
+ { "rmb6", 2, flUseLabel, OH_Direct, }, /* $67 */
+ { "pla", 1, flNone, OH_Implicit }, /* $68 */
+ { "adc", 2, flNone, OH_Immediate }, /* $69 */
+ { "ror", 1, flNone, OH_Accumulator }, /* $6a */
+ { "tza", 1, flNone, OH_Implicit }, /* $6b */
+ { "jmp", 3, flLabel, OH_JmpAbsoluteIndirect }, /* $6c */
+ { "adc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $6d */
+ { "ror", 3, flUseLabel, OH_Absolute }, /* $6e */
+ { "bbr6", 3, flUseLabel, OH_BitBranch }, /* $6f */
+ { "bvs", 2, flLabel, OH_Relative }, /* $70 */
+ { "adc", 2, flUseLabel, OH_DirectIndirectY }, /* $71 */
+ { "adc", 2, flUseLabel, OH_DirectIndirectZ }, /* $72 */
+ { "lbvs", 3, flLabel, OH_RelativeLong4510 }, /* $73 */
+ { "stz", 2, flUseLabel, OH_DirectX }, /* $74 */
+ { "adc", 2, flUseLabel, OH_DirectX }, /* $75 */
+ { "ror", 2, flUseLabel, OH_DirectX }, /* $76 */
+ { "rmb7", 2, flUseLabel, OH_Direct }, /* $77 */
+ { "sei", 1, flNone, OH_Implicit }, /* $78 */
+ { "adc", 3, flUseLabel, OH_AbsoluteY }, /* $79 */
+ { "ply", 1, flNone, OH_Implicit }, /* $7a */
+ { "tba", 1, flNone, OH_Implicit }, /* $7b */
+ { "jmp", 3, flLabel, OH_AbsoluteXIndirect }, /* $7c */
+ { "adc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $7d */
+ { "ror", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $7e */
+ { "bbr7", 3, flUseLabel, OH_BitBranch }, /* $7f */
+ { "bra", 2, flLabel, OH_Relative }, /* $80 */
+ { "sta", 2, flUseLabel, OH_DirectXIndirect }, /* $81 */
+ { "sta", 2, flNone, OH_StackRelativeIndirectY4510}, /* $82 */
+ { "lbra", 3, flLabel, OH_RelativeLong4510 }, /* $83 */
+ { "sty", 2, flUseLabel, OH_Direct }, /* $84 */
+ { "sta", 2, flUseLabel, OH_Direct }, /* $85 */
+ { "stx", 2, flUseLabel, OH_Direct }, /* $86 */
+ { "smb0", 2, flUseLabel, OH_Direct }, /* $87 */
+ { "dey", 1, flNone, OH_Implicit }, /* $88 */
+ { "bit", 2, flNone, OH_Immediate }, /* $89 */
+ { "txa", 1, flNone, OH_Implicit }, /* $8a */
+ { "sty", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $8b */
+ { "sty", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8c */
+ { "sta", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8d */
+ { "stx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8e */
+ { "bbs0", 3, flUseLabel, OH_BitBranch }, /* $8f */
+ { "bcc", 2, flLabel, OH_Relative }, /* $90 */
+ { "sta", 2, flUseLabel, OH_DirectIndirectY }, /* $91 */
+ { "sta", 2, flUseLabel, OH_DirectIndirectZ }, /* $92 */
+ { "lbcc", 3, flLabel, OH_RelativeLong4510 }, /* $93 */
+ { "sty", 2, flUseLabel, OH_DirectX }, /* $94 */
+ { "sta", 2, flUseLabel, OH_DirectX }, /* $95 */
+ { "stx", 2, flUseLabel, OH_DirectY }, /* $96 */
+ { "smb1", 2, flUseLabel, OH_Direct }, /* $97 */
+ { "tya", 1, flNone, OH_Implicit }, /* $98 */
+ { "sta", 3, flUseLabel, OH_AbsoluteY }, /* $99 */
+ { "txs", 1, flNone, OH_Implicit }, /* $9a */
+ { "stx", 3, flUseLabel|flAbsOverride, OH_AbsoluteY }, /* $9b */
+ { "stz", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $9c */
+ { "sta", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $9d */
+ { "stz", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $9e */
+ { "bbs1", 3, flUseLabel, OH_BitBranch }, /* $9f */
+ { "ldy", 2, flNone, OH_Immediate }, /* $a0 */
+ { "lda", 2, flUseLabel, OH_DirectXIndirect }, /* $a1 */
+ { "ldx", 2, flNone, OH_Immediate }, /* $a2 */
+ { "ldz", 2, flNone, OH_Immediate }, /* $a3 */
+ { "ldy", 2, flUseLabel, OH_Direct }, /* $a4 */
+ { "lda", 2, flUseLabel, OH_Direct }, /* $a5 */
+ { "ldx", 2, flUseLabel, OH_Direct }, /* $a6 */
+ { "smb2", 2, flUseLabel, OH_Direct }, /* $a7 */
+ { "tay", 1, flNone, OH_Implicit }, /* $a8 */
+ { "lda", 2, flNone, OH_Immediate }, /* $a9 */
+ { "tax", 1, flNone, OH_Implicit }, /* $aa */
+ { "ldz", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ab */
+ { "ldy", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ac */
+ { "lda", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ad */
+ { "ldx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ae */
+ { "bbs2", 3, flUseLabel, OH_BitBranch }, /* $af */
+ { "bcs", 2, flLabel, OH_Relative }, /* $b0 */
+ { "lda", 2, flUseLabel, OH_DirectIndirectY }, /* $b1 */
+ { "lda", 2, flUseLabel, OH_DirectIndirectZ }, /* $b2 */
+ { "lbcs", 3, flLabel, OH_RelativeLong4510 }, /* $b3 */
+ { "ldy", 2, flUseLabel, OH_DirectX }, /* $b4 */
+ { "lda", 2, flUseLabel, OH_DirectX }, /* $b5 */
+ { "ldx", 2, flUseLabel, OH_DirectY }, /* $b6 */
+ { "smb3", 2, flUseLabel, OH_Direct }, /* $b7 */
+ { "clv", 1, flNone, OH_Implicit }, /* $b8 */
+ { "lda", 3, flUseLabel, OH_AbsoluteY }, /* $b9 */
+ { "tsx", 1, flNone, OH_Implicit }, /* $ba */
+ { "ldz", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $bb */
+ { "ldy", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $bc */
+ { "lda", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $bd */
+ { "ldx", 3, flUseLabel|flAbsOverride, OH_AbsoluteY }, /* $be */
+ { "bbs3", 3, flUseLabel, OH_BitBranch }, /* $bf */
+ { "cpy", 2, flNone, OH_Immediate }, /* $c0 */
+ { "cmp", 2, flUseLabel, OH_DirectXIndirect }, /* $c1 */
+ { "cpz", 2, flNone, OH_Immediate }, /* $c2 */
+ { "dew", 2, flUseLabel, OH_Direct }, /* $c3 */
+ { "cpy", 2, flUseLabel, OH_Direct }, /* $c4 */
+ { "cmp", 2, flUseLabel, OH_Direct }, /* $c5 */
+ { "dec", 2, flUseLabel, OH_Direct }, /* $c6 */
+ { "smb4", 2, flUseLabel, OH_Direct }, /* $c7 */
+ { "iny", 1, flNone, OH_Implicit }, /* $c8 */
+ { "cmp", 2, flNone, OH_Immediate }, /* $c9 */
+ { "dex", 1, flNone, OH_Implicit }, /* $ca */
+ { "asw", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cb */
+ { "cpy", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cc */
+ { "cmp", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cd */
+ { "dec", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ce */
+ { "bbs4", 3, flUseLabel, OH_BitBranch }, /* $cf */
+ { "bne", 2, flLabel, OH_Relative }, /* $d0 */
+ { "cmp", 2, flUseLabel, OH_DirectIndirectY }, /* $d1 */
+ { "cmp", 2, flUseLabel, OH_DirectIndirectZ }, /* $d2 */
+ { "lbne", 3, flLabel, OH_RelativeLong4510 }, /* $d3 */
+ { "cpz", 2, flUseLabel, OH_Direct }, /* $d4 */
+ { "cmp", 2, flUseLabel, OH_DirectX }, /* $d5 */
+ { "dec", 2, flUseLabel, OH_DirectX }, /* $d6 */
+ { "smb5", 2, flUseLabel, OH_Direct }, /* $d7 */
+ { "cld", 1, flNone, OH_Implicit }, /* $d8 */
+ { "cmp", 3, flUseLabel, OH_AbsoluteY }, /* $d9 */
+ { "phx", 1, flNone, OH_Implicit }, /* $da */
+ { "phz", 1, flNone, OH_Implicit }, /* $db */
+ { "cpz", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $dc */
+ { "cmp", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $dd */
+ { "dec", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $de */
+ { "bbs5", 3, flUseLabel, OH_BitBranch }, /* $df */
+ { "cpx", 2, flNone, OH_Immediate }, /* $e0 */
+ { "sbc", 2, flUseLabel, OH_DirectXIndirect }, /* $e1 */
+ { "lda", 2, flNone, OH_StackRelativeIndirectY4510}, /* $e2 */
+ { "inw", 2, flUseLabel, OH_Direct }, /* $e3 */
+ { "cpx", 2, flUseLabel, OH_Direct }, /* $e4 */
+ { "sbc", 2, flUseLabel, OH_Direct }, /* $e5 */
+ { "inc", 2, flUseLabel, OH_Direct }, /* $e6 */
+ { "smb6", 2, flUseLabel, OH_Direct }, /* $e7 */
+ { "inx", 1, flNone, OH_Implicit }, /* $e8 */
+ { "sbc", 2, flNone, OH_Immediate }, /* $e9 */
+ { "eom", 1, flSizeChanges, OH_Implicit_ea_45GS02 }, /* $ea */
+ { "row", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $eb */
+ { "cpx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ec */
+ { "sbc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ed */
+ { "inc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ee */
+ { "bbs6", 3, flUseLabel, OH_BitBranch }, /* $ef */
+ { "beq", 2, flLabel, OH_Relative }, /* $f0 */
+ { "sbc", 2, flUseLabel, OH_DirectIndirectY }, /* $f1 */
+ { "sbc", 2, flUseLabel, OH_DirectIndirectZ }, /* $f2 */
+ { "lbeq", 3, flLabel, OH_RelativeLong4510 }, /* $f3 */
+ { "phw", 3, flNone, OH_ImmediateWord }, /* $f4 */
+ { "sbc", 2, flUseLabel, OH_DirectX }, /* $f5 */
+ { "inc", 2, flUseLabel, OH_DirectX }, /* $f6 */
+ { "smb7", 2, flUseLabel, OH_Direct }, /* $f7 */
+ { "sed", 1, flNone, OH_Implicit }, /* $f8 */
+ { "sbc", 3, flUseLabel, OH_AbsoluteY }, /* $f9 */
+ { "plx", 1, flNone, OH_Implicit }, /* $fa */
+ { "plz", 1, flNone, OH_Implicit }, /* $fb */
+ { "phw", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $fc */
+ { "sbc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $fd */
+ { "inc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $fe */
+ { "bbs7", 3, flUseLabel, OH_BitBranch }, /* $ff */
+};
diff --git a/src/da65/opc45GS02.h b/src/da65/opc45GS02.h
new file mode 100644
index 000000000..624e4bbd9
--- /dev/null
+++ b/src/da65/opc45GS02.h
@@ -0,0 +1,58 @@
+/*****************************************************************************/
+/* */
+/* opc45GS02.h */
+/* */
+/* 45GS10 opcode description table */
+/* */
+/* */
+/* */
+/* (C) 2003 Ullrich von Bassewitz */
+/* Roemerstrasse 52 */
+/* D-70794 Filderstadt */
+/* EMail: uz@cc65.org */
+/* */
+/* */
+/* This software is provided 'as-is', without any expressed or implied */
+/* warranty. In no event will the authors be held liable for any damages */
+/* arising from the use of this software. */
+/* */
+/* Permission is granted to anyone to use this software for any purpose, */
+/* including commercial applications, and to alter it and redistribute it */
+/* freely, subject to the following restrictions: */
+/* */
+/* 1. The origin of this software must not be misrepresented; you must not */
+/* claim that you wrote the original software. If you use this software */
+/* in a product, an acknowledgment in the product documentation would be */
+/* appreciated but is not required. */
+/* 2. Altered source versions must be plainly marked as such, and must not */
+/* be misrepresented as being the original software. */
+/* 3. This notice may not be removed or altered from any source */
+/* distribution. */
+/* */
+/*****************************************************************************/
+
+
+
+#ifndef OPC45GS02_H
+#define OPC45GS02_H
+
+
+
+#include "opcdesc.h"
+
+
+
+/*****************************************************************************/
+/* Data */
+/*****************************************************************************/
+
+
+
+/* Descriptions for all opcodes */
+extern const OpcDesc OpcTable_45GS02[256];
+extern const OpcDesc OpcTable_45GS02_extended[256];
+
+
+/* End of opc45GS02.h */
+
+#endif
diff --git a/src/da65/opc6502x.c b/src/da65/opc6502x.c
index 3bdc8a549..c5fb5888c 100644
--- a/src/da65/opc6502x.c
+++ b/src/da65/opc6502x.c
@@ -188,7 +188,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "dey", 1, flNone, OH_Implicit }, /* $88 */
{ "nop", 2, flNone, OH_Immediate }, /* $89 */
{ "txa", 1, flNone, OH_Implicit }, /* $8a */
- { "xaa", 2, flNone, OH_Immediate }, /* $8b */
+ { "ane", 2, flNone, OH_Immediate }, /* $8b */
{ "sty", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8c */
{ "sta", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8d */
{ "stx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8e */
@@ -196,7 +196,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "bcc", 2, flLabel, OH_Relative }, /* $90 */
{ "sta", 2, flUseLabel, OH_DirectIndirectY }, /* $91 */
{ "jam", 1, flNone, OH_Implicit }, /* $92 */
- { "ahx", 2, flUseLabel, OH_DirectIndirectY }, /* $93 */
+ { "sha", 2, flUseLabel, OH_DirectIndirectY }, /* $93 */
{ "sty", 2, flUseLabel, OH_DirectX }, /* $94 */
{ "sta", 2, flUseLabel, OH_DirectX }, /* $95 */
{ "stx", 2, flUseLabel, OH_DirectY }, /* $96 */
@@ -208,7 +208,7 @@ const OpcDesc OpcTable_6502X[256] = {
{ "shy", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $9c */
{ "sta", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $9d */
{ "shx", 3, flUseLabel, OH_AbsoluteY }, /* $9e */
- { "ahx", 3, flUseLabel, OH_AbsoluteY }, /* $9f */
+ { "sha", 3, flUseLabel, OH_AbsoluteY }, /* $9f */
{ "ldy", 2, flNone, OH_Immediate }, /* $a0 */
{ "lda", 2, flUseLabel, OH_DirectXIndirect }, /* $a1 */
{ "ldx", 2, flNone, OH_Immediate }, /* $a2 */
diff --git a/src/da65/opcm740.c b/src/da65/opcm740.c
index 67a36b48c..6d12a7d37 100644
--- a/src/da65/opcm740.c
+++ b/src/da65/opcm740.c
@@ -44,264 +44,265 @@
/* Data */
/*****************************************************************************/
-
+/* CAUTION: in the pdf $1a is dec, and $3a is inc - if that is really the case,
+ * the table below should be fixed and this notice removed */
/* Descriptions for all opcodes */
const OpcDesc OpcTable_M740[256] = {
{ "brk", 1, flNone, OH_Implicit }, /* $00 */
{ "ora", 2, flUseLabel, OH_DirectXIndirect }, /* $01 */
{ "jsr", 2, flLabel, OH_JmpDirectIndirect }, /* $02 */
- { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $03 */
+ { "bbs0", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $03 */
{ "", 1, flIllegal, OH_Illegal }, /* $04 */
{ "ora", 2, flUseLabel, OH_Direct }, /* $05 */
{ "asl", 2, flUseLabel, OH_Direct }, /* $06 */
- { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $07 */
+ { "bbs0", 3, flUseLabel, OH_BitBranch_m740 }, /* $07 */
{ "php", 1, flNone, OH_Implicit }, /* $08 */
{ "ora", 2, flNone, OH_Immediate }, /* $09 */
{ "asl", 1, flNone, OH_Accumulator }, /* $0a */
- { "seb", 1, flNone, OH_AccumulatorBit }, /* $0b */
+ { "seb0", 1, flNone, OH_AccumulatorBit }, /* $0b */
{ "", 1, flIllegal, OH_Illegal, }, /* $0c */
{ "ora", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0d */
{ "asl", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0e */
- { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $0f */
+ { "seb0", 2, flUseLabel, OH_ZeroPageBit }, /* $0f */
{ "bpl", 2, flLabel, OH_Relative }, /* $10 */
{ "ora", 2, flUseLabel, OH_DirectIndirectY }, /* $11 */
{ "clt", 1, flNone, OH_Implicit }, /* $12 */
- { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $13 */
+ { "bbc0", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $13 */
{ "", 1, flIllegal, OH_Illegal }, /* $14 */
{ "ora", 2, flUseLabel, OH_DirectX }, /* $15 */
{ "asl", 2, flUseLabel, OH_DirectX }, /* $16 */
- { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $17 */
+ { "bbc0", 3, flUseLabel, OH_BitBranch_m740 }, /* $17 */
{ "clc", 1, flNone, OH_Implicit }, /* $18 */
{ "ora", 3, flUseLabel, OH_AbsoluteY }, /* $19 */
- { "dec", 1, flNone, OH_Accumulator }, /* $1a */
- { "clb", 1, flNone, OH_AccumulatorBit }, /* $1b */
+ { "inc", 1, flNone, OH_Accumulator }, /* $1a */
+ { "clb0", 1, flNone, OH_AccumulatorBit }, /* $1b */
{ "", 1, flIllegal, OH_Illegal }, /* $1c */
{ "ora", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1d */
{ "asl", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1e */
- { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $1f */
+ { "clb0", 2, flUseLabel, OH_ZeroPageBit }, /* $1f */
{ "jsr", 3, flLabel, OH_Absolute }, /* $20 */
{ "and", 2, flUseLabel, OH_DirectXIndirect }, /* $21 */
{ "jsr", 2, flLabel, OH_SpecialPage }, /* $22 */
- { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $23 */
+ { "bbs1", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $23 */
{ "bit", 2, flUseLabel, OH_Direct }, /* $24 */
{ "and", 2, flUseLabel, OH_Direct }, /* $25 */
{ "rol", 2, flUseLabel, OH_Direct }, /* $26 */
- { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $27 */
+ { "bbs1", 3, flUseLabel, OH_BitBranch_m740 }, /* $27 */
{ "plp", 1, flNone, OH_Implicit }, /* $28 */
{ "and", 2, flNone, OH_Immediate }, /* $29 */
{ "rol", 1, flNone, OH_Accumulator }, /* $2a */
- { "seb", 1, flNone, OH_AccumulatorBit }, /* $2b */
+ { "seb1", 1, flNone, OH_AccumulatorBit }, /* $2b */
{ "bit", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2c */
{ "and", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2d */
{ "rol", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2e */
- { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $2f */
+ { "seb1", 2, flUseLabel, OH_ZeroPageBit }, /* $2f */
{ "bmi", 2, flLabel, OH_Relative }, /* $30 */
{ "and", 2, flUseLabel, OH_DirectIndirectY }, /* $31 */
{ "set", 1, flNone, OH_Implicit }, /* $32 */
- { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $33 */
+ { "bbc1", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $33 */
{ "", 1, flIllegal, OH_Illegal }, /* $34 */
{ "and", 2, flUseLabel, OH_DirectX }, /* $35 */
{ "rol", 2, flUseLabel, OH_DirectX }, /* $36 */
- { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $37 */
+ { "bbc1", 3, flUseLabel, OH_BitBranch_m740 }, /* $37 */
{ "sec", 1, flNone, OH_Implicit }, /* $38 */
{ "and", 3, flUseLabel, OH_AbsoluteY }, /* $39 */
- { "inc", 1, flNone, OH_Accumulator }, /* $3a */
- { "clb", 1, flNone, OH_AccumulatorBit }, /* $3b */
+ { "dec", 1, flNone, OH_Accumulator }, /* $3a */
+ { "clb1", 1, flNone, OH_AccumulatorBit }, /* $3b */
{ "ldm", 3, flLabel, OH_DirectImmediate }, /* $3c */
{ "and", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3d */
{ "rol", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3e */
- { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $3f */
+ { "clb1", 2, flUseLabel, OH_ZeroPageBit }, /* $3f */
{ "rti", 1, flNone, OH_Rts }, /* $40 */
{ "eor", 2, flUseLabel, OH_DirectXIndirect }, /* $41 */
{ "stp", 1, flNone, OH_Implicit }, /* $42 */
- { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $43 */
+ { "bbs2", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $43 */
{ "com", 2, flUseLabel, OH_Direct }, /* $44 */
{ "eor", 2, flUseLabel, OH_Direct }, /* $45 */
{ "lsr", 2, flUseLabel, OH_Direct }, /* $46 */
- { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $47 */
+ { "bbs2", 3, flUseLabel, OH_BitBranch_m740 }, /* $47 */
{ "pha", 1, flNone, OH_Implicit }, /* $48 */
{ "eor", 2, flNone, OH_Immediate }, /* $49 */
{ "lsr", 1, flNone, OH_Accumulator }, /* $4a */
- { "seb", 1, flNone, OH_AccumulatorBit }, /* $4b */
+ { "seb2", 1, flNone, OH_AccumulatorBit }, /* $4b */
{ "jmp", 3, flLabel, OH_JmpAbsolute }, /* $4c */
{ "eor", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $4d */
{ "lsr", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $4e */
- { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $4f */
+ { "seb2", 2, flUseLabel, OH_ZeroPageBit }, /* $4f */
{ "bvc", 2, flLabel, OH_Relative }, /* $50 */
{ "eor", 2, flUseLabel, OH_DirectIndirectY }, /* $51 */
{ "", 1, flIllegal, OH_Illegal }, /* $52 */
- { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $53 */
+ { "bbc2", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $53 */
{ "", 1, flIllegal, OH_Illegal }, /* $54 */
{ "eor", 2, flUseLabel, OH_DirectX }, /* $55 */
{ "lsr", 2, flUseLabel, OH_DirectX }, /* $56 */
- { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $57 */
+ { "bbc2", 3, flUseLabel, OH_BitBranch_m740 }, /* $57 */
{ "cli", 1, flNone, OH_Implicit }, /* $58 */
{ "eor", 3, flUseLabel, OH_AbsoluteY }, /* $59 */
{ "", 1, flIllegal, OH_Illegal }, /* $5a */
- { "clb", 1, flNone, OH_AccumulatorBit }, /* $5b */
+ { "clb2", 1, flNone, OH_AccumulatorBit }, /* $5b */
{ "", 1, flIllegal, OH_Illegal }, /* $5c */
{ "eor", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $5d */
{ "lsr", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $5e */
- { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $5f */
+ { "clb2", 2, flUseLabel, OH_ZeroPageBit }, /* $5f */
{ "rts", 1, flNone, OH_Rts }, /* $60 */
{ "adc", 2, flUseLabel, OH_DirectXIndirect }, /* $61 */
- { "mul", 2, flUseLabel, OH_DirectX }, /* $62 */
- { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $63 */
+ { "", 1, flIllegal, OH_Illegal }, /* $62 */
+ { "bbs3", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $63 */
{ "tst", 2, flUseLabel, OH_Direct }, /* $64 */
{ "adc", 2, flUseLabel, OH_Direct }, /* $65 */
{ "ror", 2, flUseLabel, OH_Direct }, /* $66 */
- { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $67 */
+ { "bbs3", 3, flUseLabel, OH_BitBranch_m740 }, /* $67 */
{ "pla", 1, flNone, OH_Implicit }, /* $68 */
{ "adc", 2, flNone, OH_Immediate }, /* $69 */
{ "ror", 1, flNone, OH_Accumulator }, /* $6a */
- { "seb", 1, flNone, OH_AccumulatorBit }, /* $6b */
+ { "seb3", 1, flNone, OH_AccumulatorBit }, /* $6b */
{ "jmp", 3, flLabel, OH_JmpAbsoluteIndirect }, /* $6c */
{ "adc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $6d */
{ "ror", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $6e */
- { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $6f */
+ { "seb3", 2, flUseLabel, OH_ZeroPageBit }, /* $6f */
{ "bvs", 2, flLabel, OH_Relative }, /* $70 */
{ "adc", 2, flUseLabel, OH_DirectIndirectY }, /* $71 */
{ "", 1, flIllegal, OH_Illegal }, /* $72 */
- { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $73 */
+ { "bbc3", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $73 */
{ "", 1, flIllegal, OH_Illegal }, /* $74 */
{ "adc", 2, flUseLabel, OH_DirectX }, /* $75 */
{ "ror", 2, flUseLabel, OH_DirectX }, /* $76 */
- { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $77 */
+ { "bbc3", 3, flUseLabel, OH_BitBranch_m740 }, /* $77 */
{ "sei", 1, flNone, OH_Implicit }, /* $78 */
{ "adc", 3, flUseLabel, OH_AbsoluteY }, /* $79 */
{ "", 1, flIllegal, OH_Illegal }, /* $7a */
- { "clb", 1, flNone, OH_AccumulatorBit }, /* $7b */
+ { "clb3", 1, flNone, OH_AccumulatorBit }, /* $7b */
{ "", 1, flIllegal, OH_Illegal }, /* $7c */
{ "adc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $7d */
{ "ror", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $7e */
- { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $7f */
+ { "clb3", 2, flUseLabel, OH_ZeroPageBit }, /* $7f */
{ "bra", 2, flLabel, OH_Relative }, /* $80 */
{ "sta", 2, flUseLabel, OH_DirectXIndirect }, /* $81 */
{ "rrf", 2, flLabel, OH_Direct }, /* $82 */
- { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $83 */
+ { "bbs4", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $83 */
{ "sty", 2, flUseLabel, OH_Direct }, /* $84 */
{ "sta", 2, flUseLabel, OH_Direct }, /* $85 */
{ "stx", 2, flUseLabel, OH_Direct }, /* $86 */
- { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $87 */
+ { "bbs4", 3, flUseLabel, OH_BitBranch_m740 }, /* $87 */
{ "dey", 1, flNone, OH_Implicit }, /* $88 */
{ "", 1, flIllegal, OH_Illegal }, /* $89 */
{ "txa", 1, flNone, OH_Implicit }, /* $8a */
- { "seb", 1, flNone, OH_AccumulatorBit }, /* $8b */
+ { "seb4", 1, flNone, OH_AccumulatorBit }, /* $8b */
{ "sty", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8c */
{ "sta", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8d */
{ "stx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8e */
- { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $8f */
+ { "seb4", 2, flUseLabel, OH_ZeroPageBit }, /* $8f */
{ "bcc", 2, flLabel, OH_Relative }, /* $90 */
{ "sta", 2, flUseLabel, OH_DirectIndirectY }, /* $91 */
{ "", 1, flIllegal, OH_Illegal }, /* $92 */
- { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $93 */
+ { "bbc4", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $93 */
{ "sty", 2, flUseLabel, OH_DirectX }, /* $94 */
{ "sta", 2, flUseLabel, OH_DirectX }, /* $95 */
{ "stx", 2, flUseLabel, OH_DirectY }, /* $96 */
- { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $97 */
+ { "bbc4", 3, flUseLabel, OH_BitBranch_m740 }, /* $97 */
{ "tya", 1, flNone, OH_Implicit }, /* $98 */
{ "sta", 3, flUseLabel, OH_AbsoluteY }, /* $99 */
{ "txs", 1, flNone, OH_Implicit }, /* $9a */
- { "clb", 1, flNone, OH_AccumulatorBit }, /* $9b */
+ { "clb4", 1, flNone, OH_AccumulatorBit }, /* $9b */
{ "", 1, flIllegal, OH_Illegal }, /* $9c */
{ "sta", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $9d */
{ "", 1, flIllegal, OH_Illegal }, /* $9e */
- { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $9f */
+ { "clb4", 2, flUseLabel, OH_ZeroPageBit }, /* $9f */
{ "ldy", 2, flNone, OH_Immediate }, /* $a0 */
{ "lda", 2, flUseLabel, OH_DirectXIndirect }, /* $a1 */
{ "ldx", 2, flNone, OH_Immediate }, /* $a2 */
- { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $a3 */
+ { "bbs5", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $a3 */
{ "ldy", 2, flUseLabel, OH_Direct }, /* $a4 */
{ "lda", 2, flUseLabel, OH_Direct }, /* $a5 */
{ "ldx", 2, flUseLabel, OH_Direct }, /* $a6 */
- { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $a7 */
+ { "bbs5", 3, flUseLabel, OH_BitBranch_m740 }, /* $a7 */
{ "tay", 1, flNone, OH_Implicit }, /* $a8 */
{ "lda", 2, flNone, OH_Immediate }, /* $a9 */
{ "tax", 1, flNone, OH_Implicit }, /* $aa */
- { "seb", 1, flNone, OH_AccumulatorBit }, /* $ab */
+ { "seb5", 1, flNone, OH_AccumulatorBit }, /* $ab */
{ "ldy", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ac */
{ "lda", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ad */
{ "ldx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ae */
- { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $af */
+ { "seb5", 2, flUseLabel, OH_ZeroPageBit }, /* $af */
{ "bcs", 2, flLabel, OH_Relative }, /* $b0 */
{ "lda", 2, flUseLabel, OH_DirectIndirectY }, /* $b1 */
{ "jmp", 2, flLabel, OH_JmpDirectIndirect }, /* $b2 */
- { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $b3 */
+ { "bbc5", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $b3 */
{ "ldy", 2, flUseLabel, OH_DirectX }, /* $b4 */
{ "lda", 2, flUseLabel, OH_DirectX }, /* $b5 */
{ "ldx", 2, flUseLabel, OH_DirectY }, /* $b6 */
- { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $b7 */
+ { "bbc5", 3, flUseLabel, OH_BitBranch_m740 }, /* $b7 */
{ "clv", 1, flNone, OH_Implicit }, /* $b8 */
{ "lda", 3, flUseLabel, OH_AbsoluteY }, /* $b9 */
{ "tsx", 1, flNone, OH_Implicit }, /* $ba */
- { "clb", 1, flNone, OH_AccumulatorBit }, /* $bb */
+ { "clb5", 1, flNone, OH_AccumulatorBit }, /* $bb */
{ "ldy", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $bc */
{ "lda", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $bd */
{ "ldx", 3, flUseLabel|flAbsOverride, OH_AbsoluteY }, /* $be */
- { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $bf */
+ { "clb5", 2, flUseLabel, OH_ZeroPageBit }, /* $bf */
{ "cpy", 2, flNone, OH_Immediate }, /* $c0 */
{ "cmp", 2, flUseLabel, OH_DirectXIndirect }, /* $c1 */
- { "wit", 1, flNone, OH_Implicit, }, /* $c2 */
- { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $c3 */
+ { "slw", 1, flNone, OH_Implicit, }, /* $c2 */
+ { "bbs6", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $c3 */
{ "cpy", 2, flUseLabel, OH_Direct }, /* $c4 */
{ "cmp", 2, flUseLabel, OH_Direct }, /* $c5 */
{ "dec", 2, flUseLabel, OH_Direct }, /* $c6 */
- { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $c7 */
+ { "bbs6", 3, flUseLabel, OH_BitBranch_m740 }, /* $c7 */
{ "iny", 1, flNone, OH_Implicit }, /* $c8 */
{ "cmp", 2, flNone, OH_Immediate }, /* $c9 */
{ "dex", 1, flNone, OH_Implicit }, /* $ca */
- { "seb", 1, flNone, OH_AccumulatorBit }, /* $cb */
+ { "seb6", 1, flNone, OH_AccumulatorBit }, /* $cb */
{ "cpy", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cc */
{ "cmp", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cd */
{ "dec", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ce */
- { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $cf */
+ { "seb6", 2, flUseLabel, OH_ZeroPageBit }, /* $cf */
{ "bne", 2, flLabel, OH_Relative }, /* $d0 */
{ "cmp", 2, flUseLabel, OH_DirectIndirectY }, /* $d1 */
{ "", 1, flIllegal, OH_Illegal }, /* $d2 */
- { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $d3 */
+ { "bbc6", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $d3 */
{ "", 1, flIllegal, OH_Illegal }, /* $d4 */
{ "cmp", 2, flUseLabel, OH_DirectX }, /* $d5 */
{ "dec", 2, flUseLabel, OH_DirectX }, /* $d6 */
- { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $d7 */
+ { "bbc6", 3, flUseLabel, OH_BitBranch_m740 }, /* $d7 */
{ "cld", 1, flNone, OH_Implicit }, /* $d8 */
{ "cmp", 3, flUseLabel, OH_AbsoluteY }, /* $d9 */
{ "", 1, flIllegal, OH_Illegal }, /* $da */
- { "clb", 1, flNone, OH_AccumulatorBit }, /* $db */
+ { "clb6", 1, flNone, OH_AccumulatorBit }, /* $db */
{ "", 1, flIllegal, OH_Illegal }, /* $dc */
{ "cmp", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $dd */
{ "dec", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $de */
- { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $df */
+ { "clb6", 2, flUseLabel, OH_ZeroPageBit }, /* $df */
{ "cpx", 2, flNone, OH_Immediate }, /* $e0 */
{ "sbc", 2, flUseLabel, OH_DirectXIndirect }, /* $e1 */
- { "div", 2, flUseLabel, OH_DirectX }, /* $e2 */
- { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $e3 */
+ { "fst", 1, flNone, OH_Implicit }, /* $e2 */
+ { "bbs7", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $e3 */
{ "cpx", 2, flUseLabel, OH_Direct }, /* $e4 */
{ "sbc", 2, flUseLabel, OH_Direct }, /* $e5 */
{ "inc", 2, flUseLabel, OH_Direct }, /* $e6 */
- { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $e7 */
+ { "bbs7", 3, flUseLabel, OH_BitBranch_m740 }, /* $e7 */
{ "inx", 1, flNone, OH_Implicit }, /* $e8 */
{ "sbc", 2, flNone, OH_Immediate }, /* $e9 */
{ "nop", 1, flNone, OH_Implicit }, /* $ea */
- { "seb", 1, flNone, OH_AccumulatorBit }, /* $eb */
+ { "seb7", 1, flNone, OH_AccumulatorBit }, /* $eb */
{ "cpx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ec */
{ "sbc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ed */
{ "inc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ee */
- { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $ef */
+ { "seb7", 2, flUseLabel, OH_ZeroPageBit }, /* $ef */
{ "beq", 2, flLabel, OH_Relative }, /* $f0 */
{ "sbc", 2, flUseLabel, OH_DirectIndirectY }, /* $f1 */
{ "", 1, flIllegal, OH_Illegal }, /* $f2 */
- { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $f3 */
+ { "bbc7", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $f3 */
{ "", 1, flIllegal, OH_Illegal }, /* $f4 */
{ "sbc", 2, flUseLabel, OH_DirectX }, /* $f5 */
{ "inc", 2, flUseLabel, OH_DirectX }, /* $f6 */
- { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $f7 */
+ { "bbc7", 3, flUseLabel, OH_BitBranch_m740 }, /* $f7 */
{ "sed", 1, flNone, OH_Implicit }, /* $f8 */
{ "sbc", 3, flUseLabel, OH_AbsoluteY }, /* $f9 */
{ "", 1, flIllegal, OH_Illegal }, /* $fa */
- { "clb", 1, flNone, OH_AccumulatorBit }, /* $fb */
+ { "clb7", 1, flNone, OH_AccumulatorBit }, /* $fb */
{ "", 1, flIllegal, OH_Illegal }, /* $fc */
{ "sbc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $fd */
{ "inc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $fe */
- { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $ff */
+ { "clb7", 2, flUseLabel, OH_ZeroPageBit }, /* $ff */
};
diff --git a/src/da65/opctable.c b/src/da65/opctable.c
index d9068d253..445f8880c 100644
--- a/src/da65/opctable.c
+++ b/src/da65/opctable.c
@@ -36,6 +36,7 @@
/* da65 */
#include "error.h"
#include "opc4510.h"
+#include "opc45GS02.h"
#include "opc6502.h"
#include "opc6502x.h"
#include "opc6502dtv.h"
@@ -78,6 +79,7 @@ void SetOpcTable (cpu_t CPU)
case CPU_HUC6280: OpcTable = OpcTable_HuC6280; break;
case CPU_M740: OpcTable = OpcTable_M740; break;
case CPU_4510: OpcTable = OpcTable_4510; break;
+ case CPU_45GS02: OpcTable = OpcTable_45GS02; break;
default: Error ("Unsupported CPU");
}
}
diff --git a/targettest/Makefile b/targettest/Makefile
index f78e22461..56b5df446 100644
--- a/targettest/Makefile
+++ b/targettest/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
#
# Makefile for cc65 testcode
#
diff --git a/targettest/accelerator/Makefile b/targettest/accelerator/Makefile
index dd5011459..6e710d010 100644
--- a/targettest/accelerator/Makefile
+++ b/targettest/accelerator/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
SYS ?= c64
diff --git a/targettest/atari/Makefile b/targettest/atari/Makefile
index d5b4d9593..0e376e9bc 100644
--- a/targettest/atari/Makefile
+++ b/targettest/atari/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/targettest/cbm/Makefile b/targettest/cbm/Makefile
index c3171b13e..ebe00198f 100644
--- a/targettest/cbm/Makefile
+++ b/targettest/cbm/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
SYS ?= c64
diff --git a/targettest/gamate/Makefile b/targettest/gamate/Makefile
index e2b060406..f03c2b064 100644
--- a/targettest/gamate/Makefile
+++ b/targettest/gamate/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/targettest/pce/Makefile b/targettest/pce/Makefile
index 89abca6b6..549720a40 100644
--- a/targettest/pce/Makefile
+++ b/targettest/pce/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Run 'make SYS='; or, set a SYS env.
# var. to build for another target system.
diff --git a/test/Makefile b/test/Makefile
index 495082fa4..94bc7e5ea 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# top-level Makefile for the regression tests
ifneq ($(shell echo),)
diff --git a/test/asm/Makefile b/test/asm/Makefile
index 5b3bff3f8..2d5ba764e 100644
--- a/test/asm/Makefile
+++ b/test/asm/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# top-level Makefile for the regression tests
ifneq ($(shell echo),)
diff --git a/test/asm/cpudetect/45GS02-cpudetect.ref b/test/asm/cpudetect/45GS02-cpudetect.ref
new file mode 100644
index 000000000..e9aa843cd
Binary files /dev/null and b/test/asm/cpudetect/45GS02-cpudetect.ref differ
diff --git a/test/asm/cpudetect/Makefile b/test/asm/cpudetect/Makefile
index ffddb1ad8..fde19b17b 100644
--- a/test/asm/cpudetect/Makefile
+++ b/test/asm/cpudetect/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the assembler regression tests
ifneq ($(shell echo),)
diff --git a/test/asm/cpudetect/allinst.inc b/test/asm/cpudetect/allinst.inc
new file mode 100644
index 000000000..8e27a5429
--- /dev/null
+++ b/test/asm/cpudetect/allinst.inc
@@ -0,0 +1,898 @@
+
+ ; just emit to bss for now, this way the output wont get checked, which is
+ ; fine - we only want to see if the assembler accepts all the opcodes it
+ ; should accept for the current CPU mode
+ .bss
+
+.if (.cpu .bitand CPU_ISET_6502)
+ .scope
+ ; regular basic 6502 (legal) instruction set
+LABEL0:
+ brk ; $00
+ ora ($12,x) ; $01
+ ora $12 ; $05
+ asl $12 ; $06
+ php ; $08
+ ora #$12 ; $09
+ asl a ; $0a
+ ora $1234 ; $0d
+ asl $1234 ; $0e
+ bpl LABEL0 ; $10
+ ora ($12),y ; $11
+ ora $12,x ; $15
+ asl $12,x ; $16
+ clc ; $18
+ ora $1234,y ; $19
+ ora $1234,x ; $1d
+ asl $1234,x ; $1e
+ jsr $1234 ; $20
+ and ($12,x) ; $21
+ bit $12 ; $24
+ and $12 ; $25
+ rol $12 ; $26
+ plp ; $28
+ and #$12 ; $29
+ rol a ; $2a
+ bit $1234 ; $2c
+ and $1234 ; $2d
+ rol $1234 ; $2e
+ bmi LABEL ; $30
+ and ($12),y ; $31
+ and $12,x ; $35
+ rol $12,x ; $36
+ sec ; $38
+ and $1234,y ; $39
+ and $1234,x ; $3d
+ rol $1234,x ; $3e
+ rti ; $40
+ eor ($12,x) ; $41
+ eor $12 ; $45
+ lsr $12 ; $46
+ pha ; $48
+ eor #$12 ; $49
+ lsr a ; $4a
+ jmp $1234 ; $4c
+ eor $1234 ; $4d
+ lsr $1234 ; $4e
+ bvc LABEL ; $50
+ eor ($12),y ; $51
+ eor $12,x ; $55
+ lsr $12,x ; $56
+ cli ; $58
+ eor $1234,y ; $59
+ eor $1234,x ; $5d
+ lsr $1234,x ; $5e
+ rts ; $60
+ adc ($12,x) ; $61
+ adc $12 ; $65
+ ror $12 ; $66
+ pla ; $68
+ adc #$12 ; $69
+ ror a ; $6a
+ jmp ($1234) ; $6c
+ adc $1234 ; $6d
+ ror $1234 ; $6e
+ bvs LABEL ; $70
+ adc ($12),y ; $71
+ adc $12,x ; $75
+ ror $12,x ; $76
+ sei ; $78
+ adc $1234,y ; $79
+ adc $1234,x ; $7d
+ ror $1234,x ; $7e
+LABEL:
+ sta ($12,x) ; $81
+ sty $12 ; $84
+ sta $12 ; $85
+ stx $12 ; $86
+ dey ; $88
+ txa ; $8a
+ sty $1234 ; $8c
+ sta $1234 ; $8d
+ stx $1234 ; $8e
+ bcc LABEL ; $90
+ sta ($12),y ; $91
+ sty $12,x ; $94
+ sta $12,x ; $95
+ stx $12,y ; $96
+ tya ; $98
+ sta $1234,y ; $99
+ txs ; $9a
+ sta $1234,x ; $9d
+ ldy #$12 ; $a0
+ lda ($12,x) ; $a1
+ ldx #$12 ; $a2
+ ldy $12 ; $a4
+ lda $12 ; $a5
+ ldx $12 ; $a6
+ tay ; $a8
+ lda #$12 ; $a9
+ tax ; $aa
+ ldy $1234 ; $ac
+ lda $1234 ; $ad
+ ldx $1234 ; $ae
+ bcs LABEL ; $b0
+ lda ($12),y ; $b1
+ ldy $12,x ; $b4
+ lda $12,x ; $b5
+ ldx $12,y ; $b6
+ clv ; $b8
+ lda $1234,y ; $b9
+ tsx ; $ba
+ ldy $1234,x ; $bc
+ lda $1234,x ; $bd
+ ldx $1234,y ; $be
+ cpy #$12 ; $c0
+ cmp ($12,x) ; $c1
+ cpy $12 ; $c4
+ cmp $12 ; $c5
+ dec $12 ; $c6
+ iny ; $c8
+ cmp #$12 ; $c9
+ dex ; $ca
+ cpy $1234 ; $cc
+ cmp $1234 ; $cd
+ dec $1234 ; $ce
+ bne LABEL ; $d0
+ cmp ($12),y ; $d1
+ cmp $12,x ; $d5
+ dec $12,x ; $d6
+ cld ; $d8
+ cmp $1234,y ; $d9
+ cmp $1234,x ; $dd
+ dec $1234,x ; $de
+ cpx #$12 ; $e0
+ sbc ($12,x) ; $e1
+ cpx $12 ; $e4
+ sbc $12 ; $e5
+ inc $12 ; $e6
+ inx ; $e8
+ sbc #$12 ; $e9
+ nop ; $ea
+ cpx $1234 ; $ec
+ sbc $1234 ; $ed
+ inc $1234 ; $ee
+ beq LABEL1 ; $f0
+ sbc ($12),y ; $f1
+ sbc $12,x ; $f5
+ inc $12,x ; $f6
+ sed ; $f8
+ sbc $1234,y ; $f9
+ sbc $1234,x ; $fd
+ inc $1234,x ; $fe
+LABEL1:
+ .endscope
+.endif
+
+
+.if (.cpu .bitand CPU_ISET_6502X)
+ .scope
+ ; all "undocumented" 6502 instructions (aka "unintended opcodes")
+ jam ; $02
+ slo ($12,x) ; $03
+ nop $12 ; $04
+ slo $12 ; $07
+ anc #$12 ; $0b
+ nop $1234 ; $0c
+ slo $1234 ; $0f
+ jam ; $12
+ slo ($12),y ; $13
+ nop $12,x ; $14
+ slo $12,y ; $17
+ nop ; $1a
+ slo $1234,y ; $1b
+ nop $1234,x ; $1c
+ slo $1234,x ; $1f
+ jam ; $22
+ rla ($12,x) ; $23
+ rla $12 ; $27
+ anc #$12 ; $2b
+ rla $1234 ; $2f
+ jam ; $32
+ rla ($12),y ; $33
+ nop $12,x ; $34
+ rla $12,y ; $37
+ nop ; $3a
+ rla $1234,y ; $3b
+ nop $1234,x ; $3c
+ rla $1234,x ; $3f
+ jam ; $42
+ sre ($12,x) ; $43
+ nop $12 ; $44
+ sre $12 ; $47
+ alr #$12 ; $4b
+ sre $1234 ; $4f
+ jam ; $52
+ sre ($12),y ; $53
+ nop $12,x ; $54
+ sre $12,y ; $57
+ nop ; $5a
+ sre $1234,y ; $5b
+ nop $1234,x ; $5c
+ sre $1234,x ; $5f
+ jam ; $62
+ rra ($12,x) ; $63
+ nop $12 ; $64
+ rra $12 ; $67
+ arr #$12 ; $6b
+ rra $1234 ; $6f
+ jam ; $72
+ rra ($12),y ; $73
+ nop $12,x ; $74
+ rra $12,y ; $77
+ nop ; $7a
+ rra $1234,y ; $7b
+ nop $1234,x ; $7c
+ rra $1234,x ; $7f
+ nop #$12 ; $80
+ nop #$12 ; $82
+ sax ($12,x) ; $83
+ sax $12 ; $87
+ nop #$12 ; $89
+ ane #$12 ; $8b
+ sax $1234 ; $8f
+ jam ; $92
+ sha ($12),y ; $93
+ sax $12,y ; $97
+ tas $1234,y ; $9b
+ shy $1234,x ; $9c
+ shx $1234,y ; $9e
+ sha $1234,y ; $9f
+ lax ($12,x) ; $a3
+ lax $12 ; $a7
+ lax #$12 ; $ab
+ lax $1234 ; $af
+ jam ; $b2
+ lax ($12),y ; $b3
+ lax $12,y ; $b7
+ las $1234,y ; $bb
+ lax $1234,y ; $bf
+ nop #$12 ; $c2
+ dcp ($12,x) ; $c3
+ dcp $12 ; $c7
+ axs #$12 ; $cb
+ dcp $1234 ; $cf
+ jam ; $d2
+ dcp ($12),y ; $d3
+ nop $12,x ; $d4
+ dcp $12,y ; $d7
+ nop ; $da
+ dcp $1234,y ; $db
+ nop $1234,x ; $dc
+ dcp $1234,x ; $df
+ nop #$12 ; $e2
+ isc ($12,x) ; $e3
+ isc $12 ; $e7
+ sbc #$12 ; $eb
+ isc $1234 ; $ef
+ jam ; $f2
+ isc ($12),y ; $f3
+ nop $12,x ; $f4
+ isc $12,y ; $f7
+ nop ; $fa
+ isc $1234,y ; $fb
+ nop $1234,x ; $fc
+ isc $1234,x ; $ff
+ .endscope
+.endif
+
+
+.if (.cpu .bitand CPU_ISET_6502DTV)
+ .scope
+LABEL:
+ ; opcodes added over 6502 (these are JAM on 6502)
+ bra LABEL ; $12
+ sac #$12 ; $32
+ sir #$12 ; $42
+
+ ; opcodes added over 6502, which work the same as the "illegal" opcodes on 6502
+ nop $12 ; $04
+ nop $1234 ; $0c
+ nop $12,x ; $14
+ nop ; $1a
+ nop $1234,x ; $1c
+ nop $12,x ; $34
+ nop ; $3a
+ nop $1234,x ; $3c
+ nop $12 ; $44
+ nop $12,x ; $54
+ nop ; $5a
+ nop $1234,x ; $5c
+ nop $12 ; $64
+ nop $12,x ; $74
+ nop ; $7a
+ nop $1234,x ; $7c
+ nop #$12 ; $80
+ nop #$12 ; $82
+ nop #$12 ; $89
+ nop #$12 ; $c2
+ nop $12,x ; $d4
+ nop ; $da
+ nop $1234,x ; $dc
+ nop #$12 ; $e2
+ nop $12,x ; $f4
+ nop ; $fa
+ nop $1234,x ; $fc
+
+ anc #$12 ; $0b
+ anc #$12 ; $2b
+
+ rla ($12,x) ; $23
+ rla $12 ; $27
+ rla $1234 ; $2f
+ rla ($12),y ; $33
+ rla $12,y ; $37
+ rla $1234,y ; $3b
+ rla $1234,x ; $3f
+
+ lax ($12,x) ; $a3
+ lax $12 ; $a7
+ lax #$12 ; $ab
+ lax $1234 ; $af
+ lax ($12),y ; $b3
+ lax $12,y ; $b7
+ lax $1234,y ; $bf
+
+ las $1234,y ; $bb
+
+ alr #$12 ; $4b
+
+ arr #$12 ; $6b
+
+ rra ($12,x) ; $63
+ rra $12 ; $67
+ rra $1234 ; $6f
+ rra ($12),y ; $73
+ rra $12,y ; $77
+ rra $1234,y ; $7b
+ rra $1234,x ; $7f
+
+ shy $1234,x ; $9c
+ shx $1234,y ; $9e
+
+ axs #$12 ; $cb
+
+ sbc #$12 ; $eb
+
+ .endscope
+.endif
+
+
+;------------------------------------------------------------------------------
+; The 65c02 is the CMOS re-design of the 6502. It has a few improvements:
+;
+; 65C02 65ce02
+;
+; $04 tsb zp
+; $0c tsb abs16
+; $12 ora (zp) (-> ora (zp), z)
+; $14 trb zp
+; $1a inc
+; $1c trb abs16
+; $32 and (zp) (-> and (zp), z)
+; $34 bit zp, x
+; $3a dec
+; $3c bit abs16, x
+; $52 eor (zp) (-> eor (zp), z)
+; $5a phy
+; $64 stz zp (store z, not 0)
+; $72 adc (zp) (-> adc (zp), z)
+; $74 stz zp, x (store z, not 0)
+; $7a ply
+; $7c jmp (abs16, x)
+; $80 bra rel8
+; $89 bit #imm8
+; $92 sta (zp) (-> sta (zp), z)
+; $9c stz abs16 (store z, not 0)
+; $9e stz abs16, x (store z, not 0)
+; $b2 lda (zp) (-> lda (zp), z)
+; $d2 cmp (zp) (-> cmp (zp), z)
+; $da phx
+; $f2 sbc (zp) (-> sbc (zp), z)
+; $fa plx
+
+; FIXME: currently CPU_ISET_65SC02 and CPU_65SC02 really means "65C02"
+
+; FIXME: should really check for 65C02
+
+.if (.cpu .bitand CPU_ISET_65SC02)
+ .scope
+ ; 65c02 instruction set adds some extra legal instructions to 6502
+ tsb $12 ; $04
+ tsb $1234 ; $0c
+ ;ora ($12) ; $12 FIXME: not working with 4510:ora (zp), z
+ trb $12 ; $14
+ inc a ; $1a
+ trb $1234 ; $1c
+ ;and ($12) ; $32 FIXME: not working with 4510:and (zp), z
+ bit $12,x ; $34
+ dec a ; $3a
+ bit $1234,x ; $3c
+ ;eor ($12) ; $52 FIXME: not working with 4510:eor (zp), z
+ phy ; $5a
+ stz $12 ; $64
+ ;adc ($12) ; $72 FIXME: not working with 4510:adc (zp), z
+ stz $12,x ; $74
+ ply ; $7a
+ jmp ($1234) ; $7c
+LABEL:
+ bra LABEL ; $80
+ bit #$12 ; $89
+ ;sta ($12) ; $92 FIXME: not working with 4510:sta (zp), z
+ stz $1234 ; $9c
+ stz $1234,x ; $9e
+ ;lda ($12) ; $b2 FIXME: not working with 4510:lda (zp), z
+ ;cmp ($12) ; $d2 FIXME: not working with 4510:cmp (zp), z
+ phx ; $da
+ ;sbc ($12) ; $f2 FIXME: not working with 4510:sbc (zp), z
+ plx ; $fa
+ .endscope
+.endif
+
+; FIXME: hack so these opcodes get tested anyway, while 4510 is still quirky
+.if (.cpu .bitand CPU_ISET_65SC02)
+.if (.not .cpu = CPU_4510)
+ ora ($12) ; $12
+ and ($12) ; $32
+ eor ($12) ; $52
+ adc ($12) ; $72
+ sta ($12) ; $92
+ lda ($12) ; $b2
+ cmp ($12) ; $d2
+ sbc ($12) ; $f2
+.endif
+.endif
+
+; TODO: R65C02
+; The R65C02 is a superset of the 65C02. It adds bit manipulation instructions:
+; smbB zp set bit in zp location
+; rmbB zp reset bit in zp location
+; bbsB zp, rel8 branch if bit is set in zp location
+; bbrB zp, rel8 branch if bit is reset in zp location
+
+; FIXME: currently CPU_ISET_65C02 and CPU_65C02 really means "W65C02"
+
+; FIXME: should really check for R65C02
+
+.if (.cpu .bitand CPU_ISET_65C02)
+
+ ; R65C02 instruction set adds some extra legal instructions to 65C02
+ rmb0 $12 ; $07
+ bbr0 $12, LABEL3 ; $0f
+ rmb1 $12 ; $17
+ bbr1 $12, LABEL3 ; $1f
+ rmb2 $12 ; $27
+ bbr2 $12, LABEL3 ; $2f
+ rmb3 $12 ; $37
+ bbr3 $12, LABEL3 ; $3f
+ rmb4 $12 ; $47
+ bbr4 $12, LABEL3 ; $4f
+ rmb5 $12 ; $57
+ bbr5 $12, LABEL3 ; $5f
+ rmb6 $12 ; $67
+ bbr6 $12, LABEL3 ; $6f
+ rmb7 $12 ; $77
+ bbr7 $12, LABEL3 ; $7f
+LABEL3:
+ smb0 $12 ; $87
+ bbs0 $12, LABEL3 ; $8f
+ smb1 $12 ; $97
+ bbs1 $12, LABEL3 ; $9f
+ smb2 $12 ; $a7
+ bbs2 $12, LABEL3 ; $af
+ smb3 $12 ; $b7
+ bbs3 $12, LABEL3 ; $bf
+ smb4 $12 ; $c7
+ bbs4 $12, LABEL3 ; $cf
+ smb5 $12 ; $d7
+ bbs5 $12, LABEL3 ; $df
+ smb6 $12 ; $e7
+ bbs6 $12, LABEL3 ; $ef
+ smb7 $12 ; $f7
+ bbs7 $12, LABEL3 ; $ff
+
+.endif
+
+
+; TODO: W65C02
+; The W65C02 is a superset of the R65C02. It only adds two instructions:
+;
+; $cb wai wait for interrupt
+; $db stp wait for reset
+
+; FIXME: currently CPU_ISET_65C02 and CPU_65C02 really means "W65C02"
+
+; FIXME: should really check for W65C02
+
+.if (.cpu = CPU_65C02)
+ wai ; $cb
+ stp ; $db
+.endif
+
+
+; TODO: 65CE02
+; The 65CE02 is another superset of the R65C02. It has several improvements:
+;
+; $02 cle clear stack extend disable
+; $03 see set stack extend disable
+; $0b tsy transfer stack_ptr_high to Y
+; $12 ora (zp), z
+; $13 lbpl rel16
+; $1b inz increment Z
+; $22 jsr (abs16)
+; $23 jsr (abs16, x)
+; $2b tys transfer Y to stack_ptr_high
+; $32 and (zp), z
+; $33 lbmi rel16
+; $3b dez decrement Z
+; $42 neg negate A
+; $43 asr
+; $44 asr zp
+; $4b taz transfer A to Z
+; $52 eor (zp), z
+; $53 lbvc rel16
+; $54 asr zp, x
+; $5b tab
+; $5c aug "4-byte NOP reserved for future expansion"
+; $62 rtn #imm8
+; $63 lbsr rel16 relative jsr, "branch to subroutine"
+; $64 stz zp store Z
+; $6b tza transfer Z to A
+; $72 adc (zp), z
+; $73 lbvs rel16
+; $74 stz zp, x store Z
+; $7b tba
+; $82 sta (off8, s), y
+; $83 lbra rel16 relative jmp
+; $8b sty abs16, x
+; $92 sta (zp), z
+; $93 lbcc rel16
+; $9b stx abs16, y
+; $9c stz abs16 store Z
+; $9e stz abs16, x store Z
+; $a3 ldz #imm8
+; $ab ldz abs16
+; $b2 lda (zp), z
+; $b3 lbcs rel16
+; $bb ldz abs16, x
+; $c2 cpz #imm8
+; $c3 dew zp
+; $cb asw abs16
+; $d2 cmp (zp), z
+; $d3 lbne rel16
+; $d4 cpz zp
+; $db phz push Z
+; $dc cpz abs16
+; $e2 lda (off8, s), y
+; $e3 inw zp
+; $eb row abs16
+; $f2 sbc (zp), z
+; $f3 lbeq rel16
+; $f4 phw #imm16
+; $fb plz pull Z
+; $fc phw abs16
+
+; FIXME: should really check for 65CE02
+
+.if (.cpu .bitand CPU_ISET_4510)
+ .scope
+ ; 65CE02 adds the following:
+ cle ; $02
+ see ; $03
+ tsy ; $0b
+ ora ($12), z ; $12 (ora (zp) on 65C02)
+ lbpl $1234 ; $13
+ inz ; $1b
+ jsr ($1234) ; $22
+ jsr ($1234,x) ; $23
+ tys ; $2b
+ and ($12), z ; $32 (and (zp) on 65C02)
+ lbmi $1234 ; $33
+ dez ; $3b
+ neg ; $42
+ asr a ; $43
+ asr $12 ; $44
+ taz ; $4b
+ lbvc $1234 ; $53
+ asr $12,x ; $54
+ tab ; $5b
+ ;aug ; $5c FIXME: implement in assembler
+ rtn #$12 ; $62
+ bsr $1234 ; $63
+ stz $12 ; $64 (stores 0 on 65C02)
+ tza ; $6b
+ adc ($12), z ; $72 (adc (zp) on 65C02)
+ lbvs $1234 ; $73
+ stz $12, x ; $74 (stores 0 on 65C02)
+ tba ; $7b
+ sta ($12,s),y ; $82
+ lbra $1234 ; $83
+ sty $1234,x ; $8b
+ lbcc $1234 ; $93
+ sta ($12), z ; $92 (sta (zp) on 65C02)
+ stx $1234,y ; $9b
+ stz $1234 ; $9c (stores 0 on 65C02)
+ ldz #$12 ; $a3
+ ldz $1234 ; $ab
+ lda ($12), z ; $b2 (lda (zp) on 65C02)
+ lbcs $1234 ; $b3
+ ldz $1234,x ; $bb
+ cpz #$12 ; $c2
+ dew $12 ; $c3
+ cmp ($12), z ; $d2 (cmp ($12) on 65C02)
+ lbne $1234 ; $d3
+ cpz $12 ; $d4
+ cpz $1234 ; $dc
+ lda ($12,s),y ; $e2
+ inw $12 ; $e3
+ row $1234 ; $eb
+ sbc ($12), z ; $f2 (sbc (zp) on 65C02)
+ lbeq $1234 ; $f3
+ phw #$1234 ; $f4
+ plz ; $fb
+ phw $1234 ; $fc
+
+ .endscope
+.endif
+
+
+; The 4510 is a superset of the 65CE02. Opcode 5c (originally a "4-byte NOP
+; reserved for future expansion") has been changed to the "map" instruction,
+; now using implied addressing.
+;
+; $5c map
+; $cb asw abs
+; $db phz
+
+.if (.cpu .bitand CPU_ISET_4510)
+ .scope
+
+ ; added to 65CE02
+ map ; $5c ("4-byte NOP reserved for future expansion" on 65CE02)
+ asw $1234 ; $cb (wai on W65C02)
+ phz ; $db (stp on W65C02)
+ eom ; $ea "end of mapping" - but really just a NOP
+
+ .endscope
+.endif
+
+
+; The 45GS02 instruction set extends the 4510 instruction set using prefix bytes.
+; Therefore, the "normal" opcode table is the same as for the 4510 cpu
+
+.if (.cpu .bitand CPU_ISET_45GS02)
+ .scope
+
+ orq $12 ; $42 $42 $05
+ aslq $12 ; $42 $42 $06
+ aslq ; $42 $42 $0a
+ orq $1234 ; $42 $42 $0d
+ aslq $1234 ; $42 $42 $0e
+ orq ($12) ; $42 $42 $12
+ aslq $12,x ; $42 $42 $16
+ inq ; $42 $42 $1a
+ aslq $1234,x ; $42 $42 $1e
+ bitq $12 ; $42 $42 $24
+ andq $12 ; $42 $42 $25
+ rolq $12 ; $42 $42 $26
+ rolq ; $42 $42 $2a
+ bitq $1234 ; $42 $42 $2c
+ andq $1234 ; $42 $42 $2d
+ rolq $1234 ; $42 $42 $2e
+ andq ($12) ; $42 $42 $32
+ rolq $12, x ; $42 $42 $36
+ deq ; $42 $42 $3a
+ rolq $1234, x ; $42 $42 $3e
+ asrq ; $42 $42 $43
+ asrq $12 ; $42 $42 $44
+ eorq $12 ; $42 $42 $45
+ lsrq $12 ; $42 $42 $46
+ lsrq ; $42 $42 $4a
+ eorq $1234 ; $42 $42 $4d
+ lsrq $1234 ; $42 $42 $4e
+ eorq ($12) ; $42 $42 $52
+ asrq $12, x ; $42 $42 $54
+ lsrq $12, x ; $42 $42 $56
+ lsrq $1234, x ; $42 $42 $5e
+ adcq $12 ; $42 $42 $65
+ rorq $12 ; $42 $42 $66
+ rorq ; $42 $42 $6a
+ adcq $1234 ; $42 $42 $6d
+ rorq $1234 ; $42 $42 $6e
+ adcq ($12) ; $42 $42 $72
+ rorq $12, x ; $42 $42 $76
+ rorq $1234, x ; $42 $42 $7e
+ stq $12 ; $42 $42 $85
+ stq $1234 ; $42 $42 $8d
+ stq ($12) ; $42 $42 $92
+ ldq $12 ; $42 $42 $a5
+ ldq $1234 ; $42 $42 $ad
+ ldq ($12), z ; $42 $42 $b2
+ cmpq $12 ; $42 $42 $c5
+ deq $12 ; $42 $42 $c6
+ cmpq $1234 ; $42 $42 $cd
+ deq $1234 ; $42 $42 $ce
+ cmpq ($12) ; $42 $42 $d2
+ deq $12, x ; $42 $42 $d6
+ deq $1234, x ; $42 $42 $de
+ sbcq $12 ; $42 $42 $e5
+ inq $12 ; $42 $42 $e6
+ sbcq $1234 ; $42 $42 $ed
+ inq $1234 ; $42 $42 $ee
+ sbcq ($12) ; $42 $42 $f2
+ inq $12, x ; $42 $42 $f6
+ inq $1234, x ; $42 $42 $fe
+
+ ora [$12], z ; $ea $12
+ and [$12], z ; $ea $32
+ eor [$12], z ; $ea $52
+ adc [$12], z ; $ea $72
+ sta [$12], z ; $ea $92
+ lda [$12], z ; $ea $b2
+ cmp [$12], z ; $ea $d2
+ sbc [$12], z ; $ea $f2
+
+ orq [$12] ; $42 $42 $ea $12
+ andq [$12] ; $42 $42 $ea $32
+ eorq [$12] ; $42 $42 $ea $52
+ adcq [$12] ; $42 $42 $ea $72
+ stq [$12] ; $42 $42 $ea $92
+ ldq [$12], z ; $42 $42 $ea $b2
+ cmpq [$12] ; $42 $42 $ea $d2
+ sbcq [$12] ; $42 $42 $ea $f2
+
+ .endscope
+.endif
+
+
+; The HUC6280 is a superset of the R65C02. It adds some other instructions:
+
+.if (.cpu .bitand CPU_ISET_HUC6280)
+ .scope
+
+ ; added to R65C02
+ sxy ; $02
+ st0 #$12 ; $03
+ st1 #$12 ; $13
+ sax ; $22
+ st2 #$12 ; $23
+ say ; $42
+ tma #$10 ; $43
+ bsr LABEL ; $44
+ tam #$12 ; $53
+ csl ; $54
+ cla ; $62
+ tii $1234, $5678, $9abc ; $73
+LABEL:
+ clx ; $82
+ tst #$12, $34 ; $83
+ clx ; $82
+ tst #$12, $34 ; $83
+ tst #$12, $3456 ; $93
+ tst #$12, $34, x ; $a3
+ tst #$12, $3456, x ; $b3
+ cly ; $c2
+ tdd $1234, $5678, $9abc ; $c3
+ tin $1234, $5678, $9abc ; $d3
+ csh ; $d4
+ tia $1234, $5678, $9abc ; $e3
+ tai $1234, $5678, $9abc ; $f3
+ set ; $f4
+
+ .endscope
+.endif
+
+
+.if (.cpu .bitand CPU_ISET_M740)
+ .scope
+ ; Mitsubishi M740 - adds new instructions to 65SC02 (but also removes some)
+
+ jsr ($12) ; $02
+ bbs0 a, LABEL ; $03
+ bbs0 $12, LABEL ; $07
+ seb0 a ; $0b
+ seb0 $12 ; $0f
+ bbc0 a, LABEL ; $13
+ bbc0 $12, LABEL ; $17
+ clb0 a ; $1b
+ clb0 $12 ; $1f
+ jsr $ff12 ; $22
+ bbs1 a, LABEL ; $23
+ bbs1 $12, LABEL ; $27
+ seb1 a ; $2b
+ seb1 $12 ; $2f
+ bbc1 a, LABEL ; $33
+ bbc1 $12, LABEL ; $37
+ clb1 a ; $3b
+ clb1 $12 ; $3f
+ stp ; $42
+ bbs2 a, LABEL ; $43
+ com $12 ; $44
+ bbs2 $12, LABEL ; $47
+ seb2 a ; $4b
+ seb2 $12 ; $4f
+ bbc2 a, LABEL ; $53
+ bbc2 $12, LABEL ; $57
+ clb2 a ; $5b
+ clb2 $12 ; $5f
+ bbs3 a, LABEL ; $63
+ bbs3 $12, LABEL ; $67
+ seb3 a ; $6b
+ seb3 $12 ; $6f
+ bbc3 a, LABEL ; $73
+ bbc3 $12, LABEL ; $77
+ clb3 a ; $7b
+ clb3 $12 ; $7f
+LABEL:
+ rrf $12 ; $82
+ bbs4 a, LABEL ; $83
+ bbs4 $12, LABEL ; $87
+ seb4 a ; $8b
+ seb4 $12 ; $8f
+ bbc4 a, LABEL ; $93
+ bbc4 $12, LABEL ; $97
+ clb4 a ; $9b
+ clb4 $12 ; $9f
+ bbs5 a, LABEL ; $a3
+ bbs5 $12, LABEL ; $a7
+ seb5 a ; $ab
+ seb5 $12 ; $af
+ bbc5 a, LABEL ; $b3
+ bbc5 $12, LABEL ; $b7
+ clb5 a ; $bb
+ clb5 $12 ; $bf
+ slw ; $c2
+ bbs6 a, LABEL ; $c3
+ bbs6 $12, LABEL ; $c7
+ seb6 a ; $cb
+ seb6 $12 ; $cf
+ bbc6 a, LABEL ; $d3
+ bbc6 $12, LABEL ; $d7
+ clb6 a ; $db
+ clb6 $12 ; $df
+ fst ; $e2
+ bbs7 a, LABEL ; $e3
+ bbs7 $12, LABEL ; $e7
+ seb7 a ; $eb
+ seb7 $12 ; $ef
+ bbc7 a, LABEL ; $f3
+ bbc7 $12, LABEL ; $f7
+ clb7 a ; $fb
+ clb7 $12 ; $ff
+
+ ; replaced from 65SC02
+ clt ; $12
+ set ; $32
+ ldm $12, #$34 ; $3c
+ tst $12 ; $64
+
+ ; removed from 65SC02 (replaced by new)
+ ; ora ($12) ; $12
+ ; and ($12) ; $32
+ ; bit $1234,x ; $3c
+ ; stz $12 ; $64
+
+ ; removed from 65SC02
+ ; tsb $12 ; $04
+ ; tsb $1234 ; $0c
+ ; trb $12 ; $14
+ ; trb $1234 ; $1c
+ ; bit $12,y ; $34
+ ; eor ($12) ; $52
+ ; phy ; $5a
+ ; adc ($12) ; $72
+ ; stz $12,y ; $74
+ ; ply ; $7a
+ ; jmp ($1234) ; $7c
+ ; bit #$12 ; $89
+ ; sta ($12) ; $92
+ ; stz $1234 ; $9c
+ ; stz $1234,x ; $9e
+ ; cmp ($12) ; $d2
+ ; phx ; $da
+ ; sbc ($12) ; $f2
+ ; plx ; $fa
+
+ .endscope
+.endif
+
diff --git a/test/asm/cpudetect/cpudetect.s b/test/asm/cpudetect/cpudetect.s
index 6ee07ae3c..545e2fa56 100644
--- a/test/asm/cpudetect/cpudetect.s
+++ b/test/asm/cpudetect/cpudetect.s
@@ -28,10 +28,18 @@
taz
.endif
+.ifp45GS02
+ orq $1234
+.endif
+
.ifpdtv
sac #$00
.endif
+.ifpm740
+ jsr $ff12
+.endif
+
; step 2: check for bitwise compatibility of instructions sets
; (made verbose for better reading with hexdump/hd(1))
@@ -72,10 +80,23 @@
.byte 0,"CPU_ISET_4510"
.endif
+.if (.cpu .bitand CPU_ISET_45GS02)
+ .byte 0,"CPU_ISET_45GS02"
+.endif
+
.if (.cpu .bitand CPU_ISET_6502DTV)
.byte 0,"CPU_ISET_6502DTV"
.endif
+.if (.cpu .bitand CPU_ISET_M740)
+ .byte 0,"CPU_ISET_M740"
+.endif
+
+; FIXME: something with 65816 is quirky
+.if (.not .cpu .bitand CPU_ISET_65816)
+ .include "allinst.inc"
+.endif
+
; step 3: switch through all supported cpus to verify the pseudo-op is there
@@ -85,4 +106,6 @@
.pc02
.p816
.p4510
+.p45GS02
.pdtv
+.pm740
diff --git a/test/asm/cpudetect/m740-cpudetect.ref b/test/asm/cpudetect/m740-cpudetect.ref
new file mode 100644
index 000000000..7788f3ed9
Binary files /dev/null and b/test/asm/cpudetect/m740-cpudetect.ref differ
diff --git a/test/asm/err/Makefile b/test/asm/err/Makefile
index 6d2430d34..c1a8285e4 100644
--- a/test/asm/err/Makefile
+++ b/test/asm/err/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the tests that MUST NOT compile
ifneq ($(shell echo),)
diff --git a/test/asm/err/bug505.s b/test/asm/err/bug505.s
new file mode 100644
index 000000000..8cb0e2f18
--- /dev/null
+++ b/test/asm/err/bug505.s
@@ -0,0 +1,28 @@
+; Test for #505 taken from the issue
+; Redefining a variable symbol "reopens" the old name space for cheap locals
+; Behavior should be: First definition of a variable symbol opens a new
+; scope for cheap locals, redefinitions of the same symbols do not.
+
+;this starts a new scope for cheap local lables
+SomeSymbol .set 4
+
+ jmp @CheapLocal1
+
+@CheapLocal0:
+
+ .byte $8b
+
+CheapLocalScopeBreaker0:
+
+CheapLocalScopeBreaker1:
+
+CheapLocalScopeBreaker2:
+
+CheapLocalScopeBreaker3:
+
+;this continues the same cheap scope as before, regardless of the many global labels in between
+SomeSymbol .set 5
+
+@CheapLocal1:
+
+ lda @CheapLocal0
diff --git a/test/asm/listing/Makefile b/test/asm/listing/Makefile
index 23aa3969c..4321d3b95 100644
--- a/test/asm/listing/Makefile
+++ b/test/asm/listing/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the assembler regression tests
ifneq ($(shell echo),)
diff --git a/test/asm/misc/Makefile b/test/asm/misc/Makefile
index 5a9d4f3ef..1b2305cda 100644
--- a/test/asm/misc/Makefile
+++ b/test/asm/misc/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the remaining asm tests that need special care in one way or another
ifneq ($(shell echo),)
diff --git a/test/asm/opcodes/45GS02-opcodes.ref b/test/asm/opcodes/45GS02-opcodes.ref
new file mode 100644
index 000000000..a4a78d46c
Binary files /dev/null and b/test/asm/opcodes/45GS02-opcodes.ref differ
diff --git a/test/asm/opcodes/45GS02-opcodes.s b/test/asm/opcodes/45GS02-opcodes.s
new file mode 100644
index 000000000..6d42b80c4
--- /dev/null
+++ b/test/asm/opcodes/45GS02-opcodes.s
@@ -0,0 +1,377 @@
+.setcpu "45GS02"
+
+ brk
+ ora ($05,x)
+ cle
+ see
+ tsb $02
+ ora $02
+ asl $02
+ rmb0 $02
+ php
+ ora #$01
+ asl
+ tsy
+ tsb $1234
+ ora $1234
+ asl $1234
+ bbr0 $02,*+$34
+
+ bpl *+$32
+ ora ($06),y
+ ora ($07),z
+ lbpl *+$3133 ; bpl *+$3133
+ trb $02
+ ora $03,x
+ asl $03,x
+ rmb1 $02
+ clc
+ ora $1456,y
+ inc
+ inz
+ trb $1234
+ ora $1345,x
+ asl $1345,x
+ bbr1 $02,*+$34
+
+ jsr $1234
+ and ($05,x)
+ jsr ($2345)
+ jsr ($2456,x)
+ bit $02
+ and $02
+ rol $02
+ rmb2 $02
+ plp
+ and #$01
+ rol
+ tys
+ bit $1234
+ and $1234
+ rol $1234
+ bbr2 $02,*+$34
+
+ bmi *+$32
+ and ($06),y
+ and ($07),z
+ lbmi *+$3133 ; bmi *+$3133
+ bit $03,x
+ and $03,x
+ rol $03,x
+ rmb3 $02
+ sec
+ and $1456,y
+ dec
+ dez
+ bit $1345,x
+ and $1345,x
+ rol $1345,x
+ bbr3 $02,*+$34
+
+ rti
+ eor ($05,x)
+ neg
+ asr
+ asr $02
+ eor $02
+ lsr $02
+ rmb4 $02
+ pha
+ eor #$01
+ lsr
+ taz
+ jmp $1234
+ eor $1234
+ lsr $1234
+ bbr4 $02,*+$34
+
+ bvc *+$32
+ eor ($06),y
+ eor ($07),z
+ lbvc *+$3133 ; bvc *+$3133
+ asr $03,x
+ eor $03,x
+ lsr $03,x
+ rmb5 $02
+ cli
+ eor $1456,y
+ phy
+ tab
+ map
+ eor $1345,x
+ lsr $1345,x
+ bbr5 $02,*+$34
+
+ rts
+ adc ($05,x)
+ rtn #$09
+ bsr *+$3133
+ stz $02
+ adc $02
+ ror $02
+ rmb6 $02
+ pla
+ adc #$01
+ ror
+ tza
+ jmp ($2345)
+ adc $1234
+ ror $1234
+ bbr6 $02,*+$34
+
+ bvs *+$32
+ adc ($06),y
+ adc ($07),z
+ lbvs *+$3133 ; bvs *+$3133
+ stz $03,x
+ adc $03,x
+ ror $03,x
+ rmb7 $02
+ sei
+ adc $1456,y
+ ply
+ tba
+ jmp ($2456,x)
+ adc $1345,x
+ ror $1345,x
+ bbr7 $02,*+$34
+
+ bra *+$32
+ sta ($05,x)
+ sta ($0f,s),y
+ sta ($0f,sp),y
+ lbra *+$3133 ; bra *+$3133
+ sty $02
+ sta $02
+ stx $02
+ smb0 $02
+ dey
+ bit #$01
+ txa
+ sty $1345,x
+ sty $1234
+ sta $1234
+ stx $1234
+ bbs0 $02,*+$34
+
+ bcc *+$32
+ sta ($06),y
+ sta ($07),z
+ lbcc *+$3133 ; bcc *+$3133
+ sty $03,x
+ sta $03,x
+ stx $04,y
+ smb1 $02
+ tya
+ sta $1456,y
+ txs
+ stx $1456,y
+ stz $1234
+ sta $1345,x
+ stz $1345,x
+ bbs1 $02,*+$34
+
+ ldy #$01
+ lda ($05,x)
+ ldx #$01
+ ldz #$01
+ ldy $02
+ lda $02
+ ldx $02
+ smb2 $02
+ tay
+ lda #$01
+ tax
+ ldz $1234
+ ldy $1234
+ lda $1234
+ ldx $1234
+ bbs2 $02,*+$34
+
+ bcs *+$32
+ lda ($06),y
+ lda ($07),z
+ lbcs *+$3133 ; bcs *+$3133
+ ldy $03,x
+ lda $03,x
+ ldx $04,y
+ smb3 $02
+ clv
+ lda $1456,y
+ tsx
+ ldz $1345,x
+ ldy $1345,x
+ lda $1345,x
+ ldx $1456,y
+ bbs3 $02,*+$34
+
+ cpy #$01
+ cmp ($05,x)
+ cpz #$01
+ dew $02
+ cpy $02
+ cmp $02
+ dec $02
+ smb4 $02
+ iny
+ cmp #$01
+ dex
+ asw $1234
+ cpy $1234
+ cmp $1234
+ dec $1234
+ bbs4 $02,*+$34
+
+ bne *+$32
+ cmp ($06),y
+ cmp ($07),z
+ lbne *+$3133 ; bne *+$3133
+ cpz $02
+ cmp $03,x
+ dec $03,x
+ smb5 $02
+ cld
+ cmp $1456,y
+ phx
+ phz
+ cpz $1234
+ cmp $1345,x
+ dec $1345,x
+ bbs5 $02,*+$34
+
+ cpx #$01
+ sbc ($05,x)
+ lda ($0f,s),y
+ lda ($0f,sp),y
+ inw $02
+ cpx $02
+ sbc $02
+ inc $02
+ smb6 $02
+ inx
+ sbc #$01
+ eom
+ nop
+ row $1234
+ cpx $1234
+ sbc $1234
+ inc $1234
+ bbs6 $02,*+$34
+
+ beq *+$32
+ sbc ($06),y
+ sbc ($07),z
+ lbeq *+$3133 ; beq *+$3133
+ phd #$089a
+ phw #$089a
+ sbc $03,x
+ inc $03,x
+ smb7 $02
+ sed
+ sbc $1456,y
+ plx
+ plz
+ phd $1234
+ phw $1234
+ sbc $1345,x
+ inc $1345,x
+ bbs7 $02,*+$34
+
+ adc [$12],z
+
+ adcq $12
+ adcq $3456
+ adcq ($78)
+ adcq [$9a]
+
+ and [$12],z
+
+ andq $12
+ andq $3456
+ andq ($78)
+ andq [$9a]
+
+ aslq $12
+ aslq
+ aslq $3456
+ aslq $78,x
+ aslq $9abc,x
+
+ asrq
+ asrq $12
+ asrq $34,x
+
+ bitq $12
+ bitq $3456
+
+ cmp [$12],z
+
+ cmpq $12
+ cmpq $3456
+ cmpq ($78)
+ cmpq [$9a]
+
+ deq
+ deq $12
+ deq $3456
+ deq $78,x
+ deq $9abc,x
+
+ eor [$12],z
+
+ eorq $12
+ eorq $3456
+ eorq ($78)
+ eorq [$9a]
+
+ inq
+ inq $12
+ inq $3456
+ inq $78,x
+ inq $9abc,x
+
+ lda [$12],z
+
+ ldq $12
+ ldq $3456
+ ldq ($78),z
+ ldq [$9a],z
+
+ lsrq $12
+ lsrq
+ lsrq $3456
+ lsrq $78,x
+ lsrq $9abc,x
+
+ ora [$12],z
+
+ orq $12
+ orq $3456
+ orq ($78)
+ orq [$9a]
+
+ rolq $12
+ rolq
+ rolq $3456
+ rolq $78,x
+ rolq $9abc,x
+
+ rorq $12
+ rorq
+ rorq $3456
+ rorq $78,x
+ rorq $9abc,x
+
+ sbc [$12],z
+
+ sbcq $12
+ sbcq $3456
+ sbcq ($78)
+ sbcq [$9a]
+
+ sta [$12],z ; EA 92 12
+
+ stq $12
+ stq $3456
+ stq ($78)
+ stq [$9a]
diff --git a/test/asm/opcodes/Makefile b/test/asm/opcodes/Makefile
index 00be96d91..70dd41c06 100644
--- a/test/asm/opcodes/Makefile
+++ b/test/asm/opcodes/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the assembler regression tests
ifneq ($(shell echo),)
diff --git a/test/asm/opcodes/m740-opcodes.ref b/test/asm/opcodes/m740-opcodes.ref
new file mode 100644
index 000000000..b3cffc9b6
Binary files /dev/null and b/test/asm/opcodes/m740-opcodes.ref differ
diff --git a/test/asm/opcodes/m740-opcodes.s b/test/asm/opcodes/m740-opcodes.s
index 3ea91cf5f..e4f8562cc 100644
--- a/test/asm/opcodes/m740-opcodes.s
+++ b/test/asm/opcodes/m740-opcodes.s
@@ -1,260 +1,565 @@
-.setcpu "65C02"
-; copy of 65c02, comments note changes to the m740 according to
-; http://documentation.renesas.com/doc/products/mpumcu/rej09b0322_740sm.pdf
+; da65 V2.19 - Git 89651fd8b
+; Created: 2025-06-16 20:10:42
+; Input file: testfile
+; Page: 1
- brk
- ora ($12,x)
- .byte $02,$00,$00 ; jsr zp,ind
- .byte $03,$00,$00 ; bbs 0,a
- tsb $12 ; .byte $04
- ora $12
- asl $12
- rmb0 $12 ; bbs 0,zp
- php
- ora #$12
- asl a
- .byte $0B,$00,$00 ; seb 0,a
- tsb $3456 ; .byte $0c
- ora $3456
- asl $3456
- bbr0 $12,*+122 ; seb 0,zp
- bpl *+122
- ora ($12),y
- ora ($12) ; clt
- .byte $13,$00,$00 ; bbc 0,a
- trb $12 ; .byte $14
- ora $12,x
- asl $12,x
- rmb1 $12 ; bbc 0,zp
- clc
- ora $3456,y
- inc a
- .byte $1B,$00,$00 ; clb 0,a
- trb $3456 ; .byte $1c
- ora $3456,x
- asl $3456,x
- bbr1 $12,*+122 ; clb 0,zp
- jsr $3456
- and ($12,x)
- .byte $22,$00,$00 ; jsr c_sp
- .byte $23,$00,$00 ; bbs 1,a
- bit $12
- and $12
- rol $12
- rmb2 $12 ; bbs 1,zp
- plp
- and #$12
- rol a
- .byte $2B,$00,$00 ; seb 1,a
- bit $3456
- and $3456
- rol $3456
- bbr2 $12,*+122 ; seb 1,zp
- bmi *+122
- and ($12),y
- and ($12) ; set
- .byte $33,$00,$00 ; bbc 1,a
- bit $12,x ; .byte $34
- and $12,x
- rol $12,x
- rmb3 $12 ; bbc 1,zp
- sec
- and $3456,y
- dec a
- .byte $3B,$00,$00 ; clb 1,a
- bit $3456,x ; ldm zp
- and $3456,x
- rol $3456,x
- bbr3 $12,*+122 ; clb 1,zp
- rti
- eor ($12,x)
- .byte $42,$00,$00 ; stp
- .byte $43,$00,$00 ; bbs 2,a
- .byte $44,$00,$00 ; com zp
- eor $12
- lsr $12
- rmb4 $12 ; bbs 2,zp
- pha
- eor #$12
- lsr a
- .byte $4B,$00,$00 ; seb 2,a
- jmp $3456
- eor $3456
- lsr $3456
- bbr4 $12,*+122 ; seb 2,zp
- bvc *+122
- eor ($12),y
- eor ($12) ; .byte $52
- .byte $53,$00,$00 ; bbc 2,a
- .byte $54,$00,$00
- eor $12,x
- lsr $12,x
- rmb5 $12 ; bbc 2,zp
- cli
- eor $3456,y
- phy
- .byte $5B,$00,$00 ; clb 2,a
- .byte $5C,$00,$00
- eor $3456,x
- lsr $3456,x
- bbr5 $12,*+122 ; clb 2,zp
- rts
- adc ($12,x)
- .byte $62,$00,$00 ; mul zp,x
- .byte $63,$00,$00 ; bbs 3,a
- stz $12 ; tst zp
- adc $12
- ror $12
- rmb6 $12 ; bbs 3,zp
- pla
- adc #$12
- ror a
- .byte $6B,$00,$00 ; seb 3,a
- jmp ($3456)
- adc $3456
- ror $3456
- bbr6 $12,*+122 ; seb 3,zp
- bvs *+122
- adc ($12),y
- adc ($12) ; .byte $72
- .byte $73,$00,$00 ; bbc 3,a
- stz $12,x ; .byte $74
- adc $12,x
- ror $12,x
- rmb7 $12 ; bbc 3,zp
- sei
- adc $3456,y
- ply
- .byte $7B,$00,$00 ; clb 3,a
- jmp ($3456,x) ; .byte $7c
- adc $3456,x
- ror $3456,x
- bbr7 $12,*+122 ; clb 3,zp
- bra *+122
- sta ($12,x)
- .byte $82,$00,$00 ; rrf zp
- .byte $83,$00,$00 ; bbs 4,a
- sty $12
- sta $12
- stx $12
- smb0 $12 ; bbs 4,zp
- dey
- bit #$12
- txa
- .byte $8B,$00,$00 ; seb 4,a
- sty $3456
- sta $3456
- stx $3456
- bbs0 $12,*+122 ; seb 4,zp
- bcc *+122
- sta ($12),y
- sta ($12) ; .byte $92
- .byte $93,$00,$00 ; bbc 4,a
- sty $12,x
- sta $12,x
- stx $12,y
- smb1 $12 ; bbc 4,zp
- tya
- sta $3456,y
- txs
- .byte $9B,$00,$00 ; clb 4,a
- stz $3456 ; .byte $9c
- sta $3456,x
- stz $3456,x ; .byte $9e
- bbs1 $12,*+122 ; clb 4,zp
- ldy #$12
- lda ($12,x)
- ldx #$12
- .byte $A3,$00,$00 ; bbs 5,a
- ldy $12
- lda $12
- ldx $12
- smb2 $12 ; bbs 5,zp
- tay
- lda #$12
- tax
- .byte $AB,$00,$00 ; seb 5,a
- ldy $3456
- lda $3456
- ldx $3456
- bbs2 $12,*+122 ; seb 5,zp
- bcs *+122
- lda ($12),y
- lda ($12) ; .byte $b2
- .byte $B3,$00,$00 ; bbc 5,a
- ldy $12,x
- lda $12,x
- ldx $12,y
- smb3 $12 ; bbc 5,zp
- clv
- lda $3456,y
- tsx
- .byte $BB,$00,$00 ; clb 5,a
- ldy $3456,x
- lda $3456,x
- ldx $3456,y
- bbs3 $12,*+122 ; clb 5,zp
- cpy #$12
- cmp ($12,x)
- .byte $C2,$00,$00 ; wit
- .byte $C3,$00,$00 ; bbs 6,a
- cpy $12
- cmp $12
- dec $12
- smb4 $12 ; bbs 6,zp
- iny
- cmp #$12
- dex
- .byte $CB,$00,$00 ; seb 6,a
- cpy $3456
- cmp $3456
- dec $3456
- bbs4 $12,*+122 ; seb 6,zp
- bne *+122
- cmp ($12),y
- cmp ($12) ; .byte $d2
- .byte $D3,$00,$00 ; bbc 6,a
- .byte $D4,$00,$00
- cmp $12,x
- dec $12,x
- smb5 $12 ; bbc 6,zp
- cld
- cmp $3456,y
- phx
- .byte $DB,$00,$00 ; clb 6,a
- .byte $DC,$00,$00
- cmp $3456,x
- dec $3456,x
- bbs5 $12,*+122 ; clb 6,zp
- cpx #$12
- sbc ($12,x)
- .byte $E2,$00,$00 ; div zp,x
- .byte $E3,$00,$00 ; bbs 7,a
- cpx $12
- sbc $12
- inc $12
- smb6 $12 ; bbs 7,zp
- inx
- sbc #$12
- nop
- .byte $EB,$00,$00 ; seb 7,a
- cpx $3456
- sbc $3456
- inc $3456
- bbs6 $12,*+122 ; seb 7,zp
- beq *+122
- sbc ($12),y
- sbc ($12) ; .byte $f2
- .byte $F3,$00,$00 ; bbc 7,a
- .byte $F4,$00,$00
- sbc $12,x
- inc $12,x
- smb7 $12 ; bbc 7,zp
- sed
- sbc $3456,y
- plx
- .byte $FB,$00,$00 ; clb 7,a
- .byte $FC,$00,$00
- sbc $3456,x
- inc $3456,x
- bbs7 $12,*+122 ; clb 7,zp
+
+ .setcpu "m740"
+
+L000C := $000C
+L040C := $040C
+LFF0C := $FF0C
+ brk
+ .byte $0C
+ .byte $04
+ ora (L000C,x)
+ .byte $04
+ jsr (L000C)
+
+ .byte $04
+ bbs0 a, L8018
+ .byte $04
+ .byte $04
+ .byte $0C
+ .byte $04
+ ora L000C
+ .byte $04
+ asl L000C
+ .byte $04
+ bbs0 L000C, L801C
+L8018: php
+ .byte $0C
+ .byte $04
+ .byte $09
+L801C: .byte $0C
+ .byte $04
+ asl a
+ .byte $0C
+ .byte $04
+ seb0 a
+ .byte $0C
+ .byte $04
+ .byte $0C
+ .byte $0C
+ .byte $04
+ ora L040C
+ asl L040C
+ seb0 L000C
+ .byte $04
+ bpl L803E
+ .byte $04
+ ora (L000C),y
+ .byte $04
+ clt
+ .byte $0C
+ .byte $04
+ bbc0 a, L8048
+ .byte $04
+ .byte $14
+ .byte $0C
+L803E: .byte $04
+ ora L000C,x
+ .byte $04
+ asl L000C,x
+ .byte $04
+ bbc0 L000C, L804C
+L8048: clc
+ .byte $0C
+ .byte $04
+ .byte $19
+L804C: .byte $0C
+ .byte $04
+ inc a
+ .byte $0C
+ .byte $04
+ clb0 a
+ .byte $0C
+ .byte $04
+ .byte $1C
+ .byte $0C
+ .byte $04
+ ora L040C,x
+ asl L040C,x
+ clb0 L000C
+ .byte $04
+ jsr L040C
+ and (L000C,x)
+ .byte $04
+ jsr LFF0C
+ .byte $04
+ bbs1 a, L8078
+ .byte $04
+ bit L000C
+ .byte $04
+ and L000C
+ .byte $04
+ rol L000C
+ .byte $04
+ bbs1 L000C, L807C
+L8078: plp
+ .byte $0C
+ .byte $04
+ .byte $29
+L807C: .byte $0C
+ .byte $04
+ rol a
+ .byte $0C
+ .byte $04
+ seb1 a
+ .byte $0C
+ .byte $04
+ bit L040C
+ and L040C
+ rol L040C
+ seb1 L000C
+ .byte $04
+ bmi L809E
+ .byte $04
+ and (L000C),y
+ .byte $04
+ set
+ .byte $0C
+ .byte $04
+ bbc1 a, L80A8
+ .byte $04
+ .byte $34
+ .byte $0C
+L809E: .byte $04
+ and L000C,x
+ .byte $04
+ rol L000C,x
+ .byte $04
+ bbc1 L000C, L80AC
+L80A8: sec
+ .byte $0C
+ .byte $04
+ .byte $39
+L80AC: .byte $0C
+ .byte $04
+ dec a
+ .byte $0C
+ .byte $04
+ clb1 a
+ .byte $0C
+ .byte $04
+ ldm L000C, #$04
+ and L040C,x
+ rol L040C,x
+ clb1 L000C
+ .byte $04
+ rti
+
+ .byte $0C
+ .byte $04
+ eor (L000C,x)
+ .byte $04
+ stp
+ .byte $0C
+ .byte $04
+ bbs2 a, L80D8
+ .byte $04
+ com L000C
+ .byte $04
+ eor L000C
+ .byte $04
+ lsr L000C
+ .byte $04
+ bbs2 L000C, L80DC
+L80D8: pha
+ .byte $0C
+ .byte $04
+ .byte $49
+L80DC: .byte $0C
+ .byte $04
+ lsr a
+ .byte $0C
+ .byte $04
+ seb2 a
+ .byte $0C
+ .byte $04
+ jmp L040C
+
+ eor L040C
+ lsr L040C
+ seb2 L000C
+ .byte $04
+ bvc L80FE
+ .byte $04
+ eor (L000C),y
+ .byte $04
+ .byte $52
+ .byte $0C
+ .byte $04
+ bbc2 a, L8108
+ .byte $04
+ .byte $54
+ .byte $0C
+L80FE: .byte $04
+ eor L000C,x
+ .byte $04
+ lsr L000C,x
+ .byte $04
+ bbc2 L000C, L810C
+L8108: cli
+ .byte $0C
+ .byte $04
+ .byte $59
+L810C: .byte $0C
+ .byte $04
+ .byte $5A
+ .byte $0C
+ .byte $04
+ clb2 a
+ .byte $0C
+ .byte $04
+ .byte $5C
+ .byte $0C
+ .byte $04
+ eor L040C,x
+ lsr L040C,x
+ clb2 L000C
+ .byte $04
+ rts
+
+ .byte $0C
+ .byte $04
+ adc (L000C,x)
+ .byte $04
+ .byte $62
+ .byte $0C
+ .byte $04
+ bbs3 a, L8138
+ .byte $04
+ tst L000C
+ .byte $04
+ adc L000C
+ .byte $04
+ ror L000C
+ .byte $04
+ bbs3 L000C, L813C
+L8138: pla
+ .byte $0C
+ .byte $04
+ .byte $69
+L813C: .byte $0C
+ .byte $04
+ ror a
+ .byte $0C
+ .byte $04
+ seb3 a
+ .byte $0C
+ .byte $04
+ jmp (L040C)
+
+ adc L040C
+ ror L040C
+ seb3 L000C
+ .byte $04
+ bvs L815E
+ .byte $04
+ adc (L000C),y
+ .byte $04
+ .byte $72
+ .byte $0C
+ .byte $04
+ bbc3 a, L8168
+ .byte $04
+ .byte $74
+ .byte $0C
+L815E: .byte $04
+ adc L000C,x
+ .byte $04
+ ror L000C,x
+ .byte $04
+ bbc3 L000C, L816C
+L8168: sei
+ .byte $0C
+ .byte $04
+ .byte $79
+L816C: .byte $0C
+ .byte $04
+ .byte $7A
+ .byte $0C
+ .byte $04
+ clb3 a
+ .byte $0C
+ .byte $04
+ .byte $7C
+ .byte $0C
+ .byte $04
+ adc L040C,x
+ ror L040C,x
+ clb3 L000C
+ .byte $04
+ bra L818E
+ .byte $04
+ sta (L000C,x)
+ .byte $04
+ rrf L000C
+ .byte $04
+ bbs4 a, L8198
+ .byte $04
+ sty L000C
+L818E: .byte $04
+ sta L000C
+ .byte $04
+ stx L000C
+ .byte $04
+ bbs4 L000C, L819C
+L8198: dey
+ .byte $0C
+ .byte $04
+ .byte $89
+L819C: .byte $0C
+ .byte $04
+ txa
+ .byte $0C
+ .byte $04
+ seb4 a
+ .byte $0C
+ .byte $04
+ sty L040C
+ sta L040C
+ stx L040C
+ seb4 L000C
+ .byte $04
+ bcc L81BE
+ .byte $04
+ sta (L000C),y
+ .byte $04
+ .byte $92
+ .byte $0C
+ .byte $04
+ bbc4 a, L81C8
+ .byte $04
+ sty L000C,x
+L81BE: .byte $04
+ sta L000C,x
+ .byte $04
+ stx L000C,y
+ .byte $04
+ bbc4 L000C, L81CC
+L81C8: tya
+ .byte $0C
+ .byte $04
+ .byte $99
+L81CC: .byte $0C
+ .byte $04
+ txs
+ .byte $0C
+ .byte $04
+ clb4 a
+ .byte $0C
+ .byte $04
+ .byte $9C
+ .byte $0C
+ .byte $04
+ sta L040C,x
+ .byte $9E
+ .byte $0C
+ .byte $04
+ clb4 L000C
+ .byte $04
+ ldy #$0C
+ .byte $04
+ lda (L000C,x)
+ .byte $04
+ ldx #$0C
+ .byte $04
+ bbs5 a, L81F8
+ .byte $04
+ ldy L000C
+ .byte $04
+ lda L000C
+ .byte $04
+ ldx L000C
+ .byte $04
+ bbs5 L000C, L81FC
+L81F8: tay
+ .byte $0C
+ .byte $04
+ .byte $A9
+L81FC: .byte $0C
+ .byte $04
+ tax
+ .byte $0C
+ .byte $04
+ seb5 a
+ .byte $0C
+ .byte $04
+ ldy L040C
+ lda L040C
+ ldx L040C
+ seb5 L000C
+ .byte $04
+ bcs L821E
+ .byte $04
+ lda (L000C),y
+ .byte $04
+ jmp (L000C)
+
+ .byte $04
+ bbc5 a, L8228
+ .byte $04
+ ldy L000C,x
+L821E: .byte $04
+ lda L000C,x
+ .byte $04
+ ldx L000C,y
+ .byte $04
+ bbc5 L000C, L822C
+L8228: clv
+ .byte $0C
+ .byte $04
+ .byte $B9
+L822C: .byte $0C
+ .byte $04
+ tsx
+ .byte $0C
+ .byte $04
+ clb5 a
+ .byte $0C
+ .byte $04
+ ldy L040C,x
+ lda L040C,x
+ ldx L040C,y
+ clb5 L000C
+ .byte $04
+ cpy #$0C
+ .byte $04
+ cmp (L000C,x)
+ .byte $04
+ slw
+ .byte $0C
+ .byte $04
+ bbs6 a, L8258
+ .byte $04
+ cpy L000C
+ .byte $04
+ cmp L000C
+ .byte $04
+ dec L000C
+ .byte $04
+ bbs6 L000C, L825C
+L8258: iny
+ .byte $0C
+ .byte $04
+ .byte $C9
+L825C: .byte $0C
+ .byte $04
+ dex
+ .byte $0C
+ .byte $04
+ seb6 a
+ .byte $0C
+ .byte $04
+ cpy L040C
+ cmp L040C
+ dec L040C
+ seb6 L000C
+ .byte $04
+ bne L827E
+ .byte $04
+ cmp (L000C),y
+ .byte $04
+ .byte $D2
+ .byte $0C
+ .byte $04
+ bbc6 a, L8288
+ .byte $04
+ .byte $D4
+ .byte $0C
+L827E: .byte $04
+ cmp L000C,x
+ .byte $04
+ dec L000C,x
+ .byte $04
+ bbc6 L000C, L828C
+L8288: cld
+ .byte $0C
+ .byte $04
+ .byte $D9
+L828C: .byte $0C
+ .byte $04
+ .byte $DA
+ .byte $0C
+ .byte $04
+ clb6 a
+ .byte $0C
+ .byte $04
+ .byte $DC
+ .byte $0C
+ .byte $04
+ cmp L040C,x
+ dec L040C,x
+ clb6 L000C
+ .byte $04
+ cpx #$0C
+ .byte $04
+ sbc (L000C,x)
+ .byte $04
+ fst
+ .byte $0C
+ .byte $04
+ bbs7 a, L82B8
+ .byte $04
+ cpx L000C
+ .byte $04
+ sbc L000C
+ .byte $04
+ inc L000C
+ .byte $04
+ bbs7 L000C, L82BC
+L82B8: inx
+ .byte $0C
+ .byte $04
+ .byte $E9
+L82BC: .byte $0C
+ .byte $04
+ nop
+ .byte $0C
+ .byte $04
+ seb7 a
+ .byte $0C
+ .byte $04
+ cpx L040C
+ sbc L040C
+ inc L040C
+ seb7 L000C
+ .byte $04
+ beq L82DE
+ .byte $04
+ sbc (L000C),y
+ .byte $04
+ .byte $F2
+ .byte $0C
+ .byte $04
+ bbc7 a, L82E8
+ .byte $04
+ .byte $F4
+ .byte $0C
+L82DE: .byte $04
+ sbc L000C,x
+ .byte $04
+ inc L000C,x
+ .byte $04
+ bbc7 L000C, L82EC
+L82E8: sed
+ .byte $0C
+ .byte $04
+ .byte $F9
+L82EC: .byte $0C
+ .byte $04
+ .byte $FA
+ .byte $0C
+ .byte $04
+ clb7 a
+ .byte $0C
+ .byte $04
+ .byte $FC
+ .byte $0C
+ .byte $04
+ sbc L040C,x
+ inc L040C,x
+ clb7 L000C
+ .byte $04
diff --git a/test/asm/val/Makefile b/test/asm/val/Makefile
index 54b1100ec..08c000f95 100644
--- a/test/asm/val/Makefile
+++ b/test/asm/val/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the regression tests that return an error code on failure
ifneq ($(shell echo),)
diff --git a/test/dasm/45GS02-disass.s b/test/dasm/45GS02-disass.s
new file mode 100644
index 000000000..1ed174a2f
--- /dev/null
+++ b/test/dasm/45GS02-disass.s
@@ -0,0 +1,381 @@
+.setcpu "45GS02"
+
+ZP = $12
+ABS = $1234
+
+ brk
+ ora ($05,x)
+ cle
+ see
+ tsb $02
+ ora $02
+ asl $02
+ rmb0 $02
+ php
+ ora #$01
+ asl
+ tsy
+ tsb $1234
+ ora $1234
+ asl $1234
+ bbr0 $02, L0
+L0:
+ bpl L0
+ ora ($06),y
+ ora ($07),z
+ lbpl *+$3133 ; bpl *+$3133
+ trb $02
+ ora $03,x
+ asl $03,x
+ rmb1 $02
+ clc
+ ora $1456,y
+ inc
+ inz
+ trb $1234
+ ora $1345,x
+ asl $1345,x
+ bbr1 $02,L1
+L1:
+ jsr $1234
+ and ($05,x)
+ jsr ($2345)
+ jsr ($2456,x)
+ bit $02
+ and $02
+ rol $02
+ rmb2 $02
+ plp
+ and #$01
+ rol
+ tys
+ bit $1234
+ and $1234
+ rol $1234
+ bbr2 $02,L2
+L2:
+ bmi L2
+ and ($06),y
+ and ($07),z
+ lbmi *+$3133 ; bmi *+$3133
+ bit $03,x
+ and $03,x
+ rol $03,x
+ rmb3 $02
+ sec
+ and $1456,y
+ dec
+ dez
+ bit $1345,x
+ and $1345,x
+ rol $1345,x
+ bbr3 $02,L3
+L3:
+ rti
+ eor ($05,x)
+ neg
+ asr
+ asr $02
+ eor $02
+ lsr $02
+ rmb4 $02
+ pha
+ eor #$01
+ lsr
+ taz
+ jmp $1234
+ eor $1234
+ lsr $1234
+ bbr4 $02,L4
+L4:
+ bvc L4
+ eor ($06),y
+ eor ($07),z
+ lbvc *+$3133 ; bvc *+$3133
+ asr $03,x
+ eor $03,x
+ lsr $03,x
+ rmb5 $02
+ cli
+ eor $1456,y
+ phy
+ tab
+ map
+ eor $1345,x
+ lsr $1345,x
+ bbr5 $02,L5
+L5:
+ rts
+ adc ($05,x)
+ rtn #$09
+ bsr *+$3133
+ stz $02
+ adc $02
+ ror $02
+ rmb6 $02
+ pla
+ adc #$01
+ ror
+ tza
+ jmp ($2345)
+ adc $1234
+ ror $1234
+ bbr6 $02,L6
+L6:
+ bvs L6
+ adc ($06),y
+ adc ($07),z
+ lbvs *+$3133 ; bvs *+$3133
+ stz $03,x
+ adc $03,x
+ ror $03,x
+ rmb7 $02
+ sei
+ adc $1456,y
+ ply
+ tba
+ jmp ($2456,x)
+ adc $1345,x
+ ror $1345,x
+ bbr7 $02,L7
+L7:
+ bra L7
+ sta ($05,x)
+ sta ($0f,s),y
+ sta ($0f,sp),y
+ lbra *+$3133 ; bra *+$3133
+ sty $02
+ sta $02
+ stx $02
+ smb0 $02
+ dey
+ bit #$01
+ txa
+ sty $1345,x
+ sty $1234
+ sta $1234
+ stx $1234
+ bbs0 $02,L8
+L8:
+ bcc L8
+ sta ($06),y
+ sta ($07),z
+ lbcc *+$3133 ; bcc *+$3133
+ sty $03,x
+ sta $03,x
+ stx $04,y
+ smb1 $02
+ tya
+ sta $1456,y
+ txs
+ stx $1456,y
+ stz $1234
+ sta $1345,x
+ stz $1345,x
+ bbs1 $02,L9
+L9:
+ ldy #$01
+ lda ($05,x)
+ ldx #$01
+ ldz #$01
+ ldy $02
+ lda $02
+ ldx $02
+ smb2 $02
+ tay
+ lda #$01
+ tax
+ ldz $1234
+ ldy $1234
+ lda $1234
+ ldx $1234
+ bbs2 $02,L10
+L10:
+ bcs L10
+ lda ($06),y
+ lda ($07),z
+ lbcs *+$3133 ; bcs *+$3133
+ ldy $03,x
+ lda $03,x
+ ldx $04,y
+ smb3 $02
+ clv
+ lda $1456,y
+ tsx
+ ldz $1345,x
+ ldy $1345,x
+ lda $1345,x
+ ldx $1456,y
+ bbs3 $02,L11
+L11:
+ cpy #$01
+ cmp ($05,x)
+ cpz #$01
+ dew $02
+ cpy $02
+ cmp $02
+ dec $02
+ smb4 $02
+ iny
+ cmp #$01
+ dex
+ asw $1234
+ cpy $1234
+ cmp $1234
+ dec $1234
+ bbs4 $02,L12
+L12:
+ bne L12
+ cmp ($06),y
+ cmp ($07),z
+ lbne *+$3133 ; bne *+$3133
+ cpz $02
+ cmp $03,x
+ dec $03,x
+ smb5 $02
+ cld
+ cmp $1456,y
+ phx
+ phz
+ cpz $1234
+ cmp $1345,x
+ dec $1345,x
+ bbs5 $02,L13
+L13:
+ cpx #$01
+ sbc ($05,x)
+ lda ($0f,s),y
+ lda ($0f,sp),y
+ inw $02
+ cpx $02
+ sbc $02
+ inc $02
+ smb6 $02
+ inx
+ sbc #$01
+ eom
+ nop
+ row $1234
+ cpx $1234
+ sbc $1234
+ inc $1234
+ bbs6 $02,L14
+L14:
+ beq L14
+ sbc ($06),y
+ sbc ($07),z
+ lbeq *+$3133 ; beq *+$3133
+ phd #$089a
+ phw #$089a
+ sbc $03,x
+ inc $03,x
+ smb7 $02
+ sed
+ sbc $1456,y
+ plx
+ plz
+ phd $1234
+ phw $1234
+ sbc $1345,x
+ inc $1345,x
+ bbs7 $02,L15
+L15:
+
+ adc [$12],z
+
+ adcq $12
+ adcq $3456
+ adcq ($78)
+ adcq [$9a]
+
+ and [$12],z
+
+ andq $12
+ andq $3456
+ andq ($78)
+ andq [$9a]
+
+ aslq $12
+ aslq
+ aslq $3456
+ aslq $78,x
+ aslq $9abc,x
+
+ asrq
+ asrq $12
+ asrq $34,x
+
+ bitq $12
+ bitq $3456
+
+ cmp [$12],z
+
+ cmpq $12
+ cmpq $3456
+ cmpq ($78)
+ cmpq [$9a]
+
+ deq
+ deq $12
+ deq $3456
+ deq $78,x
+ deq $9abc,x
+
+ eor [$12],z
+
+ eorq $12
+ eorq $3456
+ eorq ($78)
+ eorq [$9a]
+
+ inq
+ inq $12
+ inq $3456
+ inq $78,x
+ inq $9abc,x
+
+ lda [$12],z
+
+ ldq $12
+ ldq $3456
+ ldq ($78),z
+ ldq [$9a],z
+
+ lsrq $12
+ lsrq
+ lsrq $3456
+ lsrq $78,x
+ lsrq $9abc,x
+
+ ora [$12],z
+
+ orq $12
+ orq $3456
+ orq ($78)
+ orq [$9a]
+
+ rolq $12
+ rolq
+ rolq $3456
+ rolq $78,x
+ rolq $9abc,x
+
+ rorq $12
+ rorq
+ rorq $3456
+ rorq $78,x
+ rorq $9abc,x
+
+ sbc [$12],z
+
+ sbcq $12
+ sbcq $3456
+ sbcq ($78)
+ sbcq [$9a]
+
+ sta [$12],z ; EA 92 12
+
+ stq $12
+ stq $3456
+ stq ($78)
+ stq [$9a]
diff --git a/test/dasm/6502-disass.s b/test/dasm/6502-disass.s
new file mode 100644
index 000000000..794eead76
--- /dev/null
+++ b/test/dasm/6502-disass.s
@@ -0,0 +1,8 @@
+
+ .setcpu "6502"
+
+ .repeat 256, cnt
+
+ .byte 0 + cnt, $02, $ea, $00
+
+ .endrepeat
diff --git a/test/dasm/6502DTV-disass.s b/test/dasm/6502DTV-disass.s
new file mode 100644
index 000000000..5254923c5
--- /dev/null
+++ b/test/dasm/6502DTV-disass.s
@@ -0,0 +1,188 @@
+.setcpu "6502DTV"
+
+ brk
+ ora ($12,x)
+ nop $12
+ ora $12
+ asl $12
+ php
+ ora #$12
+ asl a
+ anc #$12
+ nop $3456
+ ora $3456
+ asl $3456
+ bpl *+2
+ ora ($12),y
+ bra *+2
+ nop $12,x
+ ora $12,x
+ asl $12,x
+ clc
+ ora $3456,y
+ nop $3456,x
+ ora $3456,x
+ asl $3456,x
+ jsr $3456
+ and ($12,x)
+ rla ($12,x)
+ bit $12
+ and $12
+ rol $12
+ rla $12
+ plp
+ and #$12
+ rol a
+ bit $3456
+ and $3456
+ rol $3456
+ rla $3456
+ bmi *+2
+ and ($12),y
+ sac #$12
+ rla ($12),y
+ and $12,x
+ rol $12,x
+ rla $12,x
+ sec
+ and $3456,y
+ rla $3456,y
+ and $3456,x
+ rol $3456,x
+ rla $3456,x
+ rti
+ eor ($12,x)
+ sir #$12
+ eor $12
+ lsr $12
+ pha
+ eor #$12
+ lsr a
+ alr #$12
+ jmp $3456
+ eor $3456
+ lsr $3456
+ bvc *+2
+ eor ($12),y
+ eor $12,x
+ lsr $12,x
+ cli
+ eor $3456,x
+ lsr $3456,x
+ rts
+ adc ($12,x)
+ rra ($12,x)
+ adc $12
+ ror $12
+ rra $12
+ pla
+ adc #$12
+ ror a
+ arr #$12
+ jmp ($3456)
+ adc $3456
+ ror $3456
+ rra $3456
+ bvs *+2
+ adc ($12),y
+ rra ($12),y
+ adc $12,x
+ ror $12,x
+ rra $12,x
+ sei
+ adc $3456,y
+ rra $3456,y
+ adc $3456,x
+ ror $3456,x
+ rra $3456,x
+ nop #$12
+ sta ($12,x)
+ sty $12
+ sta $12
+ stx $12
+ dey
+ txa
+ sty $3456
+ sta $3456
+ stx $3456
+ bcc *+2
+ sta ($12),y
+ sty $12,x
+ sta $12,x
+ stx $12,y
+ tya
+ sta $3456,y
+ txs
+ shy $3456,x
+ sta $3456,x
+ shx $3456,y
+ ldy #$12
+ lda ($12,x)
+ ldx #$12
+ lax ($12,x)
+ ldy $12
+ lda $12
+ ldx $12
+ lax $12
+ tay
+ lda #$12
+ tax
+ lax #$12
+ ldy $3456
+ lda $3456
+ ldx $3456
+ lax $3456
+ bcs *+2
+ lda ($12),y
+ lax ($12),y
+ ldy $12,x
+ lda $12,x
+ ldx $12,y
+ lax $12,y
+ clv
+ lda $3456,y
+ tsx
+ las $3456,y
+ ldy $3456,x
+ lda $3456,x
+ ldx $3456,y
+ lax $3456,y
+ cpy #$12
+ cmp ($12,x)
+ cpy $12
+ cmp $12
+ dec $12
+ iny
+ cmp #$12
+ dex
+ axs #$12
+ cpy $3456
+ cmp $3456
+ dec $3456
+ bne *+2
+ cmp ($12),y
+ cmp $12,x
+ dec $12,x
+ cld
+ cmp $3456,y
+ cmp $3456,x
+ dec $3456,x
+ cpx #$12
+ sbc ($12,x)
+ cpx $12
+ sbc $12
+ inc $12
+ inx
+ sbc #$12
+ nop
+ cpx $3456
+ sbc $3456
+ inc $3456
+ beq *+2
+ sbc ($12),y
+ sbc $12,x
+ inc $12,x
+ sed
+ sbc $3456,y
+ sbc $3456,x
+ inc $3456,x
diff --git a/test/dasm/6502X-disass.s b/test/dasm/6502X-disass.s
new file mode 100644
index 000000000..f102144c4
--- /dev/null
+++ b/test/dasm/6502X-disass.s
@@ -0,0 +1,30 @@
+
+ .setcpu "6502X"
+
+ .repeat 256, cnt
+
+ ; generate a pattern with all opcodes. however, for the full cycle to work,
+ ; we must take care of the "duplicate" opcodes, ie use only the favourite one.
+ .if ((cnt & $0f) = $02)
+ .byte $02 ; all JAM
+ .elseif ((cnt & $1f) = $1a)
+ .byte $ea ; all NOP
+ .elseif (cnt = $2b)
+ .byte $0b ; both ANC #imm
+ .elseif (cnt = $89)
+ .byte $80 ; both NOP #imm
+ .elseif (cnt = $eb)
+ .byte $e9 ; both SBC #imm
+ .elseif (cnt = $34) || (cnt = $54) || (cnt = $74) || (cnt = $d4) || (cnt = $f4)
+ .byte $14 ; all NOP zp, x
+ .elseif (cnt = $3c) || (cnt = $5c) || (cnt = $7c) || (cnt = $dc) || (cnt = $fc)
+ .byte $1c ; all NOP abs, x
+ .elseif (cnt = $44) || (cnt = $64)
+ .byte $04 ; all NOP zp
+ .else
+ .byte cnt
+ .endif
+
+ .byte $02, $ea, $00
+
+ .endrepeat
diff --git a/test/dasm/65C02-disass.s b/test/dasm/65C02-disass.s
new file mode 100644
index 000000000..0613921d5
--- /dev/null
+++ b/test/dasm/65C02-disass.s
@@ -0,0 +1,214 @@
+.setcpu "65C02"
+
+ brk
+ ora ($12,x)
+ tsb $12
+ ora $12
+ asl $12
+ rmb0 $12
+ php
+ ora #$12
+ asl a
+ tsb $3456
+ ora $3456
+ asl $3456
+ bbr0 $12,*+2
+ bpl *+2
+ ora ($12),y
+ ora ($12)
+ trb $12
+ ora $12,x
+ asl $12,x
+ rmb1 $12
+ clc
+ ora $3456,y
+ inc a
+ trb $3456
+ ora $3456,x
+ asl $3456,x
+ bbr1 $12,*+2
+ jsr $3456
+ and ($12,x)
+ bit $12
+ and $12
+ rol $12
+ rmb2 $12
+ plp
+ and #$12
+ rol a
+ bit $3456
+ and $3456
+ rol $3456
+ bbr2 $12,*+2
+ bmi *+2
+ and ($12),y
+ and ($12)
+ bit $12,x
+ and $12,x
+ rol $12,x
+ rmb3 $12
+ sec
+ and $3456,y
+ dec a
+ bit $3456,x
+ and $3456,x
+ rol $3456,x
+ bbr3 $12,*+2
+ rti
+ eor ($12,x)
+ eor $12
+ lsr $12
+ rmb4 $12
+ pha
+ eor #$12
+ lsr a
+ jmp $3456
+ eor $3456
+ lsr $3456
+ bbr4 $12,*+2
+ bvc *+2
+ eor ($12),y
+ eor ($12)
+ eor $12,x
+ lsr $12,x
+ rmb5 $12
+ cli
+ eor $3456,y
+ phy
+ eor $3456,x
+ lsr $3456,x
+ bbr5 $12,*+2
+ rts
+ adc ($12,x)
+ stz $12
+ adc $12
+ ror $12
+ rmb6 $12
+ pla
+ adc #$12
+ ror a
+ jmp ($3456)
+ adc $3456
+ ror $3456
+ bbr6 $12,*+2
+ bvs *+2
+ adc ($12),y
+ adc ($12)
+ stz $12,x
+ adc $12,x
+ ror $12,x
+ rmb7 $12
+ sei
+ adc $3456,y
+ ply
+ jmp ($3456,x)
+ adc $3456,x
+ ror $3456,x
+ bbr7 $12,*+2
+ bra *+2
+ sta ($12,x)
+ sty $12
+ sta $12
+ stx $12
+ smb0 $12
+ dey
+ bit #$12
+ txa
+ sty $3456
+ sta $3456
+ stx $3456
+ bbs0 $12,*+2
+ bcc *+2
+ sta ($12),y
+ sta ($12)
+ sty $12,x
+ sta $12,x
+ stx $12,y
+ smb1 $12
+ tya
+ sta $3456,y
+ txs
+ stz $3456
+ sta $3456,x
+ stz $3456,x
+ bbs1 $12,*+2
+ ldy #$12
+ lda ($12,x)
+ ldx #$12
+ ldy $12
+ lda $12
+ ldx $12
+ smb2 $12
+ tay
+ lda #$12
+ tax
+ ldy $3456
+ lda $3456
+ ldx $3456
+ bbs2 $12,*+2
+ bcs *+2
+ lda ($12),y
+ lda ($12)
+ ldy $12,x
+ lda $12,x
+ ldx $12,y
+ smb3 $12
+ clv
+ lda $3456,y
+ tsx
+ ldy $3456,x
+ lda $3456,x
+ ldx $3456,y
+ bbs3 $12,*+2
+ cpy #$12
+ cmp ($12,x)
+ cpy $12
+ cmp $12
+ dec $12
+ smb4 $12
+ iny
+ cmp #$12
+ dex
+ cpy $3456
+ cmp $3456
+ dec $3456
+ bbs4 $12,*+2
+ bne *+2
+ cmp ($12),y
+ cmp ($12)
+ cmp $12,x
+ dec $12,x
+ smb5 $12
+ cld
+ cmp $3456,y
+ phx
+ cmp $3456,x
+ dec $3456,x
+ bbs5 $12,*+2
+ cpx #$12
+ sbc ($12,x)
+ cpx $12
+ sbc $12
+ inc $12
+ smb6 $12
+ inx
+ sbc #$12
+ nop
+ cpx $3456
+ sbc $3456
+ inc $3456
+ bbs6 $12,*+2
+ beq *+2
+ sbc ($12),y
+ sbc ($12)
+ sbc $12,x
+ inc $12,x
+ smb7 $12
+ sed
+ sbc $3456,y
+ plx
+ sbc $3456,x
+ inc $3456,x
+L0:
+ bbs7 $12,L0
+ nop
diff --git a/test/dasm/65SC02-disass.s b/test/dasm/65SC02-disass.s
new file mode 100644
index 000000000..46e96aaf9
--- /dev/null
+++ b/test/dasm/65SC02-disass.s
@@ -0,0 +1,181 @@
+.setcpu "65SC02"
+
+ brk
+ ora ($12,x)
+ tsb $12
+ ora $12
+ asl $12
+ php
+ ora #$12
+ asl a
+ tsb $3456
+ ora $3456
+ asl $3456
+ bpl *+2
+ ora ($12),y
+ ora ($12)
+ trb $12
+ ora $12,x
+ asl $12,x
+ clc
+ ora $3456,y
+ inc a
+ trb $3456
+ ora $3456,x
+ asl $3456,x
+ jsr $3456
+ and ($12,x)
+ bit $12
+ and $12
+ rol $12
+ plp
+ and #$12
+ rol a
+ bit $3456
+ and $3456
+ rol $3456
+ bmi *+2
+ and ($12),y
+ and ($12)
+ bit $12,x
+ and $12,x
+ rol $12,x
+ sec
+ and $3456,y
+ dec a
+ bit $3456,x
+ and $3456,x
+ rol $3456,x
+ rti
+ eor ($12,x)
+ eor $12
+ lsr $12
+ pha
+ eor #$12
+ lsr a
+ jmp $3456
+ eor $3456
+ lsr $3456
+ bvc *+2
+ eor ($12),y
+ eor ($12)
+ eor $12,x
+ lsr $12,x
+ cli
+ eor $3456,y
+ phy
+ eor $3456,x
+ lsr $3456,x
+ rts
+ adc ($12,x)
+ stz $12
+ adc $12
+ ror $12
+ pla
+ adc #$12
+ ror a
+ jmp ($3456)
+ adc $3456
+ ror $3456
+ bvs *+2
+ adc ($12),y
+ adc ($12)
+ stz $12,x
+ adc $12,x
+ ror $12,x
+ sei
+ adc $3456,y
+ ply
+ jmp ($3456,x)
+ adc $3456,x
+ ror $3456,x
+ bra *+2
+ sta ($12,x)
+ sty $12
+ sta $12
+ stx $12
+ dey
+ bit #$12
+ txa
+ sty $3456
+ sta $3456
+ stx $3456
+ bcc *+2
+ sta ($12),y
+ sta ($12)
+ sty $12,x
+ sta $12,x
+ stx $12,y
+ tya
+ sta $3456,y
+ txs
+ stz $3456
+ sta $3456,x
+ stz $3456,x
+ ldy #$12
+ lda ($12,x)
+ ldx #$12
+ ldy $12
+ lda $12
+ ldx $12
+ tay
+ lda #$12
+ tax
+ ldy $3456
+ lda $3456
+ ldx $3456
+ bcs *+2
+ lda ($12),y
+ lda ($12)
+ ldy $12,x
+ lda $12,x
+ ldx $12,y
+ clv
+ lda $3456,y
+ tsx
+ ldy $3456,x
+ lda $3456,x
+ ldx $3456,y
+ cpy #$12
+ cmp ($12,x)
+ cpy $12
+ cmp $12
+ dec $12
+ iny
+ cmp #$12
+ dex
+ cpy $3456
+ cmp $3456
+ dec $3456
+ bne *+2
+ cmp ($12),y
+ cmp ($12)
+ cmp $12,x
+ dec $12,x
+ cld
+ cmp $3456,y
+ phx
+ cmp $3456,x
+ dec $3456,x
+ cpx #$12
+ sbc ($12,x)
+ cpx $12
+ sbc $12
+ inc $12
+ inx
+ sbc #$12
+ nop
+ cpx $3456
+ sbc $3456
+ inc $3456
+ beq *+2
+ sbc ($12),y
+ sbc ($12)
+ sbc $12,x
+ inc $12,x
+ sed
+ sbc $3456,y
+ plx
+ sbc $3456,x
+ inc $3456,x
+
diff --git a/test/dasm/Makefile b/test/dasm/Makefile
index e84560ad2..29e97b9c1 100644
--- a/test/dasm/Makefile
+++ b/test/dasm/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the disassembler regression tests
ifneq ($(shell echo),)
diff --git a/test/dasm/huc6280-disass.s b/test/dasm/huc6280-disass.s
new file mode 100644
index 000000000..4ae7b067d
--- /dev/null
+++ b/test/dasm/huc6280-disass.s
@@ -0,0 +1,250 @@
+.setcpu "huc6280"
+
+ brk
+ ora ($12,x)
+ sxy
+ st0 #$12
+ tsb $12
+ ora $12
+ asl $12
+ rmb0 $12
+ php
+ ora #$12
+ asl a
+ tsb $3456
+ ora $3456
+ asl $3456
+ bbr0 $12,L0
+L0:
+ bpl *+2
+ ora ($12),y
+ ora ($12)
+ st1 #$12
+ trb $12
+ ora $12,x
+ asl $12,x
+ rmb1 $12
+ clc
+ ora $3456,y
+ inc a
+ trb $3456
+ ora $3456,x
+ asl $3456,x
+ bbr1 $12,L1
+L1:
+ jsr $3456
+ and ($12,x)
+ sax
+ st2 #$12
+ bit $12
+ and $12
+ rol $12
+ rmb2 $12
+ plp
+ and #$12
+ rol a
+ bit $3456
+ and $3456
+ rol $3456
+ bbr2 $12,L2
+L2:
+ bmi *+2
+ and ($12),y
+ and ($12)
+ bit $12,x
+ and $12,x
+ rol $12,x
+ rmb3 $12
+ sec
+ and $3456,y
+ dec a
+ bit $3456,x
+ and $3456,x
+ rol $3456,x
+ bbr3 $12,L3
+L3:
+ rti
+ eor ($12,x)
+ say
+ tma #$02
+ bsr *+2
+ eor $12
+ lsr $12
+ rmb4 $12
+ pha
+ eor #$12
+ lsr a
+ jmp $3456
+ eor $3456
+ lsr $3456
+ bbr4 $12,L4
+L4:
+ bvc *+2
+ eor ($12),y
+ eor ($12)
+ tam #$12
+ csl
+ eor $12,x
+ lsr $12,x
+ rmb5 $12
+ cli
+ eor $3456,y
+ phy
+ eor $3456,x
+ lsr $3456,x
+ bbr5 $12,L5
+L5:
+ rts
+ adc ($12,x)
+ cla
+ stz $12
+ adc $12
+ ror $12
+ rmb6 $12
+ pla
+ adc #$12
+ ror a
+ jmp ($3456)
+ adc $3456
+ ror $3456
+ bbr6 $12,L6
+L6:
+ bvs *+2
+ adc ($12),y
+ adc ($12)
+ tii $3333,$7373,$1111
+ stz $12,x
+ adc $12,x
+ ror $12,x
+ rmb7 $12
+ sei
+ adc $3456,y
+ ply
+ jmp ($3456,x)
+ adc $3456,x
+ ror $3456,x
+ bbr7 $12,L7
+L7:
+ bra *+2
+ sta ($12,x)
+ clx
+ tst #$12,$EA
+ sty $12
+ sta $12
+ stx $12
+ smb0 $12
+ dey
+ bit #$12
+ txa
+ sty $3456
+ sta $3456
+ stx $3456
+ bbs0 $12,LS0
+LS0:
+ bcc *+2
+ sta ($12),y
+ sta ($12)
+ tst #$12,$EAEA
+ sty $12,x
+ sta $12,x
+ stx $12,y
+ smb1 $12
+ tya
+ sta $3456,y
+ txs
+ stz $3456
+ sta $3456,x
+ stz $3456,x
+ bbs1 $12,LS1
+LS1:
+ ldy #$12
+ lda ($12,x)
+ ldx #$12
+ tst #$12,$EA,x
+ ldy $12
+ lda $12
+ ldx $12
+ smb2 $12
+ tay
+ lda #$12
+ tax
+ ldy $3456
+ lda $3456
+ ldx $3456
+ bbs2 $12,LS2
+LS2:
+ bcs *+2
+ lda ($12),y
+ lda ($12)
+ tst #$12,$EAEA,x
+ ldy $12,x
+ lda $12,x
+ ldx $12,y
+ smb3 $12
+ clv
+ lda $3456,y
+ tsx
+ ldy $3456,x
+ lda $3456,x
+ ldx $3456,y
+ bbs3 $12,LS3
+LS3:
+ cpy #$12
+ cmp ($12,x)
+ cly
+ tdd $3333,$C3C3,$1111
+ cpy $12
+ cmp $12
+ dec $12
+ smb4 $12
+ iny
+ cmp #$12
+ dex
+ cpy $3456
+ cmp $3456
+ dec $3456
+ bbs4 $12,LS4
+LS4:
+ bne *+2
+ cmp ($12),y
+ cmp ($12)
+ tin $3333,$D3D3,$1111
+ cmp $12,x
+ dec $12,x
+ smb5 $12
+ cld
+ cmp $3456,y
+ phx
+ cmp $3456,x
+ dec $3456,x
+ bbs5 $12,LS5
+LS5:
+ cpx #$12
+ sbc ($12,x)
+ tia $3333,$E3E3,$1111
+ cpx $12
+ sbc $12
+ inc $12
+ smb6 $12
+ inx
+ sbc #$12
+ nop
+ cpx $3456
+ sbc $3456
+ inc $3456
+ bbs6 $12,LS6
+LS6:
+ beq *+2
+ sbc ($12),y
+ sbc ($12)
+ tai $3333,$F3F3,$1111
+ sbc $12,x
+ inc $12,x
+ smb7 $12
+ sed
+ sbc $3456,y
+ plx
+ sbc $3456,x
+ inc $3456,x
+LS7:
+ bbs7 $12,LS7
diff --git a/test/dasm/m740-disass.s b/test/dasm/m740-disass.s
new file mode 100644
index 000000000..ea0f19f8d
--- /dev/null
+++ b/test/dasm/m740-disass.s
@@ -0,0 +1,8 @@
+
+ .setcpu "M740"
+
+ .repeat 256, cnt
+
+ .byte 0 + cnt, $12, $02, $ea
+
+ .endrepeat
diff --git a/test/dasm/readme.txt b/test/dasm/readme.txt
new file mode 100644
index 000000000..9e001ec8c
--- /dev/null
+++ b/test/dasm/readme.txt
@@ -0,0 +1,9 @@
+
+Per CPU, a test binary is produced (using the assembler), which should contain
+all possible instructions. That file is then disassembled, and assembled again,
+and finally the resulting binary compared with the binary produced in the first
+step.
+
+Given that we assume the assembler works (this is tested in other/previous
+tests), this proves that the disassembler works, and can produce output that the
+assembler will understand - and produce an identical binary from.
diff --git a/test/err/Makefile b/test/err/Makefile
index 1273bbb2c..a0cdc22ae 100644
--- a/test/err/Makefile
+++ b/test/err/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the tests that MUST NOT compile
ifneq ($(shell echo),)
diff --git a/test/misc/Makefile b/test/misc/Makefile
index 48293e504..989e8f83a 100644
--- a/test/misc/Makefile
+++ b/test/misc/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the remaining tests that need special care in one way or another
ifneq ($(shell echo),)
diff --git a/test/ref/Makefile b/test/ref/Makefile
index e82c6de37..2dadf5bcc 100644
--- a/test/ref/Makefile
+++ b/test/ref/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the regression tests that generate output which has to be
# compared with reference output
diff --git a/test/standard/Makefile b/test/standard/Makefile
index bf513c84e..e359fa975 100644
--- a/test/standard/Makefile
+++ b/test/standard/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the regression tests that return an error code on failure
ifneq ($(shell echo),)
diff --git a/test/standard_err/Makefile b/test/standard_err/Makefile
index 700a52eea..f554d33eb 100644
--- a/test/standard_err/Makefile
+++ b/test/standard_err/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the tests that MUST NOT compile
ifneq ($(shell echo),)
diff --git a/test/todo/Makefile b/test/todo/Makefile
index 062b899ce..ec14cf8d4 100644
--- a/test/todo/Makefile
+++ b/test/todo/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the currently failing regression tests that return an error code on failure
ifneq ($(shell echo),)
diff --git a/test/val/Makefile b/test/val/Makefile
index 56d8e5ff9..68882971d 100644
--- a/test/val/Makefile
+++ b/test/val/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
# Makefile for the regression tests that return an error code on failure
ifneq ($(shell echo),)
diff --git a/util/Makefile b/util/Makefile
index 6d960abf6..337320d36 100644
--- a/util/Makefile
+++ b/util/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
.PHONY: atari gamate zlib
diff --git a/util/atari/Makefile b/util/atari/Makefile
index e53c837aa..aa3163ec4 100644
--- a/util/atari/Makefile
+++ b/util/atari/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
CC = $(CROSS_COMPILE)gcc
diff --git a/util/gamate/Makefile b/util/gamate/Makefile
index 54fa74191..d9b4bbd42 100644
--- a/util/gamate/Makefile
+++ b/util/gamate/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
CC = $(CROSS_COMPILE)gcc
diff --git a/util/zlib/Makefile b/util/zlib/Makefile
index f276ddaf2..8068ea120 100644
--- a/util/zlib/Makefile
+++ b/util/zlib/Makefile
@@ -1,3 +1,9 @@
+# ---- Display info during parsing phase ----
+SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
+ifneq ($(SILENT),s)
+ $(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
+endif
+
CC = $(CROSS_COMPILE)gcc