From c75d1dd7df500f6b4747eaa16d10066afbcf8e9e Mon Sep 17 00:00:00 2001 From: mrdudz Date: Thu, 19 Jun 2025 22:42:36 +0200 Subject: [PATCH] update docs with some more info about the various cpu modes --- doc/ca65.sgml | 281 +++++++++++++++++++++++++++++++++++++------------- 1 file changed, 212 insertions(+), 69 deletions(-) diff --git a/doc/ca65.sgml b/doc/ca65.sgml index 22f9a03cf..8991db900 100644 --- a/doc/ca65.sgml +++ b/doc/ca65.sgml @@ -399,7 +399,7 @@ name="--bin-include-dir">/ option on the command line. -Input format

+Input format

@@ -426,21 +426,23 @@ Here are some examples for valid input lines: The assembler accepts -all valid 6502 mnemonics when in 6502 mode (the default or after the +all valid 6502 mnemonics when in + (the default or after the command was given). -all valid 6502 mnemonics plus a set of illegal instructions when in - . -all valid 6502DTV mnemonics when in 6502DTV mode (after the +all valid 6502 mnemonics, plus a set of illegal instructions, when in + (after the + command was given). +all valid 6502DTV mnemonics when in (after the command was given). -all valid 65SC02 mnemonics when in 65SC02 mode (after the +all valid 65SC02 mnemonics when in (after the command was given). -all valid 65C02 mnemonics when in 65C02 mode (after the +all valid 65C02 mnemonics when in (after the command was given). -all valid 65816 mnemonics when in 65816 mode (after the +all valid 65816 mnemonics when in (after the command was given). -all valid 4510 mnemonics when in 4510 mode (after the +all valid 4510 mnemonics when in (after the command was given). -all valid M740 mnemonics when in M740 mode (after the +all valid M740 mnemonics when in (after the command was given). @@ -453,8 +455,206 @@ byte. If omitted, the assembler will only produce only 1 byte. brk #$34 ; 2-bytes: $00 $34 +6502 mode

-65816 mode

+In 6502 mode (which is the default) the assembler accepts all regular "legal" +6502 mnemonics and addressing modes. + +6502X mode

+ +6502X mode is an extension to the normal 6502 mode. In this mode, several +mnemonics for undocumented instructions of the NMOS 6502 CPUs are accepted. + +Note: Since these instructions are undocumented, there are no official mnemonics +for them. + + +ALR: A:=(A and #{imm})/2; +ANC: A:= A and #{imm}; Generates opcode $0B. +ANE: A:= (A or CONST) and X and #{imm}; +ARR: A:=(A and #{imm})/2; +AXS: X:=A and X-#{imm}; +DCP: {addr}:={addr}-1; A-{addr}; +ISC: {addr}:={addr}+1; A:=A-{addr}; +JAM: +LAS: A,X,S:={addr} and S; +LAX: A,X:={addr}; +NOP: #{imm}; zp; zp,x; abs; abs,x +RLA: {addr}:={addr}rol; A:=A and {addr}; +RRA: {addr}:={addr}ror; A:=A adc {addr}; +SAX: {addr}:=A and X; +SHA: {addr}:=A and X and {addr hi +1}; +SHX: {addr}:=X and {addr hi +1}; +SHY: {addr}:=Y and {addr hi +1}; +SLO: {addr}:={addr}*2; A:=A or {addr}; +SRE: {addr}:={addr}/2; A:=A xor {addr}; +TAS: {addr}:=A and X and {addr hi +1}; SP:=A and X; + + + +DTV mode

+ +The C64DTV CPU is based on the 6510, but adds some instructions, and does not +support all undocumented instructions. + + +bra {rel} Generates opcode $12. +sac #{imm} Generates opcode $32. +sir #{imm} Generates opcode $42. + + +Supported undocumented instructions: + + +ALR: A:=(A and #{imm})/2; +ANC: A:=A and #{imm}; Generates opcode $0B. +ARR: A:=(A and #{imm})/2; +AXS: X:=A and X-#{imm}; +LAS: A,X,S:={addr} and S; +LAX: A,X:={addr}; +NOP: #{imm}; zp; zp,x; abs; abs,x +RLA: {addr}:={addr}rol; A:=A and {addr}; +RRA: {addr}:={addr}ror; A:=A adc {addr}; +SHX: {addr}:=X and {addr hi +1}; +SHY: {addr}:=y and {addr hi +1}; + + + +65SC02 mode

+ +65SC02 mode supports all regular 6502 instructions, plus the following: + + +$04 tsb zp +$0c tsb abs16 +$12 ora (zp) +$14 trb zp +$1a inc +$1c trb abs16 +$32 and (zp) +$34 bit zp, x +$3a dec +$3c bit abs16, x +$52 eor (zp) +$5a phy +$64 stz zp +$72 adc (zp) +$74 stz zp, x +$7a ply +$7c jmp (abs16, x) +$80 bra rel8 +$89 bit #imm8 +$92 sta (zp) +$9c stz abs16 +$9e stz abs16, x +$b2 lda (zp) +$d2 cmp (zp) +$da phx +$f2 sbc (zp) +$fa plx + + + +65C02 mode

+ +65C02 mode supports all "official" W65C02 opcodes. + +The R65C02 adds bit manipulation instructions: + + +smbB zp set bit in zp location +rmbB zp reset bit in zp location +bbsB zp, rel8 branch if bit is set in zp location +bbrB zp, rel8 branch if bit is reset in zp location + + +And the W65C02 adds those: + + +$cb wai wait for interrupt +$db stp wait for reset + + + +4510 mode

+ +The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX. +It contains among other functions a slightly modified 65CE02/4502 CPU, to allow +address mapping for 20 bits of address space (1 megabyte addressable area). + +The 4510 mode supports the complete (legal) 65CE02 instruction set, plus these +three, which were changed/added: + +$5c map "4-byte NOP reserved for future expansion" on 65CE02 +$cb asw $1234 wai on W65C02 +$db phz stp on W65C02 + + +As compared to the description of the CPU in the + + uses these changes: + +LDA (d,SP),Y may also be written as LDA (d,S),Y +(matching the 65816 notation). +All branch instruction allow now 16 bit offsets. To use a 16 bit +branch you have to prefix these with an "L" (e.g. "LBNE" instead of +"BNE"). This might change at a later implementation of the assembler. + + +For more information about the Commodore C65/C64DX and the 4510 CPU, see + and +. + + +HUC6280 mode

+ +The HUC6280 is a superset of the R65C02. It adds some other instructions: + + +$02 sxy +$03 st0 #{imm} +$13 st1 #{imm} +$22 sax +$23 st2 #{imm} +$42 say +$43 tma #{imm} +$44 bsr {rel} +$53 tam #{imm} +$54 csl +$62 cla +$73 tii {addr}, {addr}, {addr} +$82 clx +$83 tst #{imm}, {zp} +$82 clx +$83 tst #{imm}, {zp} +$93 tst #{imm}, {addr} +$a3 tst #{imm}, {zp}, x +$b3 tst #{imm}, {addr}, x +$c2 cly +$c3 tdd {addr}, {addr}, {addr} +$d3 tin {addr}, {addr}, {addr} +$d4 csh +$e3 tia {addr}, {addr}, {addr} +$f3 tai {addr}, {addr}, {addr} +$f4 set + + +Note that this CPU does not implement wai and stp. + + +M740 mode

+ +The M740 is a microcontroller by Mitsubishi, which was marketed for embedded +devices in the mid 80s. It is a superset of 6502, and a subset of 65SC02, plus +some new instructions. + +For more information about the M740 Controllers, see +. + + +65816 mode

In 65816 mode, several aliases are accepted, in addition to the official mnemonics: @@ -482,64 +682,6 @@ or two far addresses whose high byte will be used. -6502X mode

- -6502X mode is an extension to the normal 6502 mode. In this mode, several -mnemonics for illegal instructions of the NMOS 6502 CPUs are accepted. Since -these instructions are illegal, there are no official mnemonics for them. The -unofficial ones are taken from . Please note that only the -ones marked as "stable" are supported. The following table uses information -from the mentioned web page, for more information, see there. - - -ALR: A:=(A and #{imm})/2; -ANC: A:=A and #{imm}; Generates opcode $0B. -ARR: A:=(A and #{imm})/2; -AXS: X:=A and X-#{imm}; -DCP: {adr}:={adr}-1; A-{adr}; -ISC: {adr}:={adr}+1; A:=A-{adr}; -LAS: A,X,S:={adr} and S; -LAX: A,X:={adr}; -RLA: {adr}:={adr}rol; A:=A and {adr}; -RRA: {adr}:={adr}ror; A:=A adc {adr}; -SAX: {adr}:=A and X; -SLO: {adr}:={adr}*2; A:=A or {adr}; -SRE: {adr}:={adr}/2; A:=A xor {adr}; - - - -4510 mode

- -The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX. -It contains among other functions a slightly modified 65CE02/4502 CPU, to allow -address mapping for 20 bits of address space (1 megabyte addressable area). -As compared to the description of the CPU in the - - uses these changes: - -LDA (d,SP),Y may also be written as LDA (d,S),Y -(matching the 65816 notataion). -All branch instruction allow now 16 bit offsets. To use a 16 bit -branch you have to prefix these with an "L" (e.g. "LBNE" instead of -"BNE"). This might change at a later implementation of the assembler. - -For more information about the Commodore C65/C64DX and the 4510 CPU, see - and -. - - -M740 mode

- -The M740 is a microcontroller by Mitsubishi, which was marketed for embedded -devices in the mid 80s. - -For more information about the M740 Controllers, see -. - - sweet16 mode

SWEET 16 is an interpreter for a pseudo 16 bit CPU written by Steve Wozniak @@ -4851,6 +4993,7 @@ it is possible to determine if the instruction is supported, which is the case for the 65SC02, 65C02 and 65816 CPUs (the latter two are upwards compatible to the 65SC02). +see section and following. .MACPACK module