diff --git a/asminc/cpu.mac b/asminc/cpu.mac
index 084a42119..818d70df1 100644
--- a/asminc/cpu.mac
+++ b/asminc/cpu.mac
@@ -8,7 +8,7 @@ CPU_ISET_65C02     = $0020
 CPU_ISET_65816     = $0040
 CPU_ISET_SWEET16   = $0080
 CPU_ISET_HUC6280   = $0100
-;CPU_ISET_M740     = $0200 not actually implemented
+CPU_ISET_M740      = $0200
 CPU_ISET_4510      = $0400
 
 ; CPU capabilities
@@ -20,5 +20,8 @@ CPU_65SC02         = CPU_ISET_6502|CPU_ISET_65SC02
 CPU_65C02          = CPU_ISET_6502|CPU_ISET_65SC02|CPU_ISET_65C02
 CPU_65816          = CPU_ISET_6502|CPU_ISET_65SC02|CPU_ISET_65816
 CPU_SWEET16        = CPU_ISET_SWEET16
+; NOTE: HUC6280 removes "wai" ($cb) and "stp" ($db) from the 65C02 instruction set
 CPU_HUC6280        = CPU_ISET_6502|CPU_ISET_65SC02|CPU_ISET_65C02|CPU_ISET_HUC6280
+; NOTE: 45100 replaces "wai" ($cb) and "stp" ($db) of the 65C02 instruction set
 CPU_4510           = CPU_ISET_6502|CPU_ISET_65SC02|CPU_ISET_65C02|CPU_ISET_4510
+CPU_M740           = CPU_ISET_6502|CPU_ISET_M740
diff --git a/doc/ca65.sgml b/doc/ca65.sgml
index a12a4accb..8991db900 100644
--- a/doc/ca65.sgml
+++ b/doc/ca65.sgml
@@ -152,7 +152,7 @@ Here is a description of all the command line options:
   Set the default for the CPU type. The option takes a parameter, which
   may be one of
 
-        6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, sweet16, HuC6280, 4510
+        6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, sweet16, HuC6280, 4510, M740
 
 
   <label id="option-create-dep">
@@ -399,7 +399,7 @@ name="--bin-include-dir">/ option on the command line.
 
 
 
-<sect>Input format<p>
+<sect>Input format<p><label id="input-format">
 
 <sect1>Assembler syntax<p>
 
@@ -426,20 +426,24 @@ Here are some examples for valid input lines:
 The assembler accepts
 
 <itemize>
-<item>all valid 6502 mnemonics when in 6502 mode (the default or after the
+<item>all valid 6502 mnemonics when in <ref id="6502-mode" name="6502 mode">
+      (the default or after the
       <tt><ref id=".P02" name=".P02"></tt> command was given).
-<item>all valid 6502 mnemonics plus a set of illegal instructions when in
-      <ref id="6502X-mode" name="6502X mode">.
-<item>all valid 6502DTV mnemonics when in 6502DTV mode (after the
+<item>all valid 6502 mnemonics, plus a set of illegal instructions, when in
+      <ref id="6502X-mode" name="6502X mode"> (after the
+      <tt><ref id=".P02X" name=".P02X"></tt> command was given).
+<item>all valid 6502DTV mnemonics when in <ref id="DTV-mode" name="DTV mode"> (after the
       <tt><ref id=".PDTV" name=".PDTV"></tt> command was given).
-<item>all valid 65SC02 mnemonics when in 65SC02 mode (after the
+<item>all valid 65SC02 mnemonics when in <ref id="65SC02-mode" name="65SC02 mode"> (after the
       <tt><ref id=".PSC02" name=".PSC02"></tt> command was given).
-<item>all valid 65C02 mnemonics when in 65C02 mode (after the
+<item>all valid 65C02 mnemonics when in <ref id="65C02-mode" name="65C02 mode"> (after the
       <tt><ref id=".PC02" name=".PC02"></tt> command was given).
-<item>all valid 65816 mnemonics when in 65816 mode (after the
+<item>all valid 65816 mnemonics when in <ref id="65816-mode" name="65816 mode"> (after the
       <tt><ref id=".P816" name=".P816"></tt> command was given).
-<item>all valid 4510 mnemonics when in 4510 mode (after the
+<item>all valid 4510 mnemonics when in <ref id="4510-mode" name="4510 mode"> (after the
       <tt><ref id=".P4510" name=".P4510"></tt> command was given).
+<item>all valid M740 mnemonics when in <ref id="M740-mode" name="M740 mode"> (after the
+      <tt><ref id=".PM740" name=".PM740"></tt> command was given).
 </itemize>
 
 On 6502-derived platforms the <tt/BRK/ instruction has an optional signature
@@ -451,8 +455,206 @@ byte. If omitted, the assembler will only produce only 1 byte.
                 brk     #$34            ; 2-bytes: $00 $34
 </verb></tscreen>
 
+<sect1>6502 mode<label id="6502-mode"><p>
 
-<sect1>65816 mode<p>
+In 6502 mode (which is the default) the assembler accepts all regular "legal"
+6502 mnemonics and addressing modes.
+
+<sect1>6502X mode<label id="6502X-mode"><p>
+
+6502X mode is an extension to the normal 6502 mode. In this mode, several
+mnemonics for undocumented instructions of the NMOS 6502 CPUs are accepted.
+
+Note: Since these instructions are undocumented, there are no official mnemonics
+for them.
+
+<itemize>
+<item><tt>ALR: A:=(A and #{imm})/2;</tt>
+<item><tt>ANC: A:= A and #{imm};</tt> Generates opcode &dollar;0B.
+<item><tt>ANE: A:= (A or CONST) and X and #{imm};</tt>
+<item><tt>ARR: A:=(A and #{imm})/2;</tt>
+<item><tt>AXS: X:=A and X-#{imm};</tt>
+<item><tt>DCP: {addr}:={addr}-1; A-{addr};</tt>
+<item><tt>ISC: {addr}:={addr}+1; A:=A-{addr};</tt>
+<item><tt>JAM:</tt>
+<item><tt>LAS: A,X,S:={addr} and S;</tt>
+<item><tt>LAX: A,X:={addr};</tt>
+<item><tt>NOP: #{imm}; zp; zp,x; abs; abs,x</tt>
+<item><tt>RLA: {addr}:={addr}rol; A:=A and {addr};</tt>
+<item><tt>RRA: {addr}:={addr}ror; A:=A adc {addr};</tt>
+<item><tt>SAX: {addr}:=A and X;</tt>
+<item><tt>SHA: {addr}:=A and X and {addr hi +1};</tt>
+<item><tt>SHX: {addr}:=X and {addr hi +1};</tt>
+<item><tt>SHY: {addr}:=Y and {addr hi +1};</tt>
+<item><tt>SLO: {addr}:={addr}*2; A:=A or {addr};</tt>
+<item><tt>SRE: {addr}:={addr}/2; A:=A xor {addr};</tt>
+<item><tt>TAS: {addr}:=A and X and {addr hi +1}; SP:=A and X;</tt>
+</itemize>
+
+
+<sect1>DTV mode<label id="DTV-mode"><p>
+
+The C64DTV CPU is based on the 6510, but adds some instructions, and does not
+support all undocumented instructions.
+
+<itemize>
+<item><tt>bra {rel}</tt> Generates opcode &dollar;12.
+<item><tt>sac #{imm}</tt> Generates opcode &dollar;32.
+<item><tt>sir #{imm}</tt> Generates opcode &dollar;42.
+</itemize>
+
+Supported undocumented instructions:
+
+<itemize>
+<item><tt>ALR: A:=(A and #{imm})/2;</tt>
+<item><tt>ANC: A:=A and #{imm};</tt> Generates opcode &dollar;0B.
+<item><tt>ARR: A:=(A and #{imm})/2;</tt>
+<item><tt>AXS: X:=A and X-#{imm};</tt>
+<item><tt>LAS: A,X,S:={addr} and S;</tt>
+<item><tt>LAX: A,X:={addr};</tt>
+<item><tt>NOP: #{imm}; zp; zp,x; abs; abs,x</tt>
+<item><tt>RLA: {addr}:={addr}rol; A:=A and {addr};</tt>
+<item><tt>RRA: {addr}:={addr}ror; A:=A adc {addr};</tt>
+<item><tt>SHX: {addr}:=X and {addr hi +1};</tt>
+<item><tt>SHY: {addr}:=y and {addr hi +1};</tt>
+</itemize>
+
+
+<sect1>65SC02 mode<label id="65SC02-mode"><p>
+
+65SC02 mode supports all regular 6502 instructions, plus the following:
+
+<tscreen><verb>
+$04  tsb zp
+$0c  tsb abs16
+$12  ora (zp)
+$14  trb zp
+$1a  inc
+$1c  trb abs16
+$32  and (zp)
+$34  bit zp, x
+$3a  dec
+$3c  bit abs16, x
+$52  eor (zp)
+$5a  phy
+$64  stz zp
+$72  adc (zp)
+$74  stz zp, x
+$7a  ply
+$7c  jmp (abs16, x)
+$80  bra rel8
+$89  bit #imm8
+$92  sta (zp)
+$9c  stz abs16
+$9e  stz abs16, x
+$b2  lda (zp)
+$d2  cmp (zp)
+$da  phx
+$f2  sbc (zp)
+$fa  plx
+</verb></tscreen>
+
+
+<sect1>65C02 mode<label id="65C02-mode"><p>
+
+65C02 mode supports all "official" W65C02 opcodes.
+
+The R65C02 adds bit manipulation instructions:
+
+<tscreen><verb>
+smbB zp         set bit in zp location
+rmbB zp         reset bit in zp location
+bbsB zp, rel8   branch if bit is set in zp location
+bbrB zp, rel8   branch if bit is reset in zp location
+</verb></tscreen>
+
+And the W65C02 adds those:
+
+<tscreen><verb>
+$cb  wai    wait for interrupt
+$db  stp    wait for reset
+</verb></tscreen>
+
+
+<sect1>4510 mode<label id="4510-mode"><p>
+
+The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX.
+It contains among other functions a slightly modified 65CE02/4502 CPU, to allow
+address mapping for 20 bits of address space (1 megabyte addressable area).
+
+The 4510 mode supports the complete (legal) 65CE02 instruction set, plus these
+three, which were changed/added:
+<tscreen><verb>
+$5c  map             "4-byte NOP reserved for future expansion" on 65CE02
+$cb  asw $1234       wai on W65C02
+$db  phz             stp on W65C02
+</verb></tscreen>
+
+As compared to the description of the CPU in the
+<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/c65manualupdated.txt.gz"
+name="C65 System Specification">
+<url url="https://raw.githubusercontent.com/MEGA65/c65-specifications/master/c65manualupdated.txt"
+name="(updated version)"> uses these changes:
+<itemize>
+<item><tt>LDA (d,SP),Y</tt> may also be written as <tt>LDA (d,S),Y</tt>
+(matching the 65816 notation).
+<item>All branch instruction allow now 16 bit offsets. To use a 16 bit
+branch you have to prefix these with an "L" (e.g. "<tt>LBNE</tt>" instead of
+"<tt>BNE</tt>"). This might change at a later implementation of the assembler.
+</itemize>
+
+For more information about the Commodore C65/C64DX and the 4510 CPU, see
+<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/"> and
+<url url="https://en.wikipedia.org/wiki/Commodore_65" name="Wikipedia">.
+
+
+<sect1>HUC6280 mode<label id="HUC6280-mode"><p>
+
+The HUC6280 is a superset of the R65C02. It adds some other instructions:
+
+<tscreen><verb>
+$02  sxy
+$03  st0 #{imm}
+$13  st1 #{imm}
+$22  sax
+$23  st2 #{imm}
+$42  say
+$43  tma #{imm}
+$44  bsr {rel}
+$53  tam #{imm}
+$54  csl
+$62  cla
+$73  tii {addr}, {addr}, {addr}
+$82  clx
+$83  tst #{imm}, {zp}
+$82  clx
+$83  tst #{imm}, {zp}
+$93  tst #{imm}, {addr}
+$a3  tst #{imm}, {zp}, x
+$b3  tst #{imm}, {addr}, x
+$c2  cly
+$c3  tdd {addr}, {addr}, {addr}
+$d3  tin {addr}, {addr}, {addr}
+$d4  csh
+$e3  tia {addr}, {addr}, {addr}
+$f3  tai {addr}, {addr}, {addr}
+$f4  set
+</verb></tscreen>
+
+Note that this CPU does not implement <tt>wai</tt> and <tt>stp</tt>.
+
+
+<sect1>M740 mode<label id="M740-mode"><p>
+
+The M740 is a microcontroller by Mitsubishi, which was marketed for embedded
+devices in the mid 80s. It is a superset of 6502, and a subset of 65SC02, plus
+some new instructions.
+
+For more information about the M740 Controllers, see
+<url url="https://en.wikipedia.org/wiki/Mitsubishi_740" name="Wikipedia">.
+
+
+<sect1>65816 mode<label id="65816-mode"><p><p>
 
 In 65816 mode, several aliases are accepted, in addition to the official
 mnemonics:
@@ -480,55 +682,6 @@ or two far addresses whose high byte will be used.
 </verb></tscreen>
 
 
-<sect1>6502X mode<label id="6502X-mode"><p>
-
-6502X mode is an extension to the normal 6502 mode. In this mode, several
-mnemonics for illegal instructions of the NMOS 6502 CPUs are accepted. Since
-these instructions are illegal, there are no official mnemonics for them. The
-unofficial ones are taken from <url
-url="http://www.oxyron.de/html/opcodes02.html">. Please note that only the
-ones marked as "stable" are supported. The following table uses information
-from the mentioned web page, for more information, see there.
-
-<itemize>
-<item><tt>ALR: A:=(A and #{imm})/2;</tt>
-<item><tt>ANC: A:=A and #{imm};</tt> Generates opcode &dollar;0B.
-<item><tt>ARR: A:=(A and #{imm})/2;</tt>
-<item><tt>AXS: X:=A and X-#{imm};</tt>
-<item><tt>DCP: {adr}:={adr}-1; A-{adr};</tt>
-<item><tt>ISC: {adr}:={adr}+1; A:=A-{adr};</tt>
-<item><tt>LAS: A,X,S:={adr} and S;</tt>
-<item><tt>LAX: A,X:={adr};</tt>
-<item><tt>RLA: {adr}:={adr}rol; A:=A and {adr};</tt>
-<item><tt>RRA: {adr}:={adr}ror; A:=A adc {adr};</tt>
-<item><tt>SAX: {adr}:=A and X;</tt>
-<item><tt>SLO: {adr}:={adr}*2; A:=A or {adr};</tt>
-<item><tt>SRE: {adr}:={adr}/2; A:=A xor {adr};</tt>
-</itemize>
-
-
-<sect1>4510 mode<p>
-
-The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX.
-It contains among other functions a slightly modified 65CE02/4502 CPU, to allow
-address mapping for 20 bits of address space (1 megabyte addressable area).
-As compared to the description of the CPU in the
-<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/c65manualupdated.txt.gz"
-name="C65 System Specification">
-<url url="https://raw.githubusercontent.com/MEGA65/c65-specifications/master/c65manualupdated.txt"
-name="(updated version)"> uses these changes:
-<itemize>
-<item><tt>LDA (d,SP),Y</tt> may also be written as <tt>LDA (d,S),Y</tt>
-(matching the 65816 notataion).
-<item>All branch instruction allow now 16 bit offsets. To use a 16 bit
-branch you have to prefix these with an "L" (e.g. "<tt>LBNE</tt>" instead of
-"<tt>BNE</tt>"). This might change at a later implementation of the assembler.
-</itemize>
-For more information about the Commodore C65/C64DX and the 4510 CPU, see
-<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/"> and
-<url url="https://en.wikipedia.org/wiki/Commodore_65" name="Wikipedia">.
-
-
 <sect1>sweet16 mode<label id="sweet16-mode"><p>
 
 SWEET 16 is an interpreter for a pseudo 16 bit CPU written by Steve Wozniak
@@ -3264,6 +3417,12 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".CHARMAP" name=".CH
   (see <tt><ref id=".PDTV" name=".PDTV"></tt> command).
 
 
+<sect1><tt>.IFPM740</tt><label id=".IFPM740"><p>
+
+  Conditional assembly: Check if the assembler is currently in M740 mode
+  (see <tt><ref id=".PM740" name=".PM740"></tt> command).
+
+
 <sect1><tt>.IFPSC02</tt><label id=".IFPSC02"><p>
 
   Conditional assembly: Check if the assembler is currently in 65SC02 mode
@@ -3694,6 +3853,14 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
   See: <tt><ref id=".P02" name=".P02"></tt>
 
 
+<sect1><tt>.PM740</tt><label id=".PM740"><p>
+
+  Enable the M740 instruction set. This is a superset of the 6502
+  instruction set.
+
+  See: <tt><ref id=".P02" name=".P02"></tt>
+
+
 <sect1><tt>.POPCHARMAP</tt><label id=".POPCHARMAP"><p>
 
   Pop the last character mapping from the stack, and activate it.
@@ -4028,7 +4195,7 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
   Switch the CPU instruction set. The command is followed by a string that
   specifies the CPU. Possible values are those that can also be supplied to
   the <tt><ref id="option--cpu" name="--cpu"></tt> command line option,
-  namely: 6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, 4510 and HuC6280.
+  namely: 6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, 4510, HuC6280 and m740.
 
   See: <tt><ref id=".CPU" name=".CPU"></tt>,
        <tt><ref id=".IFP02" name=".IFP02"></tt>,
@@ -4036,12 +4203,14 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
        <tt><ref id=".IFPDTV" name=".IFPDTV"></tt>,
        <tt><ref id=".IFP816" name=".IFP816"></tt>,
        <tt><ref id=".IFPC02" name=".IFPC02"></tt>,
+       <tt><ref id=".IFPM740" name=".IFPM740"></tt>,
        <tt><ref id=".IFPSC02" name=".IFPSC02"></tt>,
        <tt><ref id=".P02" name=".P02"></tt>,
        <tt><ref id=".P02X" name=".P02X"></tt>,
        <tt><ref id=".P816" name=".P816"></tt>,
        <tt><ref id=".P4510" name=".P4510"></tt>,
        <tt><ref id=".PC02" name=".PC02"></tt>,
+       <tt><ref id=".PM740" name=".PM740"></tt>,
        <tt><ref id=".PSC02" name=".PSC02"></tt>
 
 
@@ -4780,6 +4949,7 @@ each supported CPU a constant similar to
     CPU_HUC6280
     CPU_4510
     CPU_6502DTV
+    CPU_M740
 </verb></tscreen>
 
 is defined. These constants may be used to determine the exact type of the
@@ -4795,6 +4965,7 @@ another constant is defined:
     CPU_ISET_HUC6280
     CPU_ISET_4510
     CPU_ISET_6502DTV
+    CPU_ISET_M740
 </verb></tscreen>
 
 The value read from the <tt/<ref id=".CPU" name=".CPU">/ pseudo variable may
@@ -4822,6 +4993,7 @@ it is possible to determine if the
 instruction is supported, which is the case for the 65SC02, 65C02 and 65816
 CPUs (the latter two are upwards compatible to the 65SC02).
 
+see section <ref id="6502-mode" name="6502 format"> and following.
 
 <sect1><tt>.MACPACK module</tt><p>
 
diff --git a/doc/da65.sgml b/doc/da65.sgml
index 94fbfbd29..b72cd9b66 100644
--- a/doc/da65.sgml
+++ b/doc/da65.sgml
@@ -118,11 +118,13 @@ Here is a description of all the command line options:
   <item>65816
   <item>huc6280
   <item>4510
+  <item>m740
   </itemize>
 
   6502x is for the NMOS 6502 with unofficial opcodes. 6502dtv is for the
   emulated CPU of the C64DTV device. huc6280 is the CPU of the PC engine.
-  4510 is the CPU of the Commodore C65. 65816 is the CPU of the SNES.
+  4510 is the CPU of the Commodore C65. 65816 is the CPU of the SNES. M740 is a
+  Microcontroller by Mitsubishi.
 
 
   <label id="option--formfeeds">
diff --git a/src/ca65/condasm.c b/src/ca65/condasm.c
index 60e8ab0c1..a65fbebba 100644
--- a/src/ca65/condasm.c
+++ b/src/ca65/condasm.c
@@ -444,6 +444,16 @@ void DoConditionals (void)
                 CalcOverallIfCond ();
                 break;
 
+            case TOK_IFPM740:
+                D = AllocIf (".IFPM740", 1);
+                NextTok ();
+                if (IfCond) {
+                    SetIfCond (D, GetCPU() == CPU_M740);
+                }
+                ExpectSep ();
+                CalcOverallIfCond ();
+                break;
+
             case TOK_IFPSC02:
                 D = AllocIf (".IFPSC02", 1);
                 NextTok ();
@@ -500,6 +510,7 @@ int CheckConditionals (void)
         case TOK_IFP816:
         case TOK_IFPC02:
         case TOK_IFPDTV:
+        case TOK_IFPM740:
         case TOK_IFPSC02:
         case TOK_IFREF:
             DoConditionals ();
diff --git a/src/ca65/ea65.c b/src/ca65/ea65.c
index 5bd2ba82b..da11b268a 100644
--- a/src/ca65/ea65.c
+++ b/src/ca65/ea65.c
@@ -186,10 +186,11 @@ void GetEA (EffAddr* A)
 
         /* Remaining stuff:
         **
-        ** adr
-        ** adr,x
-        ** adr,y
-        ** adr,s
+        ** addr
+        ** addr, x
+        ** addr, y
+        ** addr, s
+        ** addr, relative addr
         */
         A->Expr = Expression ();
 
@@ -214,7 +215,9 @@ void GetEA (EffAddr* A)
                     break;
 
                 default:
-                    Error ("Syntax error");
+                    /* FIXME: syntax error if not zp, ind */
+                    A->AddrModeSet = AM65_ZP_REL;
+                    break;
 
             }
 
diff --git a/src/ca65/instr.c b/src/ca65/instr.c
index c7a68006c..f94740dcb 100644
--- a/src/ca65/instr.c
+++ b/src/ca65/instr.c
@@ -85,6 +85,12 @@ static void PutBlockTransfer (const InsDesc* Ins);
 static void PutBitBranch (const InsDesc* Ins);
 /* Handle 65C02 branch on bit condition */
 
+static void PutBitBranch_m740 (const InsDesc* Ins);
+/* Handle m740 branch on bit condition */
+
+static void PutLDM_m740 (const InsDesc* Ins);
+/* Handle m740 LDM instruction */
+
 static void PutREP (const InsDesc* Ins);
 /* Emit a REP instruction, track register sizes */
 
@@ -132,6 +138,11 @@ static void PutJSR816 (const InsDesc* Ins);
 ** Allowing the long_jsr_jmp_rts feature to permit a long JSR.
 */
 
+static void PutJSR_m740 (const InsDesc* Ins);
+/* Handle the JSR instruction for the m740
+** Allowing the special page feature.
+*/
+
 static void PutRTS (const InsDesc* Ins attribute ((unused)));
 /* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if
 ** the enclosing scope is FAR, but only if the long_jsr_jmp_rts feature applies.
@@ -1047,7 +1058,126 @@ static const struct {
     }
 };
 
+/* CAUTION: in the pdf $1a is dec a, and $3a is inc a - if that is really the case,
+ * the table below (and the handler) should be fixed and this notice removed */
 
+/* Instruction table for the m740 CPU */
+static const struct {
+    unsigned Count;
+    InsDesc  Ins[106];
+} InsTabm740 = {
+    sizeof (InsTabm740.Ins) / sizeof (InsTabm740.Ins[0]),
+    {
+/* BEGIN SORTED.SH */
+        { "ADC",  0x0080A26C, 0x60, 0, PutAll },
+        { "AND",  0x0080A26C, 0x20, 0, PutAll },
+        { "ASL",  0x0000006e, 0x02, 1, PutAll },
+        { "BBC0", 0x10000002, 0x13, 10, PutBitBranch_m740 },
+        { "BBC1", 0x10000002, 0x33, 10, PutBitBranch_m740 },
+        { "BBC2", 0x10000002, 0x53, 10, PutBitBranch_m740 },
+        { "BBC3", 0x10000002, 0x73, 10, PutBitBranch_m740 },
+        { "BBC4", 0x10000002, 0x93, 10, PutBitBranch_m740 },
+        { "BBC5", 0x10000002, 0xb3, 10, PutBitBranch_m740 },
+        { "BBC6", 0x10000002, 0xd3, 10, PutBitBranch_m740 },
+        { "BBC7", 0x10000002, 0xf3, 10, PutBitBranch_m740 },
+        { "BBS0", 0x10000002, 0x03, 10, PutBitBranch_m740 },
+        { "BBS1", 0x10000002, 0x23, 10, PutBitBranch_m740 },
+        { "BBS2", 0x10000002, 0x43, 10, PutBitBranch_m740 },
+        { "BBS3", 0x10000002, 0x63, 10, PutBitBranch_m740 },
+        { "BBS4", 0x10000002, 0x83, 10, PutBitBranch_m740 },
+        { "BBS5", 0x10000002, 0xa3, 10, PutBitBranch_m740 },
+        { "BBS6", 0x10000002, 0xc3, 10, PutBitBranch_m740 },
+        { "BBS7", 0x10000002, 0xe3, 10, PutBitBranch_m740 },
+        { "BCC",  0x00020000, 0x90, 0, PutPCRel8 },
+        { "BCS",  0x00020000, 0xb0, 0, PutPCRel8 },
+        { "BEQ",  0x00020000, 0xf0, 0, PutPCRel8 },
+        { "BIT",  0x0000000C, 0x00, 2, PutAll },
+        { "BMI",  0x00020000, 0x30, 0, PutPCRel8 },
+        { "BNE",  0x00020000, 0xd0, 0, PutPCRel8 },
+        { "BPL",  0x00020000, 0x10, 0, PutPCRel8 },
+        { "BRA",  0x00020000, 0x80, 0, PutPCRel8 },
+        { "BRK",  0x00000001, 0x00, 0, PutAll },
+        { "BVC",  0x00020000, 0x50, 0, PutPCRel8 },
+        { "BVS",  0x00020000, 0x70, 0, PutPCRel8 },
+        { "CLB0", 0x00000006, 0x1b, 10, PutAll },
+        { "CLB1", 0x00000006, 0x3b, 10, PutAll },
+        { "CLB2", 0x00000006, 0x5b, 10, PutAll },
+        { "CLB3", 0x00000006, 0x7b, 10, PutAll },
+        { "CLB4", 0x00000006, 0x9b, 10, PutAll },
+        { "CLB5", 0x00000006, 0xbb, 10, PutAll },
+        { "CLB6", 0x00000006, 0xdb, 10, PutAll },
+        { "CLB7", 0x00000006, 0xfb, 10, PutAll },
+        { "CLC",  0x00000001, 0x18, 0, PutAll },
+        { "CLD",  0x00000001, 0xd8, 0, PutAll },
+        { "CLI",  0x00000001, 0x58, 0, PutAll },
+        { "CLT",  0x00000001, 0x12, 0, PutAll },
+        { "CLV",  0x00000001, 0xb8, 0, PutAll },
+        { "CMP",  0x0080A26C, 0xc0, 0, PutAll },
+        { "COM",  0x00000004, 0x44, 1, PutAll },
+        { "CPX",  0x0080000C, 0xe0, 1, PutAll },
+        { "CPY",  0x0080000C, 0xc0, 1, PutAll },
+        { "DEC",  0x0000006F, 0x00, 3, PutAll },
+        { "DEX",  0x00000001, 0xca, 0, PutAll },
+        { "DEY",  0x00000001, 0x88, 0, PutAll },
+        { "EOR",  0x0080A26C, 0x40, 0, PutAll },
+        { "FST",  0x00000001, 0xe2, 0, PutAll },
+        { "INC",  0x0000006f, 0x00, 4, PutAll },
+        { "INX",  0x00000001, 0xe8, 0, PutAll },
+        { "INY",  0x00000001, 0xc8, 0, PutAll },
+        { "JMP",  0x00000C08, 0x00, 12, PutAll },
+        { "JSR",  0x20000408, 0x00, 0, PutJSR_m740 },
+        { "LDA",  0x0080A26C, 0xa0, 0, PutAll },
+        { "LDM",  0x10000000, 0x3c, 0, PutLDM_m740 },
+        { "LDX",  0x0080030C, 0xa2, 1, PutAll },
+        { "LDY",  0x0080006C, 0xa0, 1, PutAll },
+        { "LSR",  0x0000006F, 0x42, 1, PutAll },
+        { "NOP",  0x00000001, 0xea, 0, PutAll },
+        { "ORA",  0x0080A26C, 0x00, 0, PutAll },
+        { "PHA",  0x00000001, 0x48, 0, PutAll },
+        { "PHP",  0x00000001, 0x08, 0, PutAll },
+        { "PLA",  0x00000001, 0x68, 0, PutAll },
+        { "PLP",  0x00000001, 0x28, 0, PutAll },
+        { "RMB0", 0x00000006, 0x1b, 10, PutAll },
+        { "RMB1", 0x00000006, 0x3b, 10, PutAll },
+        { "RMB2", 0x00000006, 0x5b, 10, PutAll },
+        { "RMB3", 0x00000006, 0x7b, 10, PutAll },
+        { "RMB4", 0x00000006, 0x9b, 10, PutAll },
+        { "RMB5", 0x00000006, 0xbb, 10, PutAll },
+        { "RMB6", 0x00000006, 0xdb, 10, PutAll },
+        { "RMB7", 0x00000006, 0xfb, 10, PutAll },
+        { "ROL",  0x0000006F, 0x22, 1, PutAll },
+        { "ROR",  0x0000006F, 0x62, 1, PutAll },
+        { "RRF",  0x00000004, 0x82, 6, PutAll },
+        { "RTI",  0x00000001, 0x40, 0, PutAll },
+        { "RTS",  0x00000001, 0x60, 0, PutAll },
+        { "SBC",  0x0080A26C, 0xe0, 0, PutAll },
+        { "SEB0", 0x00000006, 0x0b, 10, PutAll },
+        { "SEB1", 0x00000006, 0x2b, 10, PutAll },
+        { "SEB2", 0x00000006, 0x4b, 10, PutAll },
+        { "SEB3", 0x00000006, 0x6b, 10, PutAll },
+        { "SEB4", 0x00000006, 0x8b, 10, PutAll },
+        { "SEB5", 0x00000006, 0xab, 10, PutAll },
+        { "SEB6", 0x00000006, 0xcb, 10, PutAll },
+        { "SEB7", 0x00000006, 0xeb, 10, PutAll },
+        { "SEC",  0x00000001, 0x38, 0, PutAll },
+        { "SED",  0x00000001, 0xf8, 0, PutAll },
+        { "SEI",  0x00000001, 0x78, 0, PutAll },
+        { "SET",  0x00000001, 0x32, 0, PutAll },
+        { "SLW",  0x00000001, 0xC2, 0, PutAll },
+        { "STA",  0x0000A26C, 0x80, 0, PutAll },
+        { "STP",  0x00000001, 0x42, 0, PutAll },
+        { "STX",  0x0000010c, 0x82, 1, PutAll },
+        { "STY",  0x0000002c, 0x80, 1, PutAll },
+        { "TAX",  0x00000001, 0xaa, 0, PutAll },
+        { "TAY",  0x00000001, 0xa8, 0, PutAll },
+        { "TST",  0x00000004, 0x64, 1, PutAll },
+        { "TSX",  0x00000001, 0xba, 0, PutAll },
+        { "TXA",  0x00000001, 0x8a, 0, PutAll },
+        { "TXS",  0x00000001, 0x9a, 0, PutAll },
+        { "TYA",  0x00000001, 0x98, 0, PutAll }
+/* END SORTED.SH */
+    }
+};
 
 /* An array with instruction tables */
 static const InsTable* InsTabs[CPU_COUNT] = {
@@ -1060,86 +1190,93 @@ static const InsTable* InsTabs[CPU_COUNT] = {
     (const InsTable*) &InsTab65816,
     (const InsTable*) &InsTabSweet16,
     (const InsTable*) &InsTabHuC6280,
-    0,                                  /* Mitsubishi 740 */
+    (const InsTable*) &InsTabm740,           /* Mitsubishi 740 */
     (const InsTable*) &InsTab4510,
 };
 const InsTable* InsTab = (const InsTable*) &InsTab6502;
 
 /* Table to build the effective 65xx opcode from a base opcode and an
 ** addressing mode. (The value in the table is ORed with the base opcode)
+** NOTE: each table has one entry per addressing mode!
 */
-static unsigned char EATab[12][AM65I_COUNT] = {
-    {   /* Table 0 */
+static unsigned char EATab[14][AM65I_COUNT] = {
+    {   /* Table 0 (sec, sed, seo, set, slw, sta, stp, tax, tay, tsx, txa, txs, tya) */
         0x00, 0x00, 0x05, 0x0D, 0x0F, 0x15, 0x1D, 0x1F,
         0x00, 0x19, 0x12, 0x00, 0x07, 0x11, 0x17, 0x01,
         0x00, 0x00, 0x00, 0x03, 0x13, 0x09, 0x00, 0x09,
-        0x00, 0x00, 0x00, 0x00
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00
     },
-    {   /* Table 1 */
+    {   /* Table 1 (rol, ror, stx, sty, tst) */
         0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
         0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x80, 0x00
+        0x00, 0x00, 0x80, 0x00, 0x00, 0x00
     },
-    {   /* Table 2 */
+    {   /* Table 2 (bit) */
         0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00
     },
-    {   /* Table 3 */
+    {   /* Table 3 (dec, dea) */
         0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00
     },
-    {   /* Table 4 */
+    {   /* Table 4 (inc) */
         0x1A, 0x1A, 0xE6, 0xEE, 0x00, 0xF6, 0xFE, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00
     },
-    {   /* Table 5 */
+    {   /* Table 5 (stz) */
         0x00, 0x00, 0x60, 0x98, 0x00, 0x70, 0x9E, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00
     },
-    {   /* Table 6 */
+    {   /* Table 6 (jmp, rrf) */
         0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
         0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x90, 0x00
+        0x00, 0x00, 0x90, 0x00, 0x00, 0x00
     },
-    {   /* Table 7 (Subroutine opcodes) */
+    {   /* Table 7 (jsr) */
         0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
         0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00
     },
     {   /* Table 8 */
         0x00, 0x40, 0x01, 0x41, 0x00, 0x09, 0x49, 0x00,
         0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00
     },
-    {   /* Table 9 */
+    {   /* Table 9 (dew, inw) */
         0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x30, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00
     },
-    {   /* Table 10 (NOPs) */
+    {   /* Table 10 (NOPs, clbX, sebX) */
         0xea, 0x00, 0x04, 0x0c, 0x00, 0x14, 0x1c, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
-        0x00, 0x00, 0x00, 0x00
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00
     },
     {   /* Table 11 (LAX) */
         0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
         0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
-        0x00, 0x00, 0x80, 0x00
+        0x00, 0x00, 0x80, 0x00, 0x00, 0x00
+    },
+    {   /* Table 12 (m740: JMP) */
+        0x00, 0x00, 0x00, 0x4c, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0xb2, 0x6c, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00
     },
 };
 
@@ -1156,6 +1293,7 @@ static unsigned char Sweet16EATab[2][AMSW16I_COUNT] = {
 };
 
 /* Table that encodes the additional bytes for each 65xx instruction */
+/* NOTE: one entry per addressing mode! */
 unsigned char ExtBytes[AM65I_COUNT] = {
     0,          /* Implicit */
     0,          /* Accu */
@@ -1185,6 +1323,8 @@ unsigned char ExtBytes[AM65I_COUNT] = {
     7,          /* Block transfer (HuC6280) */
     2,          /* Absolute Indirect long */
     2,          /* Immidiate word */
+    2,          /* Direct, Relative short */
+    1,          /* Special Page */
 };
 
 /* Table that encodes the additional bytes for each SWEET16 instruction */
@@ -1361,6 +1501,20 @@ static void EmitCode (EffAddr* A)
 }
 
 
+static void PutLDM_m740 (const InsDesc* Ins)
+{
+    EffAddr A;
+    /* Evaluate the addressing mode */
+    if (EvalEA (Ins, &A) == 0) {
+        /* An error occurred */
+        return;
+    }
+    Emit0 (Ins->BaseCode);
+    EmitByte (A.Expr);
+    Consume (TOK_HASH, "'#' expected");
+    EmitByte (Expression ());
+}
+
 
 static long PutImmed8 (const InsDesc* Ins)
 /* Parse and emit an immediate 8 bit instruction. Return the value of the
@@ -1481,6 +1635,42 @@ static void PutBitBranch (const InsDesc* Ins)
     EmitSigned (GenBranchExpr (1), 1);
 }
 
+static void PutBitBranch_m740 (const InsDesc* Ins)
+/* Handle m740 branch on bit condition */
+{
+    EffAddr A;
+
+    /* Evaluate the addressing mode used */
+    GetEA(&A);
+
+    /* From the possible addressing modes, remove the ones that are invalid
+    ** for this instruction or CPU.
+    */
+    A.AddrModeSet &= Ins->AddrMode;
+
+    /* Check if we have any adressing modes left */
+    if (A.AddrModeSet == 0) {
+        Error ("Illegal addressing mode");
+        return;
+    }
+    A.AddrMode    = BitFind (A.AddrModeSet);
+
+    A.Opcode = Ins->BaseCode;
+
+    if (A.AddrMode == AM65I_ACCU) {
+        /* Accu */
+        Emit0 (A.Opcode);
+        ConsumeComma ();
+        EmitSigned (GenBranchExpr (2), 1);
+    } else if (A.AddrMode == AM65I_ZP_REL) {
+        /* FIXME: hacky, the comma was already consumed here */
+        A.Opcode += 0x04;
+        /* Zeropage */
+        Emit0 (A.Opcode);
+        EmitByte (A.Expr);
+        EmitSigned (GenBranchExpr (1), 1);
+    }
+}
 
 
 static void PutREP (const InsDesc* Ins)
@@ -1584,7 +1774,6 @@ static void PutTMAn (const InsDesc* Ins)
 ** an immediate argument.
 */
 {
-    /* Emit the TMA opcode itself */
     Emit0 (0x43);
 
     /* Emit the argument, which is the opcode from the table */
@@ -1640,10 +1829,8 @@ static void PutJMP (const InsDesc* Ins)
 */
 {
     EffAddr A;
-
     /* Evaluate the addressing mode used */
     if (EvalEA (Ins, &A)) {
-
         /* Check for indirect addressing */
         if ((A.AddrModeBit & AM65_ABS_IND) && (CPU < CPU_65SC02) && (RelaxChecks == 0)) {
 
@@ -1701,6 +1888,57 @@ static void PutJSR816 (const InsDesc* Ins)
 }
 
 
+static void PutJSR_m740 (const InsDesc* Ins)
+/* Handle a JSR instruction for m740 */
+{
+    EffAddr A;
+
+    /* Evaluate the addressing mode used */
+    GetEA (&A);
+
+    /* From the possible addressing modes, remove the ones that are invalid
+    ** for this instruction or CPU.
+    */
+    A.AddrModeSet &= Ins->AddrMode;
+
+    /* Check if we have any adressing modes left */
+    if (A.AddrModeSet == 0) {
+        Error ("Illegal addressing mode");
+        return;
+    }
+    A.AddrMode    = BitFind (A.AddrModeSet);
+
+    /* Build the opcode */
+    A.Opcode = Ins->BaseCode;
+
+    switch (A.AddrMode) {
+        case AM65I_DIR_IND:
+            A.Opcode = 0x02;
+            Emit1 (A.Opcode, A.Expr);
+            break;
+        case AM65I_ABS:
+            /* If we have an expression and it's const, get it's value */
+            if (A.Expr) {
+                long Val = -1;
+                if (IsConstExpr (A.Expr, &Val)) {
+                    if ((Val & 0xff00) == 0xff00) {
+                        /* direct page */
+                        A.Opcode = 0x22;
+                        Emit0 (A.Opcode);
+                        EmitByte(GenByteExpr(A.Expr));
+                        return;
+                    }
+                }
+            }
+            A.Opcode = 0x20;
+            Emit2 (A.Opcode, A.Expr);
+            break;
+        default:
+            Internal ("Invalid Opcode 0x%02x", A.Opcode);
+    }
+
+}
+
 
 static void PutRTS (const InsDesc* Ins attribute ((unused)))
 /* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if
diff --git a/src/ca65/instr.h b/src/ca65/instr.h
index fe18d2110..8e0900c77 100644
--- a/src/ca65/instr.h
+++ b/src/ca65/instr.h
@@ -58,34 +58,36 @@
 ** When assembling for the 6502 or 65C02, all addressing modes that are not
 ** available on these CPUs are removed before doing any checks.
 */
-#define AM65_IMPLICIT           0x00000003UL
-#define AM65_ACCU               0x00000002UL
-#define AM65_DIR                0x00000004UL
-#define AM65_ABS                0x00000008UL
-#define AM65_ABS_LONG           0x00000010UL
-#define AM65_DIR_X              0x00000020UL
-#define AM65_ABS_X              0x00000040UL
-#define AM65_ABS_LONG_X         0x00000080UL
-#define AM65_DIR_Y              0x00000100UL
-#define AM65_ABS_Y              0x00000200UL
-#define AM65_DIR_IND            0x00000400UL
-#define AM65_ABS_IND            0x00000800UL
-#define AM65_DIR_IND_LONG       0x00001000UL
-#define AM65_DIR_IND_Y          0x00002000UL
-#define AM65_DIR_IND_LONG_Y     0x00004000UL
-#define AM65_DIR_X_IND          0x00008000UL
-#define AM65_ABS_X_IND          0x00010000UL
-#define AM65_REL                0x00020000UL
-#define AM65_REL_LONG           0x00040000UL
-#define AM65_STACK_REL          0x00080000UL
-#define AM65_STACK_REL_IND_Y    0x00100000UL
+#define AM65_IMPLICIT           0x00000003UL /* IMP */
+#define AM65_ACCU               0x00000002UL /* A, BIT, A */
+#define AM65_DIR                0x00000004UL /* ZP, BIT, ZP */
+#define AM65_ABS                0x00000008UL /* ABS */
+#define AM65_ABS_LONG           0x00000010UL /* -- */
+#define AM65_DIR_X              0x00000020UL /* ZP,X */
+#define AM65_ABS_X              0x00000040UL /* ABS, X */
+#define AM65_ABS_LONG_X         0x00000080UL /* -- */
+#define AM65_DIR_Y              0x00000100UL /* ZP, Y */
+#define AM65_ABS_Y              0x00000200UL /* ABS, Y */
+#define AM65_DIR_IND            0x00000400UL /* (ZP IND) */
+#define AM65_ABS_IND            0x00000800UL /* (IND) */
+#define AM65_DIR_IND_LONG       0x00001000UL /* -- */
+#define AM65_DIR_IND_Y          0x00002000UL /* IND, Y */
+#define AM65_DIR_IND_LONG_Y     0x00004000UL /* -- */
+#define AM65_DIR_X_IND          0x00008000UL /* IND, X */
+#define AM65_ABS_X_IND          0x00010000UL /* -- */
+#define AM65_REL                0x00020000UL /* REL */
+#define AM65_REL_LONG           0x00040000UL /* -- */
+#define AM65_STACK_REL          0x00080000UL /* SP ? */
+#define AM65_STACK_REL_IND_Y    0x00100000UL /* ? */
 #define AM65_IMM_ACCU           0x00200000UL
 #define AM65_IMM_INDEX          0x00400000UL
-#define AM65_IMM_IMPLICIT       0x00800000UL
-#define AM65_BLOCKMOVE          0x01000000UL
-#define AM65_BLOCKXFER          0x02000000UL
-#define AM65_ABS_IND_LONG       0x04000000UL
+#define AM65_IMM_IMPLICIT       0x00800000UL /* IMM */
+#define AM65_BLOCKMOVE          0x01000000UL /* -- */
+#define AM65_BLOCKXFER          0x02000000UL /* -- */
+#define AM65_ABS_IND_LONG       0x04000000UL /* -- */
 #define AM65_IMM_IMPLICIT_WORD  0x08000000UL /* PHW #$1234 (4510 only) */
+#define AM65_ZP_REL             0x10000000UL /* ZP, REL (m740) */
+#define AM65_SPECIAL_PAGE       0x20000000UL /* $FFxx (m740) */
 
 /* Bitmask for all ZP operations that have correspondent ABS ops */
 #define AM65_SET_ZP     (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
@@ -106,11 +108,37 @@
 #define AM65_ALL_IMM    (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT | AM65_IMM_IMPLICIT_WORD)
 
 /* Bit numbers and count */
-#define AM65I_IMM_ACCU          21
-#define AM65I_IMM_INDEX         22
-#define AM65I_IMM_IMPLICIT      23
-#define AM65I_IMM_IMPLICIT_WORD 27
-#define AM65I_COUNT             28
+#define AM65I_IMPLICIT           0
+#define AM65I_ACCU               1
+#define AM65I_DIR                2
+#define AM65I_ABS                3
+#define AM65I_ABS_LONG           4
+#define AM65I_DIR_X              5
+#define AM65I_ABS_X              6
+#define AM65I_ABS_LONG_X         7
+#define AM65I_DIR_Y              8
+#define AM65I_ABS_Y              9
+#define AM65I_DIR_IND            10
+#define AM65I_ABS_IND            11
+#define AM65I_DIR_IND_LONG       12
+#define AM65I_DIR_IND_Y          13
+#define AM65I_DIR_IND_LONG_Y     14
+#define AM65I_DIR_X_IND          15
+#define AM65I_ABS_X_IND          16
+#define AM65I_REL                17
+#define AM65I_REL_LONG           18
+#define AM65I_STACK_REL          19
+#define AM65I_STACK_REL_IND_Y    20
+#define AM65I_IMM_ACCU           21
+#define AM65I_IMM_INDEX          22
+#define AM65I_IMM_IMPLICIT       23
+#define AM65I_BLOCKMOVE          24
+#define AM65I_BLOCKXFER          25
+#define AM65I_ABS_IND_LONG       26
+#define AM65I_IMM_IMPLICIT_WORD  27
+#define AM65I_ZP_REL             28
+#define AM65I_SPECIAL_PAGE       29
+#define AM65I_COUNT              30
 
 
 
diff --git a/src/ca65/pseudo.c b/src/ca65/pseudo.c
index 37dcd78da..6cad9ed51 100644
--- a/src/ca65/pseudo.c
+++ b/src/ca65/pseudo.c
@@ -1563,7 +1563,7 @@ static void DoP02 (void)
 
 
 static void DoP02X (void)
-/* Switch to 6502 CPU */
+/* Switch to 6502X CPU */
 {
     SetCPU (CPU_6502X);
 }
@@ -1602,6 +1602,14 @@ static void DoPDTV (void)
 
 
 
+static void DoPM740 (void)
+/* Switch to M740 CPU */
+{
+    SetCPU (CPU_M740);
+}
+
+
+
 static void DoPageLength (void)
 /* Set the page length for the listing */
 {
@@ -2146,6 +2154,7 @@ static CtrlDesc CtrlCmdTab [] = {
     { ccKeepToken,      DoConditionals  },      /* .IFP816 */
     { ccKeepToken,      DoConditionals  },      /* .IFPC02 */
     { ccKeepToken,      DoConditionals  },      /* .IFPDTV */
+    { ccKeepToken,      DoConditionals  },      /* .IFPM740 */
     { ccKeepToken,      DoConditionals  },      /* .IFPSC02 */
     { ccKeepToken,      DoConditionals  },      /* .IFREF */
     { ccNone,           DoImport        },      /* .IMPORT */
@@ -2182,6 +2191,7 @@ static CtrlDesc CtrlCmdTab [] = {
     { ccNone,           DoUnexpected    },      /* .PARAMCOUNT */
     { ccNone,           DoPC02          },      /* .PSC02 */
     { ccNone,           DoPDTV          },      /* .PDTV */
+    { ccNone,           DoPM740         },      /* .PM740 */
     { ccNone,           DoPopCharmap    },      /* .POPCHARMAP */
     { ccNone,           DoPopCPU        },      /* .POPCPU */
     { ccNone,           DoPopSeg        },      /* .POPSEG */
diff --git a/src/ca65/scanner.c b/src/ca65/scanner.c
index 157702897..0d90ddc7f 100644
--- a/src/ca65/scanner.c
+++ b/src/ca65/scanner.c
@@ -226,6 +226,7 @@ struct DotKeyword {
     { ".IFP816",        TOK_IFP816              },
     { ".IFPC02",        TOK_IFPC02              },
     { ".IFPDTV",        TOK_IFPDTV              },
+    { ".IFPM740",       TOK_IFPM740             },
     { ".IFPSC02",       TOK_IFPSC02             },
     { ".IFREF",         TOK_IFREF               },
     { ".IMPORT",        TOK_IMPORT              },
@@ -268,6 +269,7 @@ struct DotKeyword {
     { ".PARAMCOUNT",    TOK_PARAMCOUNT          },
     { ".PC02",          TOK_PC02                },
     { ".PDTV",          TOK_PDTV                },
+    { ".PM740",         TOK_PM740               },
     { ".POPCHARMAP",    TOK_POPCHARMAP          },
     { ".POPCPU",        TOK_POPCPU              },
     { ".POPSEG",        TOK_POPSEG              },
diff --git a/src/ca65/token.h b/src/ca65/token.h
index aeae7166a..d4fa3a697 100644
--- a/src/ca65/token.h
+++ b/src/ca65/token.h
@@ -198,6 +198,7 @@ typedef enum token_t {
     TOK_IFP816,
     TOK_IFPC02,
     TOK_IFPDTV,
+    TOK_IFPM740,
     TOK_IFPSC02,
     TOK_IFREF,
     TOK_IMPORT,
@@ -234,6 +235,7 @@ typedef enum token_t {
     TOK_PARAMCOUNT,
     TOK_PC02,
     TOK_PDTV,
+    TOK_PM740,
     TOK_POPCHARMAP,
     TOK_POPCPU,
     TOK_POPSEG,
diff --git a/src/da65/handler.c b/src/da65/handler.c
index 79b3192de..45c152697 100644
--- a/src/da65/handler.c
+++ b/src/da65/handler.c
@@ -531,7 +531,25 @@ void OH_BitBranch (const OpcDesc* D)
     xfree (BranchLabel);
 }
 
+void OH_BitBranch_m740 (const OpcDesc* D)
+/* <bit> zp, rel
+** NOTE: currently <bit> is part of the instruction
+*/
+{
+    /* unsigned Bit = GetCodeByte (PC) >> 5; */
+    unsigned Addr = GetCodeByte (PC+1);
+    signed char BranchOffs = GetCodeByte (PC+2);
 
+    /* Calculate the target address for the branch */
+    unsigned BranchAddr = (((int) PC+3) + BranchOffs) & 0xFFFF;
+
+    /* Generate a label in pass 1 */
+    GenerateLabel (D->Flags, Addr);
+    GenerateLabel (flLabel, BranchAddr);
+
+    /* Output the line */
+    OneLine (D, "%s, %s", GetAddrArg (D->Flags, Addr), GetAddrArg (flLabel, BranchAddr));
+}
 
 void OH_ImmediateDirect (const OpcDesc* D)
 {
@@ -720,32 +738,36 @@ void OH_DirectImmediate (const OpcDesc* D)
 
 
 void OH_ZeroPageBit (const OpcDesc* D)
+/* <bit> zp
+** NOTE: currently <bit> is part of the instruction
+*/
 {
-    unsigned Bit = GetCodeByte (PC) >> 5;
     unsigned Addr = GetCodeByte (PC+1);
 
     /* Generate a label in pass 1 */
     GenerateLabel (D->Flags, Addr);
 
     /* Output the line */
-    OneLine (D, "%01X,%s", Bit, GetAddrArg (D->Flags, Addr));
+    OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
 }
 
 
 
 void OH_AccumulatorBit (const OpcDesc* D)
+/* <bit> A
+** NOTE: currently <bit> is part of the instruction
+*/
 {
-    unsigned Bit = GetCodeByte (PC) >> 5;
-
     /* Output the line */
-    OneLine (D, "%01X,a", Bit);
+    OneLine (D, "a");
 }
 
 
-
 void OH_AccumulatorBitBranch (const OpcDesc* D)
+/* <bit> A, rel
+** NOTE: currently <bit> is part of the instruction
+*/
 {
-    unsigned Bit = GetCodeByte (PC) >> 5;
     signed char BranchOffs = GetCodeByte (PC+1);
 
     /* Calculate the target address for the branch */
@@ -755,7 +777,7 @@ void OH_AccumulatorBitBranch (const OpcDesc* D)
     GenerateLabel (flLabel, BranchAddr);
 
     /* Output the line */
-    OneLine (D, "%01X,a,%s", Bit, GetAddrArg (flLabel, BranchAddr));
+    OneLine (D, "a, %s", GetAddrArg (flLabel, BranchAddr));
 }
 
 
@@ -770,17 +792,16 @@ void OH_JmpDirectIndirect (const OpcDesc* D)
 }
 
 
-
 void OH_SpecialPage (const OpcDesc* D)
+/* m740 "special page" address mode */
 {
-  /* Get the operand */
-  unsigned Addr = 0xFF00 + GetCodeByte (PC+1);
+    /* Get the operand */
+    unsigned Addr = 0xFF00 + GetCodeByte (PC+1);
 
-  /* Generate a label in pass 1 */
-  GenerateLabel (D->Flags, Addr);
+    /* Generate a label in pass 1 */
+    GenerateLabel (D->Flags, Addr);
 
-  /* OneLine (D, "$FF%02X", (CodeByte (PC+1)); */
-  OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
+    OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
 }
 
 
diff --git a/src/da65/handler.h b/src/da65/handler.h
index ee9b18bbc..fb0c40200 100644
--- a/src/da65/handler.h
+++ b/src/da65/handler.h
@@ -78,6 +78,7 @@ void OH_DirectXIndirect (const OpcDesc*);
 void OH_AbsoluteIndirect (const OpcDesc*);
 
 void OH_BitBranch (const OpcDesc*);
+void OH_BitBranch_m740 (const OpcDesc*);
 
 void OH_ImmediateDirect (const OpcDesc*);
 void OH_ImmediateDirectX (const OpcDesc*);
diff --git a/src/da65/opc6502x.c b/src/da65/opc6502x.c
index 3bdc8a549..c5fb5888c 100644
--- a/src/da65/opc6502x.c
+++ b/src/da65/opc6502x.c
@@ -188,7 +188,7 @@ const OpcDesc OpcTable_6502X[256] = {
     {   "dey",  1,  flNone,                   OH_Implicit              }, /* $88 */
     {   "nop",  2,  flNone,                   OH_Immediate             }, /* $89 */
     {   "txa",  1,  flNone,                   OH_Implicit              }, /* $8a */
-    {   "xaa",  2,  flNone,                   OH_Immediate             }, /* $8b */
+    {   "ane",  2,  flNone,                   OH_Immediate             }, /* $8b */
     {   "sty",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $8c */
     {   "sta",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $8d */
     {   "stx",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $8e */
@@ -196,7 +196,7 @@ const OpcDesc OpcTable_6502X[256] = {
     {   "bcc",  2,  flLabel,                  OH_Relative              }, /* $90 */
     {   "sta",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $91 */
     {   "jam",  1,  flNone,                   OH_Implicit              }, /* $92 */
-    {   "ahx",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $93 */
+    {   "sha",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $93 */
     {   "sty",  2,  flUseLabel,               OH_DirectX               }, /* $94 */
     {   "sta",  2,  flUseLabel,               OH_DirectX               }, /* $95 */
     {   "stx",  2,  flUseLabel,               OH_DirectY               }, /* $96 */
@@ -208,7 +208,7 @@ const OpcDesc OpcTable_6502X[256] = {
     {   "shy",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $9c */
     {   "sta",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $9d */
     {   "shx",  3,  flUseLabel,               OH_AbsoluteY             }, /* $9e */
-    {   "ahx",  3,  flUseLabel,               OH_AbsoluteY             }, /* $9f */
+    {   "sha",  3,  flUseLabel,               OH_AbsoluteY             }, /* $9f */
     {   "ldy",  2,  flNone,                   OH_Immediate             }, /* $a0 */
     {   "lda",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $a1 */
     {   "ldx",  2,  flNone,                   OH_Immediate             }, /* $a2 */
diff --git a/src/da65/opcm740.c b/src/da65/opcm740.c
index 67a36b48c..6d12a7d37 100644
--- a/src/da65/opcm740.c
+++ b/src/da65/opcm740.c
@@ -44,264 +44,265 @@
 /*                                   Data                                    */
 /*****************************************************************************/
 
-
+/* CAUTION: in the pdf $1a is dec, and $3a is inc - if that is really the case,
+ * the table below should be fixed and this notice removed */
 
 /* Descriptions for all opcodes */
 const OpcDesc OpcTable_M740[256] = {
     {   "brk",  1,  flNone,                   OH_Implicit              }, /* $00 */
     {   "ora",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $01 */
     {   "jsr",  2,  flLabel,                  OH_JmpDirectIndirect     }, /* $02 */
-    {   "bbs",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $03 */
+    {   "bbs0", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $03 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $04 */
     {   "ora",  2,  flUseLabel,               OH_Direct                }, /* $05 */
     {   "asl",  2,  flUseLabel,               OH_Direct                }, /* $06 */
-    {   "bbs",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $07 */
+    {   "bbs0", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $07 */
     {   "php",  1,  flNone,                   OH_Implicit              }, /* $08 */
     {   "ora",  2,  flNone,                   OH_Immediate             }, /* $09 */
     {   "asl",  1,  flNone,                   OH_Accumulator           }, /* $0a */
-    {   "seb",  1,  flNone,                   OH_AccumulatorBit        }, /* $0b */
+    {   "seb0", 1,  flNone,                   OH_AccumulatorBit        }, /* $0b */
     {   "",     1,  flIllegal,                OH_Illegal,              }, /* $0c */
     {   "ora",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $0d */
     {   "asl",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $0e */
-    {   "seb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $0f */
+    {   "seb0", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $0f */
     {   "bpl",  2,  flLabel,                  OH_Relative              }, /* $10 */
     {   "ora",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $11 */
     {   "clt",  1,  flNone,                   OH_Implicit              }, /* $12 */
-    {   "bbc",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $13 */
+    {   "bbc0", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $13 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $14 */
     {   "ora",  2,  flUseLabel,               OH_DirectX               }, /* $15 */
     {   "asl",  2,  flUseLabel,               OH_DirectX               }, /* $16 */
-    {   "bbc",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $17 */
+    {   "bbc0", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $17 */
     {   "clc",  1,  flNone,                   OH_Implicit              }, /* $18 */
     {   "ora",  3,  flUseLabel,               OH_AbsoluteY             }, /* $19 */
-    {   "dec",  1,  flNone,                   OH_Accumulator           }, /* $1a */
-    {   "clb",  1,  flNone,                   OH_AccumulatorBit        }, /* $1b */
+    {   "inc",  1,  flNone,                   OH_Accumulator           }, /* $1a */
+    {   "clb0", 1,  flNone,                   OH_AccumulatorBit        }, /* $1b */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $1c */
     {   "ora",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $1d */
     {   "asl",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $1e */
-    {   "clb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $1f */
+    {   "clb0", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $1f */
     {   "jsr",  3,  flLabel,                  OH_Absolute              }, /* $20 */
     {   "and",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $21 */
     {   "jsr",  2,  flLabel,                  OH_SpecialPage           }, /* $22 */
-    {   "bbs",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $23 */
+    {   "bbs1", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $23 */
     {   "bit",  2,  flUseLabel,               OH_Direct                }, /* $24 */
     {   "and",  2,  flUseLabel,               OH_Direct                }, /* $25 */
     {   "rol",  2,  flUseLabel,               OH_Direct                }, /* $26 */
-    {   "bbs",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $27 */
+    {   "bbs1", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $27 */
     {   "plp",  1,  flNone,                   OH_Implicit              }, /* $28 */
     {   "and",  2,  flNone,                   OH_Immediate             }, /* $29 */
     {   "rol",  1,  flNone,                   OH_Accumulator           }, /* $2a */
-    {   "seb",  1,  flNone,                   OH_AccumulatorBit        }, /* $2b */
+    {   "seb1", 1,  flNone,                   OH_AccumulatorBit        }, /* $2b */
     {   "bit",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $2c */
     {   "and",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $2d */
     {   "rol",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $2e */
-    {   "seb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $2f */
+    {   "seb1", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $2f */
     {   "bmi",  2,  flLabel,                  OH_Relative              }, /* $30 */
     {   "and",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $31 */
     {   "set",  1,  flNone,                   OH_Implicit              }, /* $32 */
-    {   "bbc",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $33 */
+    {   "bbc1", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $33 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $34 */
     {   "and",  2,  flUseLabel,               OH_DirectX               }, /* $35 */
     {   "rol",  2,  flUseLabel,               OH_DirectX               }, /* $36 */
-    {   "bbc",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $37 */
+    {   "bbc1", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $37 */
     {   "sec",  1,  flNone,                   OH_Implicit              }, /* $38 */
     {   "and",  3,  flUseLabel,               OH_AbsoluteY             }, /* $39 */
-    {   "inc",  1,  flNone,                   OH_Accumulator           }, /* $3a */
-    {   "clb",  1,  flNone,                   OH_AccumulatorBit        }, /* $3b */
+    {   "dec",  1,  flNone,                   OH_Accumulator           }, /* $3a */
+    {   "clb1", 1,  flNone,                   OH_AccumulatorBit        }, /* $3b */
     {   "ldm",  3,  flLabel,                  OH_DirectImmediate       }, /* $3c */
     {   "and",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $3d */
     {   "rol",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $3e */
-    {   "clb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $3f */
+    {   "clb1", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $3f */
     {   "rti",  1,  flNone,                   OH_Rts                   }, /* $40 */
     {   "eor",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $41 */
     {   "stp",  1,  flNone,                   OH_Implicit              }, /* $42 */
-    {   "bbs",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $43 */
+    {   "bbs2", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $43 */
     {   "com",  2,  flUseLabel,               OH_Direct                }, /* $44 */
     {   "eor",  2,  flUseLabel,               OH_Direct                }, /* $45 */
     {   "lsr",  2,  flUseLabel,               OH_Direct                }, /* $46 */
-    {   "bbs",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $47 */
+    {   "bbs2", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $47 */
     {   "pha",  1,  flNone,                   OH_Implicit              }, /* $48 */
     {   "eor",  2,  flNone,                   OH_Immediate             }, /* $49 */
     {   "lsr",  1,  flNone,                   OH_Accumulator           }, /* $4a */
-    {   "seb",  1,  flNone,                   OH_AccumulatorBit        }, /* $4b */
+    {   "seb2", 1,  flNone,                   OH_AccumulatorBit        }, /* $4b */
     {   "jmp",  3,  flLabel,                  OH_JmpAbsolute           }, /* $4c */
     {   "eor",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $4d */
     {   "lsr",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $4e */
-    {   "seb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $4f */
+    {   "seb2", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $4f */
     {   "bvc",  2,  flLabel,                  OH_Relative              }, /* $50 */
     {   "eor",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $51 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $52 */
-    {   "bbc",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $53 */
+    {   "bbc2", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $53 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $54 */
     {   "eor",  2,  flUseLabel,               OH_DirectX               }, /* $55 */
     {   "lsr",  2,  flUseLabel,               OH_DirectX               }, /* $56 */
-    {   "bbc",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $57 */
+    {   "bbc2", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $57 */
     {   "cli",  1,  flNone,                   OH_Implicit              }, /* $58 */
     {   "eor",  3,  flUseLabel,               OH_AbsoluteY             }, /* $59 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $5a */
-    {   "clb",  1,  flNone,                   OH_AccumulatorBit        }, /* $5b */
+    {   "clb2", 1,  flNone,                   OH_AccumulatorBit        }, /* $5b */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $5c */
     {   "eor",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $5d */
     {   "lsr",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $5e */
-    {   "clb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $5f */
+    {   "clb2", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $5f */
     {   "rts",  1,  flNone,                   OH_Rts                   }, /* $60 */
     {   "adc",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $61 */
-    {   "mul",  2,  flUseLabel,               OH_DirectX               }, /* $62 */
-    {   "bbs",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $63 */
+    {   "",     1,  flIllegal,                OH_Illegal               }, /* $62 */
+    {   "bbs3", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $63 */
     {   "tst",  2,  flUseLabel,               OH_Direct                }, /* $64 */
     {   "adc",  2,  flUseLabel,               OH_Direct                }, /* $65 */
     {   "ror",  2,  flUseLabel,               OH_Direct                }, /* $66 */
-    {   "bbs",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $67 */
+    {   "bbs3", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $67 */
     {   "pla",  1,  flNone,                   OH_Implicit              }, /* $68 */
     {   "adc",  2,  flNone,                   OH_Immediate             }, /* $69 */
     {   "ror",  1,  flNone,                   OH_Accumulator           }, /* $6a */
-    {   "seb",  1,  flNone,                   OH_AccumulatorBit        }, /* $6b */
+    {   "seb3", 1,  flNone,                   OH_AccumulatorBit        }, /* $6b */
     {   "jmp",  3,  flLabel,                  OH_JmpAbsoluteIndirect   }, /* $6c */
     {   "adc",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $6d */
     {   "ror",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $6e */
-    {   "seb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $6f */
+    {   "seb3", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $6f */
     {   "bvs",  2,  flLabel,                  OH_Relative              }, /* $70 */
     {   "adc",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $71 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $72 */
-    {   "bbc",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $73 */
+    {   "bbc3", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $73 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $74 */
     {   "adc",  2,  flUseLabel,               OH_DirectX               }, /* $75 */
     {   "ror",  2,  flUseLabel,               OH_DirectX               }, /* $76 */
-    {   "bbc",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $77 */
+    {   "bbc3", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $77 */
     {   "sei",  1,  flNone,                   OH_Implicit              }, /* $78 */
     {   "adc",  3,  flUseLabel,               OH_AbsoluteY             }, /* $79 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $7a */
-    {   "clb",  1,  flNone,                   OH_AccumulatorBit        }, /* $7b */
+    {   "clb3", 1,  flNone,                   OH_AccumulatorBit        }, /* $7b */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $7c */
     {   "adc",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $7d */
     {   "ror",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $7e */
-    {   "clb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $7f */
+    {   "clb3", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $7f */
     {   "bra",  2,  flLabel,                  OH_Relative              }, /* $80 */
     {   "sta",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $81 */
     {   "rrf",  2,  flLabel,                  OH_Direct                }, /* $82 */
-    {   "bbs",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $83 */
+    {   "bbs4", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $83 */
     {   "sty",  2,  flUseLabel,               OH_Direct                }, /* $84 */
     {   "sta",  2,  flUseLabel,               OH_Direct                }, /* $85 */
     {   "stx",  2,  flUseLabel,               OH_Direct                }, /* $86 */
-    {   "bbs",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $87 */
+    {   "bbs4", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $87 */
     {   "dey",  1,  flNone,                   OH_Implicit              }, /* $88 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $89 */
     {   "txa",  1,  flNone,                   OH_Implicit              }, /* $8a */
-    {   "seb",  1,  flNone,                   OH_AccumulatorBit        }, /* $8b */
+    {   "seb4", 1,  flNone,                   OH_AccumulatorBit        }, /* $8b */
     {   "sty",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $8c */
     {   "sta",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $8d */
     {   "stx",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $8e */
-    {   "seb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $8f */
+    {   "seb4", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $8f */
     {   "bcc",  2,  flLabel,                  OH_Relative              }, /* $90 */
     {   "sta",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $91 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $92 */
-    {   "bbc",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $93 */
+    {   "bbc4", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $93 */
     {   "sty",  2,  flUseLabel,               OH_DirectX               }, /* $94 */
     {   "sta",  2,  flUseLabel,               OH_DirectX               }, /* $95 */
     {   "stx",  2,  flUseLabel,               OH_DirectY               }, /* $96 */
-    {   "bbc",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $97 */
+    {   "bbc4", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $97 */
     {   "tya",  1,  flNone,                   OH_Implicit              }, /* $98 */
     {   "sta",  3,  flUseLabel,               OH_AbsoluteY             }, /* $99 */
     {   "txs",  1,  flNone,                   OH_Implicit              }, /* $9a */
-    {   "clb",  1,  flNone,                   OH_AccumulatorBit        }, /* $9b */
+    {   "clb4", 1,  flNone,                   OH_AccumulatorBit        }, /* $9b */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $9c */
     {   "sta",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $9d */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $9e */
-    {   "clb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $9f */
+    {   "clb4", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $9f */
     {   "ldy",  2,  flNone,                   OH_Immediate             }, /* $a0 */
     {   "lda",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $a1 */
     {   "ldx",  2,  flNone,                   OH_Immediate             }, /* $a2 */
-    {   "bbs",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $a3 */
+    {   "bbs5", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $a3 */
     {   "ldy",  2,  flUseLabel,               OH_Direct                }, /* $a4 */
     {   "lda",  2,  flUseLabel,               OH_Direct                }, /* $a5 */
     {   "ldx",  2,  flUseLabel,               OH_Direct                }, /* $a6 */
-    {   "bbs",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $a7 */
+    {   "bbs5", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $a7 */
     {   "tay",  1,  flNone,                   OH_Implicit              }, /* $a8 */
     {   "lda",  2,  flNone,                   OH_Immediate             }, /* $a9 */
     {   "tax",  1,  flNone,                   OH_Implicit              }, /* $aa */
-    {   "seb",  1,  flNone,                   OH_AccumulatorBit        }, /* $ab */
+    {   "seb5", 1,  flNone,                   OH_AccumulatorBit        }, /* $ab */
     {   "ldy",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ac */
     {   "lda",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ad */
     {   "ldx",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ae */
-    {   "seb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $af */
+    {   "seb5", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $af */
     {   "bcs",  2,  flLabel,                  OH_Relative              }, /* $b0 */
     {   "lda",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $b1 */
     {   "jmp",  2,  flLabel,                  OH_JmpDirectIndirect     }, /* $b2 */
-    {   "bbc",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $b3 */
+    {   "bbc5", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $b3 */
     {   "ldy",  2,  flUseLabel,               OH_DirectX               }, /* $b4 */
     {   "lda",  2,  flUseLabel,               OH_DirectX               }, /* $b5 */
     {   "ldx",  2,  flUseLabel,               OH_DirectY               }, /* $b6 */
-    {   "bbc",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $b7 */
+    {   "bbc5", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $b7 */
     {   "clv",  1,  flNone,                   OH_Implicit              }, /* $b8 */
     {   "lda",  3,  flUseLabel,               OH_AbsoluteY             }, /* $b9 */
     {   "tsx",  1,  flNone,                   OH_Implicit              }, /* $ba */
-    {   "clb",  1,  flNone,                   OH_AccumulatorBit        }, /* $bb */
+    {   "clb5", 1,  flNone,                   OH_AccumulatorBit        }, /* $bb */
     {   "ldy",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $bc */
     {   "lda",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $bd */
     {   "ldx",  3,  flUseLabel|flAbsOverride, OH_AbsoluteY             }, /* $be */
-    {   "clb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $bf */
+    {   "clb5", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $bf */
     {   "cpy",  2,  flNone,                   OH_Immediate             }, /* $c0 */
     {   "cmp",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $c1 */
-    {   "wit",  1,  flNone,                   OH_Implicit,             }, /* $c2 */
-    {   "bbs",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $c3 */
+    {   "slw",  1,  flNone,                   OH_Implicit,             }, /* $c2 */
+    {   "bbs6", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $c3 */
     {   "cpy",  2,  flUseLabel,               OH_Direct                }, /* $c4 */
     {   "cmp",  2,  flUseLabel,               OH_Direct                }, /* $c5 */
     {   "dec",  2,  flUseLabel,               OH_Direct                }, /* $c6 */
-    {   "bbs",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $c7 */
+    {   "bbs6", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $c7 */
     {   "iny",  1,  flNone,                   OH_Implicit              }, /* $c8 */
     {   "cmp",  2,  flNone,                   OH_Immediate             }, /* $c9 */
     {   "dex",  1,  flNone,                   OH_Implicit              }, /* $ca */
-    {   "seb",  1,  flNone,                   OH_AccumulatorBit        }, /* $cb */
+    {   "seb6", 1,  flNone,                   OH_AccumulatorBit        }, /* $cb */
     {   "cpy",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $cc */
     {   "cmp",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $cd */
     {   "dec",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ce */
-    {   "seb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $cf */
+    {   "seb6", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $cf */
     {   "bne",  2,  flLabel,                  OH_Relative              }, /* $d0 */
     {   "cmp",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $d1 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $d2 */
-    {   "bbc",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $d3 */
+    {   "bbc6", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $d3 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $d4 */
     {   "cmp",  2,  flUseLabel,               OH_DirectX               }, /* $d5 */
     {   "dec",  2,  flUseLabel,               OH_DirectX               }, /* $d6 */
-    {   "bbc",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $d7 */
+    {   "bbc6", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $d7 */
     {   "cld",  1,  flNone,                   OH_Implicit              }, /* $d8 */
     {   "cmp",  3,  flUseLabel,               OH_AbsoluteY             }, /* $d9 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $da */
-    {   "clb",  1,  flNone,                   OH_AccumulatorBit        }, /* $db */
+    {   "clb6", 1,  flNone,                   OH_AccumulatorBit        }, /* $db */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $dc */
     {   "cmp",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $dd */
     {   "dec",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $de */
-    {   "clb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $df */
+    {   "clb6", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $df */
     {   "cpx",  2,  flNone,                   OH_Immediate             }, /* $e0 */
     {   "sbc",  2,  flUseLabel,               OH_DirectXIndirect       }, /* $e1 */
-    {   "div",  2,  flUseLabel,               OH_DirectX               }, /* $e2 */
-    {   "bbs",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $e3 */
+    {   "fst",  1,  flNone,                   OH_Implicit              }, /* $e2 */
+    {   "bbs7", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $e3 */
     {   "cpx",  2,  flUseLabel,               OH_Direct                }, /* $e4 */
     {   "sbc",  2,  flUseLabel,               OH_Direct                }, /* $e5 */
     {   "inc",  2,  flUseLabel,               OH_Direct                }, /* $e6 */
-    {   "bbs",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $e7 */
+    {   "bbs7", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $e7 */
     {   "inx",  1,  flNone,                   OH_Implicit              }, /* $e8 */
     {   "sbc",  2,  flNone,                   OH_Immediate             }, /* $e9 */
     {   "nop",  1,  flNone,                   OH_Implicit              }, /* $ea */
-    {   "seb",  1,  flNone,                   OH_AccumulatorBit        }, /* $eb */
+    {   "seb7", 1,  flNone,                   OH_AccumulatorBit        }, /* $eb */
     {   "cpx",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ec */
     {   "sbc",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ed */
     {   "inc",  3,  flUseLabel|flAbsOverride, OH_Absolute              }, /* $ee */
-    {   "seb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $ef */
+    {   "seb7", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $ef */
     {   "beq",  2,  flLabel,                  OH_Relative              }, /* $f0 */
     {   "sbc",  2,  flUseLabel,               OH_DirectIndirectY       }, /* $f1 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $f2 */
-    {   "bbc",  2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $f3 */
+    {   "bbc7", 2,  flUseLabel,               OH_AccumulatorBitBranch  }, /* $f3 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $f4 */
     {   "sbc",  2,  flUseLabel,               OH_DirectX               }, /* $f5 */
     {   "inc",  2,  flUseLabel,               OH_DirectX               }, /* $f6 */
-    {   "bbc",  3,  flUseLabel,               OH_ZeroPageBit           }, /* $f7 */
+    {   "bbc7", 3,  flUseLabel,               OH_BitBranch_m740        }, /* $f7 */
     {   "sed",  1,  flNone,                   OH_Implicit              }, /* $f8 */
     {   "sbc",  3,  flUseLabel,               OH_AbsoluteY             }, /* $f9 */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $fa */
-    {   "clb",  1,  flNone,                   OH_AccumulatorBit        }, /* $fb */
+    {   "clb7", 1,  flNone,                   OH_AccumulatorBit        }, /* $fb */
     {   "",     1,  flIllegal,                OH_Illegal               }, /* $fc */
     {   "sbc",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $fd */
     {   "inc",  3,  flUseLabel|flAbsOverride, OH_AbsoluteX             }, /* $fe */
-    {   "clb",  2,  flUseLabel,               OH_ZeroPageBit           }, /* $ff */
+    {   "clb7", 2,  flUseLabel,               OH_ZeroPageBit           }, /* $ff */
 };
diff --git a/test/asm/cpudetect/allinst.inc b/test/asm/cpudetect/allinst.inc
new file mode 100644
index 000000000..ab266915e
--- /dev/null
+++ b/test/asm/cpudetect/allinst.inc
@@ -0,0 +1,814 @@
+
+    ; just emit to bss for now, this way the output wont get checked, which is
+    ; fine - we only want to see if the assembler accepts all the opcodes it
+    ; should accept for the current CPU mode
+    .bss
+
+.if (.cpu .bitand CPU_ISET_6502)
+    .scope
+    ; regular basic 6502 (legal) instruction set
+LABEL0:
+    brk             ; $00
+    ora ($12,x)     ; $01
+    ora $12         ; $05
+    asl $12         ; $06
+    php             ; $08
+    ora #$12        ; $09
+    asl a           ; $0a
+    ora $1234       ; $0d
+    asl $1234       ; $0e
+    bpl LABEL0      ; $10
+    ora ($12),y     ; $11
+    ora $12,x       ; $15
+    asl $12,x       ; $16
+    clc             ; $18
+    ora $1234,y     ; $19
+    ora $1234,x     ; $1d
+    asl $1234,x     ; $1e
+    jsr $1234       ; $20
+    and ($12,x)     ; $21
+    bit $12         ; $24
+    and $12         ; $25
+    rol $12         ; $26
+    plp             ; $28
+    and #$12        ; $29
+    rol a           ; $2a
+    bit $1234       ; $2c
+    and $1234       ; $2d
+    rol $1234       ; $2e
+    bmi LABEL       ; $30
+    and ($12),y     ; $31
+    and $12,x       ; $35
+    rol $12,x       ; $36
+    sec             ; $38
+    and $1234,y     ; $39
+    and $1234,x     ; $3d
+    rol $1234,x     ; $3e
+    rti             ; $40
+    eor ($12,x)     ; $41
+    eor $12         ; $45
+    lsr $12         ; $46
+    pha             ; $48
+    eor #$12        ; $49
+    lsr a           ; $4a
+    jmp $1234       ; $4c
+    eor $1234       ; $4d
+    lsr $1234       ; $4e
+    bvc LABEL       ; $50
+    eor ($12),y     ; $51
+    eor $12,x       ; $55
+    lsr $12,x       ; $56
+    cli             ; $58
+    eor $1234,y     ; $59
+    eor $1234,x     ; $5d
+    lsr $1234,x     ; $5e
+    rts             ; $60
+    adc ($12,x)     ; $61
+    adc $12         ; $65
+    ror $12         ; $66
+    pla             ; $68
+    adc #$12        ; $69
+    ror a           ; $6a
+    jmp ($1234)     ; $6c
+    adc $1234       ; $6d
+    ror $1234       ; $6e
+    bvs LABEL       ; $70
+    adc ($12),y     ; $71
+    adc $12,x       ; $75
+    ror $12,x       ; $76
+    sei             ; $78
+    adc $1234,y     ; $79
+    adc $1234,x     ; $7d
+    ror $1234,x     ; $7e
+LABEL:
+    sta ($12,x)     ; $81
+    sty $12         ; $84
+    sta $12         ; $85
+    stx $12         ; $86
+    dey             ; $88
+    txa             ; $8a
+    sty $1234       ; $8c
+    sta $1234       ; $8d
+    stx $1234       ; $8e
+    bcc LABEL       ; $90
+    sta ($12),y     ; $91
+    sty $12,x       ; $94
+    sta $12,x       ; $95
+    stx $12,y       ; $96
+    tya             ; $98
+    sta $1234,y     ; $99
+    txs             ; $9a
+    sta $1234,x     ; $9d
+    ldy #$12        ; $a0
+    lda ($12,x)     ; $a1
+    ldx #$12        ; $a2
+    ldy $12         ; $a4
+    lda $12         ; $a5
+    ldx $12         ; $a6
+    tay             ; $a8
+    lda #$12        ; $a9
+    tax             ; $aa
+    ldy $1234       ; $ac
+    lda $1234       ; $ad
+    ldx $1234       ; $ae
+    bcs LABEL       ; $b0
+    lda ($12),y     ; $b1
+    ldy $12,x       ; $b4
+    lda $12,x       ; $b5
+    ldx $12,y       ; $b6
+    clv             ; $b8
+    lda $1234,y     ; $b9
+    tsx             ; $ba
+    ldy $1234,x     ; $bc
+    lda $1234,x     ; $bd
+    ldx $1234,y     ; $be
+    cpy #$12        ; $c0
+    cmp ($12,x)     ; $c1
+    cpy $12         ; $c4
+    cmp $12         ; $c5
+    dec $12         ; $c6
+    iny             ; $c8
+    cmp #$12        ; $c9
+    dex             ; $ca
+    cpy $1234       ; $cc
+    cmp $1234       ; $cd
+    dec $1234       ; $ce
+    bne LABEL       ; $d0
+    cmp ($12),y     ; $d1
+    cmp $12,x       ; $d5
+    dec $12,x       ; $d6
+    cld             ; $d8
+    cmp $1234,y     ; $d9
+    cmp $1234,x     ; $dd
+    dec $1234,x     ; $de
+    cpx #$12        ; $e0
+    sbc ($12,x)     ; $e1
+    cpx $12         ; $e4
+    sbc $12         ; $e5
+    inc $12         ; $e6
+    inx             ; $e8
+    sbc #$12        ; $e9
+    nop             ; $ea
+    cpx $1234       ; $ec
+    sbc $1234       ; $ed
+    inc $1234       ; $ee
+    beq LABEL1      ; $f0
+    sbc ($12),y     ; $f1
+    sbc $12,x       ; $f5
+    inc $12,x       ; $f6
+    sed             ; $f8
+    sbc $1234,y     ; $f9
+    sbc $1234,x     ; $fd
+    inc $1234,x     ; $fe
+LABEL1:
+    .endscope
+.endif
+
+
+.if (.cpu .bitand CPU_ISET_6502X)
+    .scope
+    ; all "undocumented" 6502 instructions (aka "unintended opcodes")
+    jam             ; $02
+    slo ($12,x)     ; $03
+    nop $12         ; $04
+    slo $12         ; $07
+    anc #$12        ; $0b
+    nop $1234       ; $0c
+    slo $1234       ; $0f
+    jam             ; $12
+    slo ($12),y     ; $13
+    nop $12,x       ; $14
+    slo $12,y       ; $17
+    nop             ; $1a
+    slo $1234,y     ; $1b
+    nop $1234,x     ; $1c
+    slo $1234,x     ; $1f
+    jam             ; $22
+    rla ($12,x)     ; $23
+    rla $12         ; $27
+    anc #$12        ; $2b
+    rla $1234       ; $2f
+    jam             ; $32
+    rla ($12),y     ; $33
+    nop $12,x       ; $34
+    rla $12,y       ; $37
+    nop             ; $3a
+    rla $1234,y     ; $3b
+    nop $1234,x     ; $3c
+    rla $1234,x     ; $3f
+    jam             ; $42
+    sre ($12,x)     ; $43
+    nop $12         ; $44
+    sre $12         ; $47
+    alr #$12        ; $4b
+    sre $1234       ; $4f
+    jam             ; $52
+    sre ($12),y     ; $53
+    nop $12,x       ; $54
+    sre $12,y       ; $57
+    nop             ; $5a
+    sre $1234,y     ; $5b
+    nop $1234,x     ; $5c
+    sre $1234,x     ; $5f
+    jam             ; $62
+    rra ($12,x)     ; $63
+    nop $12         ; $64
+    rra $12         ; $67
+    arr #$12        ; $6b
+    rra $1234       ; $6f
+    jam             ; $72
+    rra ($12),y     ; $73
+    nop $12,x       ; $74
+    rra $12,y       ; $77
+    nop             ; $7a
+    rra $1234,y     ; $7b
+    nop $1234,x     ; $7c
+    rra $1234,x     ; $7f
+    nop #$12        ; $80
+    nop #$12        ; $82
+    sax ($12,x)     ; $83
+    sax $12         ; $87
+    nop #$12        ; $89
+    ane #$12        ; $8b
+    sax $1234       ; $8f
+    jam             ; $92
+    sha ($12),y     ; $93
+    sax $12,y       ; $97
+    tas $1234,y     ; $9b
+    shy $1234,x     ; $9c
+    shx $1234,y     ; $9e
+    sha $1234,y     ; $9f
+    lax ($12,x)     ; $a3
+    lax $12         ; $a7
+    lax #$12        ; $ab
+    lax $1234       ; $af
+    jam             ; $b2
+    lax ($12),y     ; $b3
+    lax $12,y       ; $b7
+    las $1234,y     ; $bb
+    lax $1234,y     ; $bf
+    nop #$12        ; $c2
+    dcp ($12,x)     ; $c3
+    dcp $12         ; $c7
+    axs #$12        ; $cb
+    dcp $1234       ; $cf
+    jam             ; $d2
+    dcp ($12),y     ; $d3
+    nop $12,x       ; $d4
+    dcp $12,y       ; $d7
+    nop             ; $da
+    dcp $1234,y     ; $db
+    nop $1234,x     ; $dc
+    dcp $1234,x     ; $df
+    nop #$12        ; $e2
+    isc ($12,x)     ; $e3
+    isc $12         ; $e7
+    sbc #$12        ; $eb
+    isc $1234       ; $ef
+    jam             ; $f2
+    isc ($12),y     ; $f3
+    nop $12,x       ; $f4
+    isc $12,y       ; $f7
+    nop             ; $fa
+    isc $1234,y     ; $fb
+    nop $1234,x     ; $fc
+    isc $1234,x     ; $ff
+    .endscope
+.endif
+
+
+.if (.cpu .bitand CPU_ISET_6502DTV)
+    .scope
+LABEL:
+    ; opcodes added over 6502 (these are JAM on 6502)
+    bra LABEL       ; $12
+    sac #$12        ; $32
+    sir #$12        ; $42
+
+    ; opcodes added over 6502, which work the same as the "illegal" opcodes on 6502
+    nop $12         ; $04
+    nop $1234       ; $0c
+    nop $12,x       ; $14
+    nop             ; $1a
+    nop $1234,x     ; $1c
+    nop $12,x       ; $34
+    nop             ; $3a
+    nop $1234,x     ; $3c
+    nop $12         ; $44
+    nop $12,x       ; $54
+    nop             ; $5a
+    nop $1234,x     ; $5c
+    nop $12         ; $64
+    nop $12,x       ; $74
+    nop             ; $7a
+    nop $1234,x     ; $7c
+    nop #$12        ; $80
+    nop #$12        ; $82
+    nop #$12        ; $89
+    nop #$12        ; $c2
+    nop $12,x       ; $d4
+    nop             ; $da
+    nop $1234,x     ; $dc
+    nop #$12        ; $e2
+    nop $12,x       ; $f4
+    nop             ; $fa
+    nop $1234,x     ; $fc
+
+    anc #$12        ; $0b
+    anc #$12        ; $2b
+
+    rla ($12,x)     ; $23
+    rla $12         ; $27
+    rla $1234       ; $2f
+    rla ($12),y     ; $33
+    rla $12,y       ; $37
+    rla $1234,y     ; $3b
+    rla $1234,x     ; $3f
+
+    lax ($12,x)     ; $a3
+    lax $12         ; $a7
+    lax #$12        ; $ab
+    lax $1234       ; $af
+    lax ($12),y     ; $b3
+    lax $12,y       ; $b7
+    lax $1234,y     ; $bf
+
+    las $1234,y     ; $bb
+
+    alr #$12        ; $4b
+
+    arr #$12        ; $6b
+
+    rra ($12,x)     ; $63
+    rra $12         ; $67
+    rra $1234       ; $6f
+    rra ($12),y     ; $73
+    rra $12,y       ; $77
+    rra $1234,y     ; $7b
+    rra $1234,x     ; $7f
+
+    shy $1234,x     ; $9c
+    shx $1234,y     ; $9e
+
+    axs #$12        ; $cb
+
+    sbc #$12        ; $eb
+
+    .endscope
+.endif
+
+
+;------------------------------------------------------------------------------
+; The 65c02 is the CMOS re-design of the 6502. It has a few improvements:
+;
+;      65C02            65ce02
+;
+; $04  tsb zp
+; $0c  tsb abs16
+; $12  ora (zp)         (-> ora (zp), z)
+; $14  trb zp
+; $1a  inc
+; $1c  trb abs16
+; $32  and (zp)         (-> and (zp), z)
+; $34  bit zp, x
+; $3a  dec
+; $3c  bit abs16, x
+; $52  eor (zp)         (-> eor (zp), z)
+; $5a  phy
+; $64  stz zp           (store z, not 0)
+; $72  adc (zp)         (-> adc (zp), z)
+; $74  stz zp, x        (store z, not 0)
+; $7a  ply
+; $7c  jmp (abs16, x)
+; $80  bra rel8
+; $89  bit #imm8
+; $92  sta (zp)         (-> sta (zp), z)
+; $9c  stz abs16        (store z, not 0)
+; $9e  stz abs16, x     (store z, not 0)
+; $b2  lda (zp)         (-> lda (zp), z)
+; $d2  cmp (zp)         (-> cmp (zp), z)
+; $da  phx
+; $f2  sbc (zp)         (-> sbc (zp), z)
+; $fa  plx
+
+; FIXME: currently CPU_ISET_65SC02 and CPU_65SC02 really means "65C02"
+
+; FIXME: should really check for 65C02
+
+.if (.cpu .bitand CPU_ISET_65SC02)
+    .scope
+    ; 65c02 instruction set adds some extra legal instructions to 6502
+    tsb $12         ; $04
+    tsb $1234       ; $0c
+    ;ora ($12)       ; $12  FIXME: not working with 4510:ora (zp), z
+    trb $12         ; $14
+    inc a           ; $1a
+    trb $1234       ; $1c
+    ;and ($12)       ; $32  FIXME: not working with 4510:and (zp), z
+    bit $12,x       ; $34
+    dec a           ; $3a
+    bit $1234,x     ; $3c
+    ;eor ($12)       ; $52  FIXME: not working with 4510:eor (zp), z
+    phy             ; $5a
+    stz $12         ; $64
+    ;adc ($12)       ; $72  FIXME: not working with 4510:adc (zp), z
+    stz $12,x       ; $74
+    ply             ; $7a
+    jmp ($1234)     ; $7c
+LABEL:
+    bra LABEL       ; $80
+    bit #$12        ; $89
+    ;sta ($12)       ; $92  FIXME: not working with 4510:sta (zp), z
+    stz $1234       ; $9c
+    stz $1234,x     ; $9e
+    ;lda ($12)       ; $b2  FIXME: not working with 4510:lda (zp), z
+    ;cmp ($12)       ; $d2  FIXME: not working with 4510:cmp (zp), z
+    phx             ; $da
+    ;sbc ($12)       ; $f2  FIXME: not working with 4510:sbc (zp), z
+    plx             ; $fa
+    .endscope
+.endif
+
+; FIXME: hack so these opcodes get tested anyway, while 4510 is still quirky
+.if (.cpu .bitand CPU_ISET_65SC02)
+.if (.not .cpu = CPU_4510)
+    ora ($12)       ; $12
+    and ($12)       ; $32
+    eor ($12)       ; $52
+    adc ($12)       ; $72
+    sta ($12)       ; $92
+    lda ($12)       ; $b2
+    cmp ($12)       ; $d2
+    sbc ($12)       ; $f2
+.endif
+.endif
+
+; TODO: R65C02
+; The R65C02 is a superset of the 65C02. It adds bit manipulation instructions:
+;   smbB zp         set bit in zp location
+;   rmbB zp         reset bit in zp location
+;   bbsB zp, rel8   branch if bit is set in zp location
+;   bbrB zp, rel8   branch if bit is reset in zp location
+
+; FIXME: currently CPU_ISET_65C02 and CPU_65C02 really means "W65C02"
+
+; FIXME: should really check for R65C02
+
+.if (.cpu .bitand CPU_ISET_65C02)
+
+    ; R65C02 instruction set adds some extra legal instructions to 65C02
+    rmb0 $12            ; $07
+    bbr0 $12, LABEL3    ; $0f
+    rmb1 $12            ; $17
+    bbr1 $12, LABEL3    ; $1f
+    rmb2 $12            ; $27
+    bbr2 $12, LABEL3    ; $2f
+    rmb3 $12            ; $37
+    bbr3 $12, LABEL3    ; $3f
+    rmb4 $12            ; $47
+    bbr4 $12, LABEL3    ; $4f
+    rmb5 $12            ; $57
+    bbr5 $12, LABEL3    ; $5f
+    rmb6 $12            ; $67
+    bbr6 $12, LABEL3    ; $6f
+    rmb7 $12            ; $77
+    bbr7 $12, LABEL3    ; $7f
+LABEL3:
+    smb0 $12            ; $87
+    bbs0 $12, LABEL3    ; $8f
+    smb1 $12            ; $97
+    bbs1 $12, LABEL3    ; $9f
+    smb2 $12            ; $a7
+    bbs2 $12, LABEL3    ; $af
+    smb3 $12            ; $b7
+    bbs3 $12, LABEL3    ; $bf
+    smb4 $12            ; $c7
+    bbs4 $12, LABEL3    ; $cf
+    smb5 $12            ; $d7
+    bbs5 $12, LABEL3    ; $df
+    smb6 $12            ; $e7
+    bbs6 $12, LABEL3    ; $ef
+    smb7 $12            ; $f7
+    bbs7 $12, LABEL3    ; $ff
+
+.endif
+
+
+; TODO: W65C02
+; The W65C02 is a superset of the R65C02. It only adds two instructions:
+;
+; $cb  wai             wait for interrupt
+; $db  stp             wait for reset
+
+; FIXME: currently CPU_ISET_65C02 and CPU_65C02 really means "W65C02"
+
+; FIXME: should really check for W65C02
+
+.if (.cpu = CPU_65C02)
+    wai             ; $cb
+    stp             ; $db
+.endif
+
+
+; TODO: 65CE02
+; The 65CE02 is another superset of the R65C02. It has several improvements:
+;
+; $02  cle              clear stack extend disable
+; $03  see              set stack extend disable
+; $0b  tsy              transfer stack_ptr_high to Y
+; $12  ora (zp), z
+; $13  lbpl rel16
+; $1b  inz              increment Z
+; $22  jsr (abs16)
+; $23  jsr (abs16, x)
+; $2b  tys              transfer Y to stack_ptr_high
+; $32  and (zp), z
+; $33  lbmi rel16
+; $3b  dez              decrement Z
+; $42  neg              negate A
+; $43  asr
+; $44  asr zp
+; $4b  taz              transfer A to Z
+; $52  eor (zp), z
+; $53  lbvc rel16
+; $54  asr zp, x
+; $5b  tab
+; $5c  aug              "4-byte NOP reserved for future expansion"
+; $62  rtn #imm8
+; $63  lbsr rel16       relative jsr, "branch to subroutine"
+; $64  stz zp           store Z
+; $6b  tza              transfer Z to A
+; $72  adc (zp), z
+; $73  lbvs rel16
+; $74  stz zp, x        store Z
+; $7b  tba
+; $82  sta (off8, s), y
+; $83  lbra rel16       relative jmp
+; $8b  sty abs16, x
+; $92  sta (zp), z
+; $93  lbcc rel16
+; $9b  stx abs16, y
+; $9c  stz abs16        store Z
+; $9e  stz abs16, x     store Z
+; $a3  ldz #imm8
+; $ab  ldz abs16
+; $b2  lda (zp), z
+; $b3  lbcs rel16
+; $bb  ldz abs16, x
+; $c2  cpz #imm8
+; $c3  dew zp
+; $cb  asw abs16
+; $d2  cmp (zp), z
+; $d3  lbne rel16
+; $d4  cpz zp
+; $db  phz              push Z
+; $dc  cpz abs16
+; $e2  lda (off8, s), y
+; $e3  inw zp
+; $eb  row abs16
+; $f2  sbc (zp), z
+; $f3  lbeq rel16
+; $f4  phw #imm16
+; $fb  plz              pull Z
+; $fc  phw abs16
+
+; FIXME: should really check for 65CE02
+
+.if (.cpu .bitand CPU_ISET_4510)
+    .scope
+    ; 65CE02 adds the following:
+    cle                         ; $02
+    see                         ; $03
+    tsy                         ; $0b
+    ora ($12), z                ; $12    (ora (zp) on 65C02)
+    lbpl $1234                  ; $13
+    inz                         ; $1b
+    jsr ($1234)                 ; $22
+    jsr ($1234,x)               ; $23
+    tys                         ; $2b
+    and ($12), z                ; $32    (and (zp) on 65C02)
+    lbmi $1234                  ; $33
+    dez                         ; $3b
+    neg                         ; $42
+    asr a                       ; $43
+    asr $12                     ; $44
+    taz                         ; $4b
+    lbvc $1234                  ; $53
+    asr $12,x                   ; $54
+    tab                         ; $5b
+    ;aug                        ; $5c FIXME: implement in assembler
+    rtn #$12                    ; $62
+    bsr $1234                   ; $63
+    stz $12                     ; $64    (stores 0 on 65C02)
+    tza                         ; $6b
+    adc ($12), z                ; $72    (adc (zp) on 65C02)
+    lbvs $1234                  ; $73
+    stz $12, x                  ; $74    (stores 0 on 65C02)
+    tba                         ; $7b
+    sta ($12,s),y               ; $82
+    lbra $1234                  ; $83
+    sty $1234,x                 ; $8b
+    lbcc $1234                  ; $93
+    sta ($12), z                ; $92    (sta (zp) on 65C02)
+    stx $1234,y                 ; $9b
+    stz $1234                   ; $9c    (stores 0 on 65C02)
+    ldz #$12                    ; $a3
+    ldz $1234                   ; $ab
+    lda ($12), z                ; $b2    (lda (zp) on 65C02)
+    lbcs $1234                  ; $b3
+    ldz $1234,x                 ; $bb
+    cpz #$12                    ; $c2
+    dew $12                     ; $c3
+    cmp ($12), z                ; $d2    (cmp ($12) on 65C02)
+    lbne $1234                  ; $d3
+    cpz $12                     ; $d4
+    cpz $1234                   ; $dc
+    lda ($12,s),y               ; $e2
+    inw $12                     ; $e3
+    row $1234                   ; $eb
+    sbc ($12), z                ; $f2    (sbc (zp) on 65C02)
+    lbeq $1234                  ; $f3
+    phw #$1234                  ; $f4
+    plz                         ; $fb
+    phw $1234                   ; $fc
+
+    .endscope
+.endif
+
+
+; The 4502 is a superset of the 65CE02. Opcode 5c (originally a "4-byte NOP
+; reserved for future expansion") has been changed to the "map" instruction,
+; now using implied addressing.
+;
+; $5c  map
+; $cb  asw abs
+; $db  phz
+
+.if (.cpu .bitand CPU_ISET_4510)
+    .scope
+
+    ; added to 65CE02
+    map                         ; $5c   ("4-byte NOP reserved for future expansion" on 65CE02)
+    asw $1234                   ; $cb   (wai on W65C02)
+    phz                         ; $db   (stp on W65C02)
+
+    .endscope
+.endif
+
+
+; TODO: MEGA65
+; The m65 instruction set extends the 4502 instruction set using prefix bytes.
+; Therefore, the "normal" opcode table is the same as for the 4502 cpu
+
+
+; The HUC6280 is a superset of the R65C02. It adds some other instructions:
+
+.if (.cpu .bitand CPU_ISET_HUC6280)
+    .scope
+
+    ; added to R65C02
+    sxy                         ; $02
+    st0 #$12                    ; $03
+    st1 #$12                    ; $13
+    sax                         ; $22
+    st2 #$12                    ; $23
+    say                         ; $42
+    tma #$10                    ; $43
+    bsr LABEL                   ; $44
+    tam #$12                    ; $53
+    csl                         ; $54
+    cla                         ; $62
+    tii $1234, $5678, $9abc     ; $73
+LABEL:
+    clx                         ; $82
+    tst #$12, $34               ; $83
+    clx                         ; $82
+    tst #$12, $34               ; $83
+    tst #$12, $3456             ; $93
+    tst #$12, $34, x            ; $a3
+    tst #$12, $3456, x          ; $b3
+    cly                         ; $c2
+    tdd $1234, $5678, $9abc     ; $c3
+    tin $1234, $5678, $9abc     ; $d3
+    csh                         ; $d4
+    tia $1234, $5678, $9abc     ; $e3
+    tai $1234, $5678, $9abc     ; $f3
+    set                         ; $f4
+
+    .endscope
+.endif
+
+
+.if (.cpu .bitand CPU_ISET_M740)
+    .scope
+    ; Mitsubishi M740 - adds new instructions to 65SC02 (but also removes some)
+
+    jsr ($12)           ; $02
+    bbs0 a, LABEL       ; $03
+    bbs0 $12, LABEL     ; $07
+    seb0 a              ; $0b
+    seb0 $12            ; $0f
+    bbc0 a, LABEL       ; $13
+    bbc0 $12, LABEL     ; $17
+    clb0 a              ; $1b
+    clb0 $12            ; $1f
+    jsr $ff12           ; $22
+    bbs1 a, LABEL       ; $23
+    bbs1 $12, LABEL     ; $27
+    seb1 a              ; $2b
+    seb1 $12            ; $2f
+    bbc1 a, LABEL       ; $33
+    bbc1 $12, LABEL     ; $37
+    clb1 a              ; $3b
+    clb1 $12            ; $3f
+    stp                 ; $42
+    bbs2 a, LABEL       ; $43
+    com $12             ; $44
+    bbs2 $12, LABEL     ; $47
+    seb2 a              ; $4b
+    seb2 $12            ; $4f
+    bbc2 a, LABEL       ; $53
+    bbc2 $12, LABEL     ; $57
+    clb2 a              ; $5b
+    clb2 $12            ; $5f
+    bbs3 a, LABEL       ; $63
+    bbs3 $12, LABEL     ; $67
+    seb3 a              ; $6b
+    seb3 $12            ; $6f
+    bbc3 a, LABEL       ; $73
+    bbc3 $12, LABEL     ; $77
+    clb3 a              ; $7b
+    clb3 $12            ; $7f
+LABEL:
+    rrf $12             ; $82
+    bbs4 a, LABEL       ; $83
+    bbs4 $12, LABEL     ; $87
+    seb4 a              ; $8b
+    seb4 $12            ; $8f
+    bbc4 a, LABEL       ; $93
+    bbc4 $12, LABEL     ; $97
+    clb4 a              ; $9b
+    clb4 $12            ; $9f
+    bbs5 a, LABEL       ; $a3
+    bbs5 $12, LABEL     ; $a7
+    seb5 a              ; $ab
+    seb5 $12            ; $af
+    bbc5 a, LABEL       ; $b3
+    bbc5 $12, LABEL     ; $b7
+    clb5 a              ; $bb
+    clb5 $12            ; $bf
+    slw                 ; $c2
+    bbs6 a, LABEL       ; $c3
+    bbs6 $12, LABEL     ; $c7
+    seb6 a              ; $cb
+    seb6 $12            ; $cf
+    bbc6 a, LABEL       ; $d3
+    bbc6 $12, LABEL     ; $d7
+    clb6 a              ; $db
+    clb6 $12            ; $df
+    fst                 ; $e2
+    bbs7 a, LABEL       ; $e3
+    bbs7 $12, LABEL     ; $e7
+    seb7 a              ; $eb
+    seb7 $12            ; $ef
+    bbc7 a, LABEL       ; $f3
+    bbc7 $12, LABEL     ; $f7
+    clb7 a              ; $fb
+    clb7 $12            ; $ff
+
+    ; replaced from 65SC02
+    clt                 ; $12
+    set                 ; $32
+    ldm $12, #$34       ; $3c
+    tst $12             ; $64
+
+    ; removed from 65SC02 (replaced by new)
+    ; ora ($12)         ; $12
+    ; and ($12)         ; $32
+    ; bit $1234,x       ; $3c
+    ; stz $12           ; $64
+
+    ; removed from 65SC02
+    ; tsb $12           ; $04
+    ; tsb $1234         ; $0c
+    ; trb $12           ; $14
+    ; trb $1234         ; $1c
+    ; bit $12,y         ; $34
+    ; eor ($12)         ; $52
+    ; phy               ; $5a
+    ; adc ($12)         ; $72
+    ; stz $12,y         ; $74
+    ; ply               ; $7a
+    ; jmp ($1234)       ; $7c
+    ; bit #$12          ; $89
+    ; sta ($12)         ; $92
+    ; stz $1234         ; $9c
+    ; stz $1234,x       ; $9e
+    ; cmp ($12)         ; $d2
+    ; phx               ; $da
+    ; sbc ($12)         ; $f2
+    ; plx               ; $fa
+
+    .endscope
+.endif
+
diff --git a/test/asm/cpudetect/cpudetect.s b/test/asm/cpudetect/cpudetect.s
index 6ee07ae3c..a017e652d 100644
--- a/test/asm/cpudetect/cpudetect.s
+++ b/test/asm/cpudetect/cpudetect.s
@@ -32,6 +32,10 @@
    sac #$00
 .endif
 
+.ifpm740
+   jsr $ff12
+.endif
+
 
 ; step 2: check for bitwise compatibility of instructions sets
 ;         (made verbose for better reading with hexdump/hd(1))
@@ -76,6 +80,15 @@
    .byte 0,"CPU_ISET_6502DTV"
 .endif
 
+.if (.cpu .bitand CPU_ISET_M740)
+   .byte 0,"CPU_ISET_M740"
+.endif
+
+; FIXME: something with 65816 is quirky
+.if (.not .cpu .bitand CPU_ISET_65816)
+    .include "allinst.inc"
+.endif
+
 
 ; step 3: switch through all supported cpus to verify the pseudo-op is there
 
@@ -86,3 +99,4 @@
 .p816
 .p4510
 .pdtv
+.pm740
diff --git a/test/asm/cpudetect/m740-cpudetect.ref b/test/asm/cpudetect/m740-cpudetect.ref
new file mode 100644
index 000000000..7788f3ed9
Binary files /dev/null and b/test/asm/cpudetect/m740-cpudetect.ref differ
diff --git a/test/asm/opcodes/m740-opcodes.ref b/test/asm/opcodes/m740-opcodes.ref
new file mode 100644
index 000000000..b3cffc9b6
Binary files /dev/null and b/test/asm/opcodes/m740-opcodes.ref differ
diff --git a/test/asm/opcodes/m740-opcodes.s b/test/asm/opcodes/m740-opcodes.s
index df6d71488..e4f8562cc 100644
--- a/test/asm/opcodes/m740-opcodes.s
+++ b/test/asm/opcodes/m740-opcodes.s
@@ -1,260 +1,565 @@
-.setcpu "65C02"
-; copy of 65c02, comments note changes to the m740 according to
-; http://documentation.renesas.com/doc/products/mpumcu/rej09b0322_740sm.pdf
+; da65 V2.19 - Git 89651fd8b
+; Created:    2025-06-16 20:10:42
+; Input file: testfile
+; Page:       1
 
-   brk
-   ora     ($12,x)
-   .byte   $02,$00,$00 ; jsr zp,ind
-   .byte   $03,$00,$00 ; bbs 0,a
-   tsb     $12         ; .byte $04
-   ora     $12
-   asl     $12
-   rmb0    $12         ; bbs 0,zp
-   php
-   ora     #$12
-   asl     a
-   .byte   $0B,$00,$00 ; seb 0,a
-   tsb     $3456       ; .byte $0c
-   ora     $3456
-   asl     $3456
-   bbr0    $12,*+122   ; seb 0,zp
-   bpl     *+122
-   ora     ($12),y
-   ora     ($12)       ; clt
-   .byte   $13,$00,$00 ; bbc 0,a
-   trb     $12         ; .byte $14
-   ora     $12,x
-   asl     $12,x
-   rmb1    $12         ; bbc 0,zp
-   clc
-   ora     $3456,y
-   inc     a
-   .byte   $1B,$00,$00 ; clb 0,a
-   trb     $3456       ; .byte $1c
-   ora     $3456,x
-   asl     $3456,x
-   bbr1    $12,*+122   ; clb 0,zp
-   jsr     $3456
-   and     ($12,x)
-   .byte   $22,$00,$00 ; jsr sp
-   .byte   $23,$00,$00 ; bbs 1,a
-   bit     $12
-   and     $12
-   rol     $12
-   rmb2    $12         ; bbs 1,zp
-   plp
-   and     #$12
-   rol     a
-   .byte   $2B,$00,$00 ; seb 1,a
-   bit     $3456
-   and     $3456
-   rol     $3456
-   bbr2    $12,*+122   ; seb 1,zp
-   bmi     *+122
-   and     ($12),y
-   and     ($12)       ; set
-   .byte   $33,$00,$00 ; bbc 1,a
-   bit     $12,x       ; .byte $34
-   and     $12,x
-   rol     $12,x
-   rmb3    $12         ; bbc 1,zp
-   sec
-   and     $3456,y
-   dec     a
-   .byte   $3B,$00,$00 ; clb 1,a
-   bit     $3456,x     ; ldm zp
-   and     $3456,x
-   rol     $3456,x
-   bbr3    $12,*+122   ; clb 1,zp
-   rti
-   eor     ($12,x)
-   .byte   $42,$00,$00 ; stp
-   .byte   $43,$00,$00 ; bbs 2,a
-   .byte   $44,$00,$00 ; com zp
-   eor     $12
-   lsr     $12
-   rmb4    $12         ; bbs 2,zp
-   pha
-   eor     #$12
-   lsr     a
-   .byte   $4B,$00,$00 ; seb 2,a
-   jmp     $3456
-   eor     $3456
-   lsr     $3456
-   bbr4    $12,*+122   ; seb 2,zp
-   bvc     *+122
-   eor     ($12),y
-   eor     ($12)       ; .byte $52
-   .byte   $53,$00,$00 ; bbc 2,a
-   .byte   $54,$00,$00
-   eor     $12,x
-   lsr     $12,x
-   rmb5    $12         ; bbc 2,zp
-   cli
-   eor     $3456,y
-   phy
-   .byte   $5B,$00,$00 ; clb 2,a
-   .byte   $5C,$00,$00
-   eor     $3456,x
-   lsr     $3456,x
-   bbr5    $12,*+122   ; clb 2,zp
-   rts
-   adc     ($12,x)
-   .byte   $62,$00,$00 ; mul zp,x
-   .byte   $63,$00,$00 ; bbs 3,a
-   stz     $12         ; tst zp
-   adc     $12
-   ror     $12
-   rmb6    $12         ; bbs 3,zp
-   pla
-   adc     #$12
-   ror     a
-   .byte   $6B,$00,$00 ; seb 3,a
-   jmp     ($3456)
-   adc     $3456
-   ror     $3456
-   bbr6    $12,*+122   ; seb 3,zp
-   bvs     *+122
-   adc     ($12),y
-   adc     ($12)       ; .byte $72
-   .byte   $73,$00,$00 ; bbc 3,a
-   stz     $12,x       ; .byte $74
-   adc     $12,x
-   ror     $12,x
-   rmb7    $12         ; bbc 3,zp
-   sei
-   adc     $3456,y
-   ply
-   .byte   $7B,$00,$00 ; clb 3,a
-   jmp     ($3456,x)   ; .byte $7c
-   adc     $3456,x
-   ror     $3456,x
-   bbr7    $12,*+122   ; clb 3,zp
-   bra     *+122
-   sta     ($12,x)
-   .byte   $82,$00,$00 ; rrf zp
-   .byte   $83,$00,$00 ; bbs 4,a
-   sty     $12
-   sta     $12
-   stx     $12
-   smb0    $12         ; bbs 4,zp
-   dey
-   bit     #$12
-   txa
-   .byte   $8B,$00,$00 ; seb 4,a
-   sty     $3456
-   sta     $3456
-   stx     $3456
-   bbs0    $12,*+122   ; seb 4,zp
-   bcc     *+122
-   sta     ($12),y
-   sta     ($12)       ; .byte $92
-   .byte   $93,$00,$00 ; bbc 4,a
-   sty     $12,x
-   sta     $12,x
-   stx     $12,y
-   smb1    $12         ; bbc 4,zp
-   tya
-   sta     $3456,y
-   txs
-   .byte   $9B,$00,$00 ; clb 4,a
-   stz     $3456       ; .byte $9c
-   sta     $3456,x
-   stz     $3456,x     ; .byte $9e
-   bbs1    $12,*+122   ; clb 4,zp
-   ldy     #$12
-   lda     ($12,x)
-   ldx     #$12
-   .byte   $A3,$00,$00 ; bbs 5,a
-   ldy     $12
-   lda     $12
-   ldx     $12
-   smb2    $12         ; bbs 5,zp
-   tay
-   lda     #$12
-   tax
-   .byte   $AB,$00,$00 ; seb 5,a
-   ldy     $3456
-   lda     $3456
-   ldx     $3456
-   bbs2    $12,*+122   ; seb 5,zp
-   bcs     *+122
-   lda     ($12),y
-   lda     ($12)       ; .byte $b2
-   .byte   $B3,$00,$00 ; bbc 5,a
-   ldy     $12,x
-   lda     $12,x
-   ldx     $12,y
-   smb3    $12         ; bbc 5,zp
-   clv
-   lda     $3456,y
-   tsx
-   .byte   $BB,$00,$00 ; clb 5,a
-   ldy     $3456,x
-   lda     $3456,x
-   ldx     $3456,y
-   bbs3    $12,*+122   ; clb 5,zp
-   cpy     #$12
-   cmp     ($12,x)
-   .byte   $C2,$00,$00 ; wit
-   .byte   $C3,$00,$00 ; bbs 6,a
-   cpy     $12
-   cmp     $12
-   dec     $12
-   smb4    $12         ; bbs 6,zp
-   iny
-   cmp     #$12
-   dex
-   .byte   $CB,$00,$00 ; seb 6,a
-   cpy     $3456
-   cmp     $3456
-   dec     $3456
-   bbs4    $12,*+122   ; seb 6,zp
-   bne     *+122
-   cmp     ($12),y
-   cmp     ($12)       ; .byte $d2
-   .byte   $D3,$00,$00 ; bbc 6,a
-   .byte   $D4,$00,$00
-   cmp     $12,x
-   dec     $12,x
-   smb5    $12         ; bbc 6,zp
-   cld
-   cmp     $3456,y
-   phx
-   .byte   $DB,$00,$00 ; clb 6,a
-   .byte   $DC,$00,$00
-   cmp     $3456,x
-   dec     $3456,x
-   bbs5    $12,*+122   ; clb 6,zp
-   cpx     #$12
-   sbc     ($12,x)
-   .byte   $E2,$00,$00 ; div zp,x
-   .byte   $E3,$00,$00 ; bbs 7,a
-   cpx     $12
-   sbc     $12
-   inc     $12
-   smb6    $12         ; bbs 7,zp
-   inx
-   sbc     #$12
-   nop
-   .byte   $EB,$00,$00 ; seb 7,a
-   cpx     $3456
-   sbc     $3456
-   inc     $3456
-   bbs6    $12,*+122   ; seb 7,zp
-   beq     *+122
-   sbc     ($12),y
-   sbc     ($12)       ; .byte $f2
-   .byte   $F3,$00,$00 ; bbc 7,a
-   .byte   $F4,$00,$00
-   sbc     $12,x
-   inc     $12,x
-   smb7    $12         ; bbc 7,zp
-   sed
-   sbc     $3456,y
-   plx
-   .byte   $FB,$00,$00 ; clb 7,a
-   .byte   $FC,$00,$00
-   sbc     $3456,x
-   inc     $3456,x
-   bbs7    $12,*+122   ; clb 7,zp
+
+        .setcpu "m740"
+
+L000C           := $000C
+L040C           := $040C
+LFF0C           := $FF0C
+        brk
+        .byte   $0C
+        .byte   $04
+        ora     (L000C,x)
+        .byte   $04
+        jsr     (L000C)
+
+        .byte   $04
+        bbs0    a, L8018
+        .byte   $04
+        .byte   $04
+        .byte   $0C
+        .byte   $04
+        ora     L000C
+        .byte   $04
+        asl     L000C
+        .byte   $04
+        bbs0    L000C, L801C
+L8018:  php
+        .byte   $0C
+        .byte   $04
+        .byte   $09
+L801C:  .byte   $0C
+        .byte   $04
+        asl     a
+        .byte   $0C
+        .byte   $04
+        seb0    a
+        .byte   $0C
+        .byte   $04
+        .byte   $0C
+        .byte   $0C
+        .byte   $04
+        ora     L040C
+        asl     L040C
+        seb0    L000C
+        .byte   $04
+        bpl     L803E
+        .byte   $04
+        ora     (L000C),y
+        .byte   $04
+        clt
+        .byte   $0C
+        .byte   $04
+        bbc0    a, L8048
+        .byte   $04
+        .byte   $14
+        .byte   $0C
+L803E:  .byte   $04
+        ora     L000C,x
+        .byte   $04
+        asl     L000C,x
+        .byte   $04
+        bbc0    L000C, L804C
+L8048:  clc
+        .byte   $0C
+        .byte   $04
+        .byte   $19
+L804C:  .byte   $0C
+        .byte   $04
+        inc     a
+        .byte   $0C
+        .byte   $04
+        clb0    a
+        .byte   $0C
+        .byte   $04
+        .byte   $1C
+        .byte   $0C
+        .byte   $04
+        ora     L040C,x
+        asl     L040C,x
+        clb0    L000C
+        .byte   $04
+        jsr     L040C
+        and     (L000C,x)
+        .byte   $04
+        jsr     LFF0C
+        .byte   $04
+        bbs1    a, L8078
+        .byte   $04
+        bit     L000C
+        .byte   $04
+        and     L000C
+        .byte   $04
+        rol     L000C
+        .byte   $04
+        bbs1    L000C, L807C
+L8078:  plp
+        .byte   $0C
+        .byte   $04
+        .byte   $29
+L807C:  .byte   $0C
+        .byte   $04
+        rol     a
+        .byte   $0C
+        .byte   $04
+        seb1    a
+        .byte   $0C
+        .byte   $04
+        bit     L040C
+        and     L040C
+        rol     L040C
+        seb1    L000C
+        .byte   $04
+        bmi     L809E
+        .byte   $04
+        and     (L000C),y
+        .byte   $04
+        set
+        .byte   $0C
+        .byte   $04
+        bbc1    a, L80A8
+        .byte   $04
+        .byte   $34
+        .byte   $0C
+L809E:  .byte   $04
+        and     L000C,x
+        .byte   $04
+        rol     L000C,x
+        .byte   $04
+        bbc1    L000C, L80AC
+L80A8:  sec
+        .byte   $0C
+        .byte   $04
+        .byte   $39
+L80AC:  .byte   $0C
+        .byte   $04
+        dec     a
+        .byte   $0C
+        .byte   $04
+        clb1    a
+        .byte   $0C
+        .byte   $04
+        ldm     L000C, #$04
+        and     L040C,x
+        rol     L040C,x
+        clb1    L000C
+        .byte   $04
+        rti
+
+        .byte   $0C
+        .byte   $04
+        eor     (L000C,x)
+        .byte   $04
+        stp
+        .byte   $0C
+        .byte   $04
+        bbs2    a, L80D8
+        .byte   $04
+        com     L000C
+        .byte   $04
+        eor     L000C
+        .byte   $04
+        lsr     L000C
+        .byte   $04
+        bbs2    L000C, L80DC
+L80D8:  pha
+        .byte   $0C
+        .byte   $04
+        .byte   $49
+L80DC:  .byte   $0C
+        .byte   $04
+        lsr     a
+        .byte   $0C
+        .byte   $04
+        seb2    a
+        .byte   $0C
+        .byte   $04
+        jmp     L040C
+
+        eor     L040C
+        lsr     L040C
+        seb2    L000C
+        .byte   $04
+        bvc     L80FE
+        .byte   $04
+        eor     (L000C),y
+        .byte   $04
+        .byte   $52
+        .byte   $0C
+        .byte   $04
+        bbc2    a, L8108
+        .byte   $04
+        .byte   $54
+        .byte   $0C
+L80FE:  .byte   $04
+        eor     L000C,x
+        .byte   $04
+        lsr     L000C,x
+        .byte   $04
+        bbc2    L000C, L810C
+L8108:  cli
+        .byte   $0C
+        .byte   $04
+        .byte   $59
+L810C:  .byte   $0C
+        .byte   $04
+        .byte   $5A
+        .byte   $0C
+        .byte   $04
+        clb2    a
+        .byte   $0C
+        .byte   $04
+        .byte   $5C
+        .byte   $0C
+        .byte   $04
+        eor     L040C,x
+        lsr     L040C,x
+        clb2    L000C
+        .byte   $04
+        rts
+
+        .byte   $0C
+        .byte   $04
+        adc     (L000C,x)
+        .byte   $04
+        .byte   $62
+        .byte   $0C
+        .byte   $04
+        bbs3    a, L8138
+        .byte   $04
+        tst     L000C
+        .byte   $04
+        adc     L000C
+        .byte   $04
+        ror     L000C
+        .byte   $04
+        bbs3    L000C, L813C
+L8138:  pla
+        .byte   $0C
+        .byte   $04
+        .byte   $69
+L813C:  .byte   $0C
+        .byte   $04
+        ror     a
+        .byte   $0C
+        .byte   $04
+        seb3    a
+        .byte   $0C
+        .byte   $04
+        jmp     (L040C)
+
+        adc     L040C
+        ror     L040C
+        seb3    L000C
+        .byte   $04
+        bvs     L815E
+        .byte   $04
+        adc     (L000C),y
+        .byte   $04
+        .byte   $72
+        .byte   $0C
+        .byte   $04
+        bbc3    a, L8168
+        .byte   $04
+        .byte   $74
+        .byte   $0C
+L815E:  .byte   $04
+        adc     L000C,x
+        .byte   $04
+        ror     L000C,x
+        .byte   $04
+        bbc3    L000C, L816C
+L8168:  sei
+        .byte   $0C
+        .byte   $04
+        .byte   $79
+L816C:  .byte   $0C
+        .byte   $04
+        .byte   $7A
+        .byte   $0C
+        .byte   $04
+        clb3    a
+        .byte   $0C
+        .byte   $04
+        .byte   $7C
+        .byte   $0C
+        .byte   $04
+        adc     L040C,x
+        ror     L040C,x
+        clb3    L000C
+        .byte   $04
+        bra     L818E
+        .byte   $04
+        sta     (L000C,x)
+        .byte   $04
+        rrf     L000C
+        .byte   $04
+        bbs4    a, L8198
+        .byte   $04
+        sty     L000C
+L818E:  .byte   $04
+        sta     L000C
+        .byte   $04
+        stx     L000C
+        .byte   $04
+        bbs4    L000C, L819C
+L8198:  dey
+        .byte   $0C
+        .byte   $04
+        .byte   $89
+L819C:  .byte   $0C
+        .byte   $04
+        txa
+        .byte   $0C
+        .byte   $04
+        seb4    a
+        .byte   $0C
+        .byte   $04
+        sty     L040C
+        sta     L040C
+        stx     L040C
+        seb4    L000C
+        .byte   $04
+        bcc     L81BE
+        .byte   $04
+        sta     (L000C),y
+        .byte   $04
+        .byte   $92
+        .byte   $0C
+        .byte   $04
+        bbc4    a, L81C8
+        .byte   $04
+        sty     L000C,x
+L81BE:  .byte   $04
+        sta     L000C,x
+        .byte   $04
+        stx     L000C,y
+        .byte   $04
+        bbc4    L000C, L81CC
+L81C8:  tya
+        .byte   $0C
+        .byte   $04
+        .byte   $99
+L81CC:  .byte   $0C
+        .byte   $04
+        txs
+        .byte   $0C
+        .byte   $04
+        clb4    a
+        .byte   $0C
+        .byte   $04
+        .byte   $9C
+        .byte   $0C
+        .byte   $04
+        sta     L040C,x
+        .byte   $9E
+        .byte   $0C
+        .byte   $04
+        clb4    L000C
+        .byte   $04
+        ldy     #$0C
+        .byte   $04
+        lda     (L000C,x)
+        .byte   $04
+        ldx     #$0C
+        .byte   $04
+        bbs5    a, L81F8
+        .byte   $04
+        ldy     L000C
+        .byte   $04
+        lda     L000C
+        .byte   $04
+        ldx     L000C
+        .byte   $04
+        bbs5    L000C, L81FC
+L81F8:  tay
+        .byte   $0C
+        .byte   $04
+        .byte   $A9
+L81FC:  .byte   $0C
+        .byte   $04
+        tax
+        .byte   $0C
+        .byte   $04
+        seb5    a
+        .byte   $0C
+        .byte   $04
+        ldy     L040C
+        lda     L040C
+        ldx     L040C
+        seb5    L000C
+        .byte   $04
+        bcs     L821E
+        .byte   $04
+        lda     (L000C),y
+        .byte   $04
+        jmp     (L000C)
+
+        .byte   $04
+        bbc5    a, L8228
+        .byte   $04
+        ldy     L000C,x
+L821E:  .byte   $04
+        lda     L000C,x
+        .byte   $04
+        ldx     L000C,y
+        .byte   $04
+        bbc5    L000C, L822C
+L8228:  clv
+        .byte   $0C
+        .byte   $04
+        .byte   $B9
+L822C:  .byte   $0C
+        .byte   $04
+        tsx
+        .byte   $0C
+        .byte   $04
+        clb5    a
+        .byte   $0C
+        .byte   $04
+        ldy     L040C,x
+        lda     L040C,x
+        ldx     L040C,y
+        clb5    L000C
+        .byte   $04
+        cpy     #$0C
+        .byte   $04
+        cmp     (L000C,x)
+        .byte   $04
+        slw
+        .byte   $0C
+        .byte   $04
+        bbs6    a, L8258
+        .byte   $04
+        cpy     L000C
+        .byte   $04
+        cmp     L000C
+        .byte   $04
+        dec     L000C
+        .byte   $04
+        bbs6    L000C, L825C
+L8258:  iny
+        .byte   $0C
+        .byte   $04
+        .byte   $C9
+L825C:  .byte   $0C
+        .byte   $04
+        dex
+        .byte   $0C
+        .byte   $04
+        seb6    a
+        .byte   $0C
+        .byte   $04
+        cpy     L040C
+        cmp     L040C
+        dec     L040C
+        seb6    L000C
+        .byte   $04
+        bne     L827E
+        .byte   $04
+        cmp     (L000C),y
+        .byte   $04
+        .byte   $D2
+        .byte   $0C
+        .byte   $04
+        bbc6    a, L8288
+        .byte   $04
+        .byte   $D4
+        .byte   $0C
+L827E:  .byte   $04
+        cmp     L000C,x
+        .byte   $04
+        dec     L000C,x
+        .byte   $04
+        bbc6    L000C, L828C
+L8288:  cld
+        .byte   $0C
+        .byte   $04
+        .byte   $D9
+L828C:  .byte   $0C
+        .byte   $04
+        .byte   $DA
+        .byte   $0C
+        .byte   $04
+        clb6    a
+        .byte   $0C
+        .byte   $04
+        .byte   $DC
+        .byte   $0C
+        .byte   $04
+        cmp     L040C,x
+        dec     L040C,x
+        clb6    L000C
+        .byte   $04
+        cpx     #$0C
+        .byte   $04
+        sbc     (L000C,x)
+        .byte   $04
+        fst
+        .byte   $0C
+        .byte   $04
+        bbs7    a, L82B8
+        .byte   $04
+        cpx     L000C
+        .byte   $04
+        sbc     L000C
+        .byte   $04
+        inc     L000C
+        .byte   $04
+        bbs7    L000C, L82BC
+L82B8:  inx
+        .byte   $0C
+        .byte   $04
+        .byte   $E9
+L82BC:  .byte   $0C
+        .byte   $04
+        nop
+        .byte   $0C
+        .byte   $04
+        seb7    a
+        .byte   $0C
+        .byte   $04
+        cpx     L040C
+        sbc     L040C
+        inc     L040C
+        seb7    L000C
+        .byte   $04
+        beq     L82DE
+        .byte   $04
+        sbc     (L000C),y
+        .byte   $04
+        .byte   $F2
+        .byte   $0C
+        .byte   $04
+        bbc7    a, L82E8
+        .byte   $04
+        .byte   $F4
+        .byte   $0C
+L82DE:  .byte   $04
+        sbc     L000C,x
+        .byte   $04
+        inc     L000C,x
+        .byte   $04
+        bbc7    L000C, L82EC
+L82E8:  sed
+        .byte   $0C
+        .byte   $04
+        .byte   $F9
+L82EC:  .byte   $0C
+        .byte   $04
+        .byte   $FA
+        .byte   $0C
+        .byte   $04
+        clb7    a
+        .byte   $0C
+        .byte   $04
+        .byte   $FC
+        .byte   $0C
+        .byte   $04
+        sbc     L040C,x
+        inc     L040C,x
+        clb7    L000C
+        .byte   $04