From 5be4c4697c33b1e9780122a43cb564b151bf0fd8 Mon Sep 17 00:00:00 2001 From: mrdudz Date: Sun, 15 Jun 2025 18:25:01 +0200 Subject: [PATCH 01/26] original patch --- cfg/m740.cfg | 37 +++++++++++ src/ca65/instr.c | 156 +++++++++++++++++++++++++++++++++++++++++++-- src/ca65/instr.h | 67 ++++++++++--------- src/da65/handler.c | 15 +++++ src/da65/handler.h | 1 + src/da65/opcm740.c | 32 +++++----- 6 files changed, 256 insertions(+), 52 deletions(-) create mode 100644 cfg/m740.cfg diff --git a/cfg/m740.cfg b/cfg/m740.cfg new file mode 100644 index 000000000..e68bff0f5 --- /dev/null +++ b/cfg/m740.cfg @@ -0,0 +1,37 @@ +FEATURES { + STARTADDRESS: default = $8000; +} +SYMBOLS { + __STACKSIZE__: type = weak, value = $0000; # 2k stack + __STACKSTART__: type = weak, value = $100; + __ZPSTART__: type = weak, value = $0000; +} +MEMORY { + ZP: file = "", define = yes, start = __ZPSTART__, size = $001F; + MAIN: file = %O, start = %S, size = __STACKSTART__ - __STACKSIZE__ - %S; +} +SEGMENTS { + ZEROPAGE: load = ZP, type = zp; + STARTUP: load = MAIN, type = ro, optional = yes; + LOWCODE: load = MAIN, type = ro, optional = yes; + ONCE: load = MAIN, type = ro, optional = yes; + CODE: load = MAIN, type = rw; + RODATA: load = MAIN, type = rw; + DATA: load = MAIN, type = rw; + BSS: load = MAIN, type = bss, define = yes; +} +FEATURES { + CONDES: type = constructor, + label = __CONSTRUCTOR_TABLE__, + count = __CONSTRUCTOR_COUNT__, + segment = ONCE; + CONDES: type = destructor, + label = __DESTRUCTOR_TABLE__, + count = __DESTRUCTOR_COUNT__, + segment = RODATA; + CONDES: type = interruptor, + label = __INTERRUPTOR_TABLE__, + count = __INTERRUPTOR_COUNT__, + segment = RODATA, + import = __CALLIRQ__; +} diff --git a/src/ca65/instr.c b/src/ca65/instr.c index c7a68006c..ddbd12125 100644 --- a/src/ca65/instr.c +++ b/src/ca65/instr.c @@ -85,6 +85,12 @@ static void PutBlockTransfer (const InsDesc* Ins); static void PutBitBranch (const InsDesc* Ins); /* Handle 65C02 branch on bit condition */ +static void PutBitBranchm740 (const InsDesc* Ins); +/* Handle m740 branch on bit condition */ + +static void PutLDMm740 (const InsDesc* Ins); +/* Handle m740 LDM instruction */ + static void PutREP (const InsDesc* Ins); /* Emit a REP instruction, track register sizes */ @@ -1047,7 +1053,114 @@ static const struct { } }; - +/* Instruction table for the m740 CPU */ +static const struct { + unsigned Count; + InsDesc Ins[97]; +} InsTabm740 = { + sizeof (InsTabm740.Ins) / sizeof (InsTabm740.Ins[0]), + { +/* BEGIN SORTED.SH */ + { "ADC", 0x080A26C, 0x60, 0, PutAll }, + { "AND", 0x080A26C, 0x20, 0, PutAll }, + { "ASL", 0x000006e, 0x02, 1, PutAll }, + { "BBR0", 0x0000006, 0x13, 10, PutBitBranchm740 }, + { "BBR1", 0x0000006, 0x33, 10, PutBitBranchm740 }, + { "BBR2", 0x0000006, 0x53, 10, PutBitBranchm740 }, + { "BBR3", 0x0000006, 0x73, 10, PutBitBranchm740 }, + { "BBR4", 0x0000006, 0x93, 10, PutBitBranchm740 }, + { "BBR5", 0x0000006, 0xb3, 10, PutBitBranchm740 }, + { "BBR6", 0x0000006, 0xd3, 10, PutBitBranchm740 }, + { "BBR7", 0x0000006, 0xf3, 10, PutBitBranchm740 }, + { "BBS0", 0x0000006, 0x03, 10, PutBitBranchm740 }, + { "BBS1", 0x0000006, 0x23, 10, PutBitBranchm740 }, + { "BBS2", 0x0000006, 0x43, 10, PutBitBranchm740 }, + { "BBS3", 0x0000006, 0x63, 10, PutBitBranchm740 }, + { "BBS4", 0x0000006, 0x83, 10, PutBitBranchm740 }, + { "BBS5", 0x0000006, 0xa3, 10, PutBitBranchm740 }, + { "BBS6", 0x0000006, 0xc3, 10, PutBitBranchm740 }, + { "BBS7", 0x0000006, 0xe3, 10, PutBitBranchm740 }, + { "BCC", 0x0020000, 0x90, 0, PutPCRel8 }, + { "BCS", 0x0020000, 0xb0, 0, PutPCRel8 }, + { "BEQ", 0x0020000, 0xf0, 0, PutPCRel8 }, + { "BIT", 0x000000C, 0x00, 2, PutAll }, + { "BMI", 0x0020000, 0x30, 0, PutPCRel8 }, + { "BNE", 0x0020000, 0xd0, 0, PutPCRel8 }, + { "BPL", 0x0020000, 0x10, 0, PutPCRel8 }, + { "BRA", 0x0020000, 0x80, 0, PutPCRel8 }, + { "BRK", 0x0000001, 0x00, 0, PutAll }, + { "BVC", 0x0020000, 0x50, 0, PutPCRel8 }, + { "BVS", 0x0020000, 0x70, 0, PutPCRel8 }, + { "CLC", 0x0000001, 0x18, 0, PutAll }, + { "CLD", 0x0000001, 0xd8, 0, PutAll }, + { "CLI", 0x0000001, 0x58, 0, PutAll }, + { "CLT", 0x0000001, 0x12, 0, PutAll }, + { "CLV", 0x0000001, 0xb8, 0, PutAll }, + { "CMP", 0x080A26C, 0xc0, 0, PutAll }, + { "COM", 0x0000004, 0x44, 1, PutAll }, + { "CPX", 0x080000C, 0xe0, 1, PutAll }, + { "CPY", 0x080000C, 0xc0, 1, PutAll }, + { "DEC", 0x000006F, 0x00, 3, PutAll }, + { "DEX", 0x0000001, 0xca, 0, PutAll }, + { "DEY", 0x0000001, 0x88, 0, PutAll }, + { "EOR", 0x080A26C, 0x40, 0, PutAll }, + { "FST", 0x0000001, 0xe2, 0, PutAll }, + { "INC", 0x000006f, 0x00, 4, PutAll }, + { "INX", 0x0000001, 0xe8, 0, PutAll }, + { "INY", 0x0000001, 0xc8, 0, PutAll }, + { "JMP", 0x0000C08, 0x00, 12, PutAll }, + { "JSR", 0x0080808, 0x00, 13, PutAll }, + { "LDA", 0x080A26C, 0xa0, 0, PutAll }, + { "LDM", 0x0000004, 0x3c, 6, PutLDMm740 }, + { "LDX", 0x080030C, 0xa2, 1, PutAll }, + { "LDY", 0x080006C, 0xa0, 1, PutAll }, + { "LSR", 0x000006F, 0x42, 1, PutAll }, + { "NOP", 0x0000001, 0xea, 0, PutAll }, + { "ORA", 0x080A26C, 0x00, 0, PutAll }, + { "PHA", 0x0000001, 0x48, 0, PutAll }, + { "PHP", 0x0000001, 0x08, 0, PutAll }, + { "PLA", 0x0000001, 0x68, 0, PutAll }, + { "PLP", 0x0000001, 0x28, 0, PutAll }, + { "RMB0", 0x0000006, 0x1b, 10, PutAll }, + { "RMB1", 0x0000006, 0x3b, 10, PutAll }, + { "RMB2", 0x0000006, 0x5b, 10, PutAll }, + { "RMB3", 0x0000006, 0x7b, 10, PutAll }, + { "RMB4", 0x0000006, 0x9b, 10, PutAll }, + { "RMB5", 0x0000006, 0xbb, 10, PutAll }, + { "RMB6", 0x0000006, 0xdb, 10, PutAll }, + { "RMB7", 0x0000006, 0xfb, 10, PutAll }, + { "ROL", 0x000006F, 0x22, 1, PutAll }, + { "ROR", 0x000006F, 0x62, 1, PutAll }, + { "RRF", 0x0000004, 0x82, 6, PutAll }, + { "RTI", 0x0000001, 0x40, 0, PutAll }, + { "RTS", 0x0000001, 0x60, 0, PutAll }, + { "SBC", 0x080A26C, 0xe0, 0, PutAll }, + { "SEC", 0x0000001, 0x38, 0, PutAll }, + { "SED", 0x0000001, 0xf8, 0, PutAll }, + { "SEI", 0x0000001, 0x78, 0, PutAll }, + { "SET", 0x0000001, 0x32, 0, PutAll }, + { "SLW", 0x0000001, 0xC2, 0, PutAll }, + { "SMB0", 0x0000006, 0x0b, 10, PutAll }, + { "SMB1", 0x0000006, 0x2b, 10, PutAll }, + { "SMB2", 0x0000006, 0x4b, 10, PutAll }, + { "SMB3", 0x0000006, 0x6b, 10, PutAll }, + { "SMB4", 0x0000006, 0x8b, 10, PutAll }, + { "SMB5", 0x0000006, 0xab, 10, PutAll }, + { "SMB6", 0x0000006, 0xcb, 10, PutAll }, + { "SMB7", 0x0000006, 0xeb, 10, PutAll }, + { "STA", 0x000A26C, 0x80, 0, PutAll }, + { "STP", 0x0000001, 0x42, 0, PutAll }, + { "STX", 0x000010c, 0x82, 1, PutAll }, + { "STY", 0x000002c, 0x80, 1, PutAll }, + { "TAX", 0x0000001, 0xaa, 0, PutAll }, + { "TAY", 0x0000001, 0xa8, 0, PutAll }, + { "TSX", 0x0000001, 0xba, 0, PutAll }, + { "TXA", 0x0000001, 0x8a, 0, PutAll }, + { "TXS", 0x0000001, 0x9a, 0, PutAll }, + { "TYA", 0x0000001, 0x98, 0, PutAll } +/* END SORTED.SH */ + } +}; /* An array with instruction tables */ static const InsTable* InsTabs[CPU_COUNT] = { @@ -1060,7 +1173,7 @@ static const InsTable* InsTabs[CPU_COUNT] = { (const InsTable*) &InsTab65816, (const InsTable*) &InsTabSweet16, (const InsTable*) &InsTabHuC6280, - 0, /* Mitsubishi 740 */ + (const InsTable*) &InsTabm740, /* Mitsubishi 740 */ (const InsTable*) &InsTab4510, }; const InsTable* InsTab = (const InsTable*) &InsTab6502; @@ -1068,7 +1181,7 @@ const InsTable* InsTab = (const InsTable*) &InsTab6502; /* Table to build the effective 65xx opcode from a base opcode and an ** addressing mode. (The value in the table is ORed with the base opcode) */ -static unsigned char EATab[12][AM65I_COUNT] = { +static unsigned char EATab[14][AM65I_COUNT] = { { /* Table 0 */ 0x00, 0x00, 0x05, 0x0D, 0x0F, 0x15, 0x1D, 0x1F, 0x00, 0x19, 0x12, 0x00, 0x07, 0x11, 0x17, 0x01, @@ -1141,6 +1254,18 @@ static unsigned char EATab[12][AM65I_COUNT] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x80, 0x00 }, + { /* Table 12 m740 JMP */ + 0x00, 0x00, 0x00, 0x4c, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xb2, 0x6c, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }, + { /* Table 13 m740 JSR */ + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }, }; /* Table to build the effective SWEET16 opcode from a base opcode and an @@ -1361,6 +1486,12 @@ static void EmitCode (EffAddr* A) } +static void PutLDMm740 (const InsDesc* Ins) +{ + + Emit0 (Ins->BaseCode); + EmitWord (Expression ()); +} static long PutImmed8 (const InsDesc* Ins) /* Parse and emit an immediate 8 bit instruction. Return the value of the @@ -1481,6 +1612,22 @@ static void PutBitBranch (const InsDesc* Ins) EmitSigned (GenBranchExpr (1), 1); } +static void PutBitBranchm740 (const InsDesc* Ins) +/* Handle 65C02 branch on bit condition */ +{ + EffAddr A; + + /* HACK: hardcoded for zp addressing mode, this doesn't work all the time */ + A.AddrMode = 2; + + A.Opcode = Ins->BaseCode | EATab[Ins->ExtCode][A.AddrMode]; + /* Evaluate the addressing mode used */ + /* No error, output code */ + Emit0 (A.Opcode); + EmitByte (Expression ()); + ConsumeComma (); + EmitSigned (GenBranchExpr (1), 1); +} static void PutREP (const InsDesc* Ins) @@ -1584,7 +1731,6 @@ static void PutTMAn (const InsDesc* Ins) ** an immediate argument. */ { - /* Emit the TMA opcode itself */ Emit0 (0x43); /* Emit the argument, which is the opcode from the table */ @@ -1640,10 +1786,8 @@ static void PutJMP (const InsDesc* Ins) */ { EffAddr A; - /* Evaluate the addressing mode used */ if (EvalEA (Ins, &A)) { - /* Check for indirect addressing */ if ((A.AddrModeBit & AM65_ABS_IND) && (CPU < CPU_65SC02) && (RelaxChecks == 0)) { diff --git a/src/ca65/instr.h b/src/ca65/instr.h index fe18d2110..823aa5659 100644 --- a/src/ca65/instr.h +++ b/src/ca65/instr.h @@ -58,53 +58,60 @@ ** When assembling for the 6502 or 65C02, all addressing modes that are not ** available on these CPUs are removed before doing any checks. */ -#define AM65_IMPLICIT 0x00000003UL -#define AM65_ACCU 0x00000002UL -#define AM65_DIR 0x00000004UL -#define AM65_ABS 0x00000008UL -#define AM65_ABS_LONG 0x00000010UL -#define AM65_DIR_X 0x00000020UL -#define AM65_ABS_X 0x00000040UL -#define AM65_ABS_LONG_X 0x00000080UL -#define AM65_DIR_Y 0x00000100UL -#define AM65_ABS_Y 0x00000200UL -#define AM65_DIR_IND 0x00000400UL -#define AM65_ABS_IND 0x00000800UL -#define AM65_DIR_IND_LONG 0x00001000UL -#define AM65_DIR_IND_Y 0x00002000UL -#define AM65_DIR_IND_LONG_Y 0x00004000UL -#define AM65_DIR_X_IND 0x00008000UL -#define AM65_ABS_X_IND 0x00010000UL -#define AM65_REL 0x00020000UL -#define AM65_REL_LONG 0x00040000UL -#define AM65_STACK_REL 0x00080000UL -#define AM65_STACK_REL_IND_Y 0x00100000UL +#define AM65_IMPLICIT 0x00000003UL /* IMP */ +#define AM65_ACCU 0x00000002UL /* A, BIT, A */ +#define AM65_DIR 0x00000004UL /* ZP, BIT, ZP */ +#define AM65_ABS 0x00000008UL /* ABS */ +#define AM65_ABS_LONG 0x00000010UL /* -- */ +#define AM65_DIR_X 0x00000020UL /* ZP,X */ +#define AM65_ABS_X 0x00000040UL /* ABS, X */ +#define AM65_ABS_LONG_X 0x00000080UL /* -- */ +#define AM65_DIR_Y 0x00000100UL /* ZP, Y */ +#define AM65_ABS_Y 0x00000200UL /* ABS, Y */ +#define AM65_DIR_IND 0x00000400UL /* ZP, IND */ +#define AM65_ABS_IND 0x00000800UL /* IND */ +#define AM65_DIR_IND_LONG 0x00001000UL /* -- */ +#define AM65_DIR_IND_Y 0x00002000UL /* IND, Y */ +#define AM65_DIR_IND_LONG_Y 0x00004000UL /* -- */ +#define AM65_DIR_X_IND 0x00008000UL /* IND, X */ +#define AM65_ABS_X_IND 0x00010000UL /* -- */ +#define AM65_REL 0x00020000UL /* REL */ +#define AM65_REL_LONG 0x00040000UL /* -- */ +#define AM65_STACK_REL 0x00080000UL /* SP ? */ +#define AM65_STACK_REL_IND_Y 0x00100000UL /* ? */ #define AM65_IMM_ACCU 0x00200000UL #define AM65_IMM_INDEX 0x00400000UL -#define AM65_IMM_IMPLICIT 0x00800000UL -#define AM65_BLOCKMOVE 0x01000000UL -#define AM65_BLOCKXFER 0x02000000UL -#define AM65_ABS_IND_LONG 0x04000000UL +#define AM65_IMM_IMPLICIT 0x00800000UL /* IMM */ +#define AM65_BLOCKMOVE 0x01000000UL /* -- */ +#define AM65_BLOCKXFER 0x02000000UL /* -- */ +#define AM65_ABS_IND_LONG 0x04000000UL /* -- */ #define AM65_IMM_IMPLICIT_WORD 0x08000000UL /* PHW #$1234 (4510 only) */ /* Bitmask for all ZP operations that have correspondent ABS ops */ +/* $8524 */ #define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND) - + /*$4 $20 $100 $400 $8000 */ /* Bitmask for all ABS operations that have correspondent FAR ops */ +/* $48 */ #define AM65_SET_ABS (AM65_ABS | AM65_ABS_X) - +/* $8 $40 */ /* Bitmask for all ZP operations */ +/* $8524 */ #define AM65_ALL_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND) - + /*$4 $20 $100 $400 $8000 */ /* Bitmask for all ABS operations */ +/* $10a48 */ #define AM65_ALL_ABS (AM65_ABS | AM65_ABS_X | AM65_ABS_Y | AM65_ABS_IND | AM65_ABS_X_IND) - +/* $8 $40 $200 $800 $10000 */ /* Bitmask for all FAR operations */ +/* $90 */ #define AM65_ALL_FAR (AM65_ABS_LONG | AM65_ABS_LONG_X) + /* $10 $80 */ /* Bitmask for all immediate operations */ +/* $8e00 000 */ #define AM65_ALL_IMM (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT | AM65_IMM_IMPLICIT_WORD) - +/* $200000 $400000 $800000 $8000000 */ /* Bit numbers and count */ #define AM65I_IMM_ACCU 21 #define AM65I_IMM_INDEX 22 diff --git a/src/da65/handler.c b/src/da65/handler.c index 79b3192de..3e448635d 100644 --- a/src/da65/handler.c +++ b/src/da65/handler.c @@ -531,7 +531,22 @@ void OH_BitBranch (const OpcDesc* D) xfree (BranchLabel); } +void OH_BitBranchm740 (const OpcDesc* D) +{ + unsigned Bit = GetCodeByte (PC) >> 5; + unsigned Addr = GetCodeByte (PC+1); + signed char BranchOffs = GetCodeByte (PC+2); + /* Calculate the target address for the branch */ + unsigned BranchAddr = (((int) PC+3) + BranchOffs) & 0xFFFF; + + /* Generate a label in pass 1 */ + GenerateLabel (D->Flags, Addr); + GenerateLabel (flLabel, BranchAddr); + + /* Output the line */ + OneLine (D, "%01X,%s,%s", Bit, GetAddrArg (D->Flags, Addr), GetAddrArg (flLabel, BranchAddr)); +} void OH_ImmediateDirect (const OpcDesc* D) { diff --git a/src/da65/handler.h b/src/da65/handler.h index ee9b18bbc..7688ff1c8 100644 --- a/src/da65/handler.h +++ b/src/da65/handler.h @@ -78,6 +78,7 @@ void OH_DirectXIndirect (const OpcDesc*); void OH_AbsoluteIndirect (const OpcDesc*); void OH_BitBranch (const OpcDesc*); +void OH_BitBranchm740 (const OpcDesc*); void OH_ImmediateDirect (const OpcDesc*); void OH_ImmediateDirectX (const OpcDesc*); diff --git a/src/da65/opcm740.c b/src/da65/opcm740.c index 67a36b48c..791f7f7a8 100644 --- a/src/da65/opcm740.c +++ b/src/da65/opcm740.c @@ -55,7 +55,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $04 */ { "ora", 2, flUseLabel, OH_Direct }, /* $05 */ { "asl", 2, flUseLabel, OH_Direct }, /* $06 */ - { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $07 */ + { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $07 */ { "php", 1, flNone, OH_Implicit }, /* $08 */ { "ora", 2, flNone, OH_Immediate }, /* $09 */ { "asl", 1, flNone, OH_Accumulator }, /* $0a */ @@ -71,7 +71,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $14 */ { "ora", 2, flUseLabel, OH_DirectX }, /* $15 */ { "asl", 2, flUseLabel, OH_DirectX }, /* $16 */ - { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $17 */ + { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $17 */ { "clc", 1, flNone, OH_Implicit }, /* $18 */ { "ora", 3, flUseLabel, OH_AbsoluteY }, /* $19 */ { "dec", 1, flNone, OH_Accumulator }, /* $1a */ @@ -87,7 +87,7 @@ const OpcDesc OpcTable_M740[256] = { { "bit", 2, flUseLabel, OH_Direct }, /* $24 */ { "and", 2, flUseLabel, OH_Direct }, /* $25 */ { "rol", 2, flUseLabel, OH_Direct }, /* $26 */ - { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $27 */ + { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $27 */ { "plp", 1, flNone, OH_Implicit }, /* $28 */ { "and", 2, flNone, OH_Immediate }, /* $29 */ { "rol", 1, flNone, OH_Accumulator }, /* $2a */ @@ -103,7 +103,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $34 */ { "and", 2, flUseLabel, OH_DirectX }, /* $35 */ { "rol", 2, flUseLabel, OH_DirectX }, /* $36 */ - { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $37 */ + { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $37 */ { "sec", 1, flNone, OH_Implicit }, /* $38 */ { "and", 3, flUseLabel, OH_AbsoluteY }, /* $39 */ { "inc", 1, flNone, OH_Accumulator }, /* $3a */ @@ -119,7 +119,7 @@ const OpcDesc OpcTable_M740[256] = { { "com", 2, flUseLabel, OH_Direct }, /* $44 */ { "eor", 2, flUseLabel, OH_Direct }, /* $45 */ { "lsr", 2, flUseLabel, OH_Direct }, /* $46 */ - { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $47 */ + { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $47 */ { "pha", 1, flNone, OH_Implicit }, /* $48 */ { "eor", 2, flNone, OH_Immediate }, /* $49 */ { "lsr", 1, flNone, OH_Accumulator }, /* $4a */ @@ -135,7 +135,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $54 */ { "eor", 2, flUseLabel, OH_DirectX }, /* $55 */ { "lsr", 2, flUseLabel, OH_DirectX }, /* $56 */ - { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $57 */ + { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $57 */ { "cli", 1, flNone, OH_Implicit }, /* $58 */ { "eor", 3, flUseLabel, OH_AbsoluteY }, /* $59 */ { "", 1, flIllegal, OH_Illegal }, /* $5a */ @@ -151,7 +151,7 @@ const OpcDesc OpcTable_M740[256] = { { "tst", 2, flUseLabel, OH_Direct }, /* $64 */ { "adc", 2, flUseLabel, OH_Direct }, /* $65 */ { "ror", 2, flUseLabel, OH_Direct }, /* $66 */ - { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $67 */ + { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $67 */ { "pla", 1, flNone, OH_Implicit }, /* $68 */ { "adc", 2, flNone, OH_Immediate }, /* $69 */ { "ror", 1, flNone, OH_Accumulator }, /* $6a */ @@ -167,7 +167,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $74 */ { "adc", 2, flUseLabel, OH_DirectX }, /* $75 */ { "ror", 2, flUseLabel, OH_DirectX }, /* $76 */ - { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $77 */ + { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $77 */ { "sei", 1, flNone, OH_Implicit }, /* $78 */ { "adc", 3, flUseLabel, OH_AbsoluteY }, /* $79 */ { "", 1, flIllegal, OH_Illegal }, /* $7a */ @@ -183,7 +183,7 @@ const OpcDesc OpcTable_M740[256] = { { "sty", 2, flUseLabel, OH_Direct }, /* $84 */ { "sta", 2, flUseLabel, OH_Direct }, /* $85 */ { "stx", 2, flUseLabel, OH_Direct }, /* $86 */ - { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $87 */ + { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $87 */ { "dey", 1, flNone, OH_Implicit }, /* $88 */ { "", 1, flIllegal, OH_Illegal }, /* $89 */ { "txa", 1, flNone, OH_Implicit }, /* $8a */ @@ -199,7 +199,7 @@ const OpcDesc OpcTable_M740[256] = { { "sty", 2, flUseLabel, OH_DirectX }, /* $94 */ { "sta", 2, flUseLabel, OH_DirectX }, /* $95 */ { "stx", 2, flUseLabel, OH_DirectY }, /* $96 */ - { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $97 */ + { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $97 */ { "tya", 1, flNone, OH_Implicit }, /* $98 */ { "sta", 3, flUseLabel, OH_AbsoluteY }, /* $99 */ { "txs", 1, flNone, OH_Implicit }, /* $9a */ @@ -215,7 +215,7 @@ const OpcDesc OpcTable_M740[256] = { { "ldy", 2, flUseLabel, OH_Direct }, /* $a4 */ { "lda", 2, flUseLabel, OH_Direct }, /* $a5 */ { "ldx", 2, flUseLabel, OH_Direct }, /* $a6 */ - { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $a7 */ + { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $a7 */ { "tay", 1, flNone, OH_Implicit }, /* $a8 */ { "lda", 2, flNone, OH_Immediate }, /* $a9 */ { "tax", 1, flNone, OH_Implicit }, /* $aa */ @@ -231,7 +231,7 @@ const OpcDesc OpcTable_M740[256] = { { "ldy", 2, flUseLabel, OH_DirectX }, /* $b4 */ { "lda", 2, flUseLabel, OH_DirectX }, /* $b5 */ { "ldx", 2, flUseLabel, OH_DirectY }, /* $b6 */ - { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $b7 */ + { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $b7 */ { "clv", 1, flNone, OH_Implicit }, /* $b8 */ { "lda", 3, flUseLabel, OH_AbsoluteY }, /* $b9 */ { "tsx", 1, flNone, OH_Implicit }, /* $ba */ @@ -247,7 +247,7 @@ const OpcDesc OpcTable_M740[256] = { { "cpy", 2, flUseLabel, OH_Direct }, /* $c4 */ { "cmp", 2, flUseLabel, OH_Direct }, /* $c5 */ { "dec", 2, flUseLabel, OH_Direct }, /* $c6 */ - { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $c7 */ + { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $c7 */ { "iny", 1, flNone, OH_Implicit }, /* $c8 */ { "cmp", 2, flNone, OH_Immediate }, /* $c9 */ { "dex", 1, flNone, OH_Implicit }, /* $ca */ @@ -263,7 +263,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $d4 */ { "cmp", 2, flUseLabel, OH_DirectX }, /* $d5 */ { "dec", 2, flUseLabel, OH_DirectX }, /* $d6 */ - { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $d7 */ + { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $d7 */ { "cld", 1, flNone, OH_Implicit }, /* $d8 */ { "cmp", 3, flUseLabel, OH_AbsoluteY }, /* $d9 */ { "", 1, flIllegal, OH_Illegal }, /* $da */ @@ -279,7 +279,7 @@ const OpcDesc OpcTable_M740[256] = { { "cpx", 2, flUseLabel, OH_Direct }, /* $e4 */ { "sbc", 2, flUseLabel, OH_Direct }, /* $e5 */ { "inc", 2, flUseLabel, OH_Direct }, /* $e6 */ - { "bbs", 3, flUseLabel, OH_ZeroPageBit }, /* $e7 */ + { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $e7 */ { "inx", 1, flNone, OH_Implicit }, /* $e8 */ { "sbc", 2, flNone, OH_Immediate }, /* $e9 */ { "nop", 1, flNone, OH_Implicit }, /* $ea */ @@ -295,7 +295,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $f4 */ { "sbc", 2, flUseLabel, OH_DirectX }, /* $f5 */ { "inc", 2, flUseLabel, OH_DirectX }, /* $f6 */ - { "bbc", 3, flUseLabel, OH_ZeroPageBit }, /* $f7 */ + { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $f7 */ { "sed", 1, flNone, OH_Implicit }, /* $f8 */ { "sbc", 3, flUseLabel, OH_AbsoluteY }, /* $f9 */ { "", 1, flIllegal, OH_Illegal }, /* $fa */ From 7b12962eec45990b2e24b07f67d430d53c2325ab Mon Sep 17 00:00:00 2001 From: mrdudz Date: Mon, 16 Jun 2025 01:17:36 +0200 Subject: [PATCH 02/26] fix m740, survives disasm/asm roundtrip now, still needs some work though --- src/ca65/ea65.c | 4 +- src/ca65/instr.c | 137 +++++++++++++++++++++++++++------------------ src/ca65/instr.h | 3 + src/da65/handler.c | 33 +++++++++-- src/da65/handler.h | 2 +- src/da65/opcm740.c | 38 ++++++------- 6 files changed, 135 insertions(+), 82 deletions(-) diff --git a/src/ca65/ea65.c b/src/ca65/ea65.c index 5bd2ba82b..965d15b2d 100644 --- a/src/ca65/ea65.c +++ b/src/ca65/ea65.c @@ -214,7 +214,9 @@ void GetEA (EffAddr* A) break; default: - Error ("Syntax error"); + /* FIXME: syntax error if not zp, ind */ + A->AddrModeSet = AM65_ZP_REL; + break; } diff --git a/src/ca65/instr.c b/src/ca65/instr.c index ddbd12125..1b33bcd7d 100644 --- a/src/ca65/instr.c +++ b/src/ca65/instr.c @@ -85,10 +85,10 @@ static void PutBlockTransfer (const InsDesc* Ins); static void PutBitBranch (const InsDesc* Ins); /* Handle 65C02 branch on bit condition */ -static void PutBitBranchm740 (const InsDesc* Ins); +static void PutBitBranch_m740 (const InsDesc* Ins); /* Handle m740 branch on bit condition */ -static void PutLDMm740 (const InsDesc* Ins); +static void PutLDM_m740 (const InsDesc* Ins); /* Handle m740 LDM instruction */ static void PutREP (const InsDesc* Ins); @@ -1056,41 +1056,49 @@ static const struct { /* Instruction table for the m740 CPU */ static const struct { unsigned Count; - InsDesc Ins[97]; + InsDesc Ins[106]; } InsTabm740 = { sizeof (InsTabm740.Ins) / sizeof (InsTabm740.Ins[0]), { /* BEGIN SORTED.SH */ - { "ADC", 0x080A26C, 0x60, 0, PutAll }, - { "AND", 0x080A26C, 0x20, 0, PutAll }, - { "ASL", 0x000006e, 0x02, 1, PutAll }, - { "BBR0", 0x0000006, 0x13, 10, PutBitBranchm740 }, - { "BBR1", 0x0000006, 0x33, 10, PutBitBranchm740 }, - { "BBR2", 0x0000006, 0x53, 10, PutBitBranchm740 }, - { "BBR3", 0x0000006, 0x73, 10, PutBitBranchm740 }, - { "BBR4", 0x0000006, 0x93, 10, PutBitBranchm740 }, - { "BBR5", 0x0000006, 0xb3, 10, PutBitBranchm740 }, - { "BBR6", 0x0000006, 0xd3, 10, PutBitBranchm740 }, - { "BBR7", 0x0000006, 0xf3, 10, PutBitBranchm740 }, - { "BBS0", 0x0000006, 0x03, 10, PutBitBranchm740 }, - { "BBS1", 0x0000006, 0x23, 10, PutBitBranchm740 }, - { "BBS2", 0x0000006, 0x43, 10, PutBitBranchm740 }, - { "BBS3", 0x0000006, 0x63, 10, PutBitBranchm740 }, - { "BBS4", 0x0000006, 0x83, 10, PutBitBranchm740 }, - { "BBS5", 0x0000006, 0xa3, 10, PutBitBranchm740 }, - { "BBS6", 0x0000006, 0xc3, 10, PutBitBranchm740 }, - { "BBS7", 0x0000006, 0xe3, 10, PutBitBranchm740 }, - { "BCC", 0x0020000, 0x90, 0, PutPCRel8 }, - { "BCS", 0x0020000, 0xb0, 0, PutPCRel8 }, - { "BEQ", 0x0020000, 0xf0, 0, PutPCRel8 }, - { "BIT", 0x000000C, 0x00, 2, PutAll }, - { "BMI", 0x0020000, 0x30, 0, PutPCRel8 }, - { "BNE", 0x0020000, 0xd0, 0, PutPCRel8 }, - { "BPL", 0x0020000, 0x10, 0, PutPCRel8 }, - { "BRA", 0x0020000, 0x80, 0, PutPCRel8 }, - { "BRK", 0x0000001, 0x00, 0, PutAll }, - { "BVC", 0x0020000, 0x50, 0, PutPCRel8 }, - { "BVS", 0x0020000, 0x70, 0, PutPCRel8 }, + { "ADC", 0x0080A26C, 0x60, 0, PutAll }, + { "AND", 0x0080A26C, 0x20, 0, PutAll }, + { "ASL", 0x0000006e, 0x02, 1, PutAll }, + { "BBC0", 0x10000002, 0x13, 10, PutBitBranch_m740 }, + { "BBC1", 0x10000002, 0x33, 10, PutBitBranch_m740 }, + { "BBC2", 0x10000002, 0x53, 10, PutBitBranch_m740 }, + { "BBC3", 0x10000002, 0x73, 10, PutBitBranch_m740 }, + { "BBC4", 0x10000002, 0x93, 10, PutBitBranch_m740 }, + { "BBC5", 0x10000002, 0xb3, 10, PutBitBranch_m740 }, + { "BBC6", 0x10000002, 0xd3, 10, PutBitBranch_m740 }, + { "BBC7", 0x10000002, 0xf3, 10, PutBitBranch_m740 }, + { "BBS0", 0x10000002, 0x03, 10, PutBitBranch_m740 }, + { "BBS1", 0x10000002, 0x23, 10, PutBitBranch_m740 }, + { "BBS2", 0x10000002, 0x43, 10, PutBitBranch_m740 }, + { "BBS3", 0x10000002, 0x63, 10, PutBitBranch_m740 }, + { "BBS4", 0x10000002, 0x83, 10, PutBitBranch_m740 }, + { "BBS5", 0x10000002, 0xa3, 10, PutBitBranch_m740 }, + { "BBS6", 0x10000002, 0xc3, 10, PutBitBranch_m740 }, + { "BBS7", 0x10000002, 0xe3, 10, PutBitBranch_m740 }, + { "BCC", 0x00020000, 0x90, 0, PutPCRel8 }, + { "BCS", 0x00020000, 0xb0, 0, PutPCRel8 }, + { "BEQ", 0x00020000, 0xf0, 0, PutPCRel8 }, + { "BIT", 0x0000000C, 0x00, 2, PutAll }, + { "BMI", 0x00020000, 0x30, 0, PutPCRel8 }, + { "BNE", 0x00020000, 0xd0, 0, PutPCRel8 }, + { "BPL", 0x00020000, 0x10, 0, PutPCRel8 }, + { "BRA", 0x00020000, 0x80, 0, PutPCRel8 }, + { "BRK", 0x00000001, 0x00, 0, PutAll }, + { "BVC", 0x00020000, 0x50, 0, PutPCRel8 }, + { "BVS", 0x00020000, 0x70, 0, PutPCRel8 }, + { "CLB0", 0x0000006, 0x1b, 10, PutAll }, + { "CLB1", 0x0000006, 0x3b, 10, PutAll }, + { "CLB2", 0x0000006, 0x5b, 10, PutAll }, + { "CLB3", 0x0000006, 0x7b, 10, PutAll }, + { "CLB4", 0x0000006, 0x9b, 10, PutAll }, + { "CLB5", 0x0000006, 0xbb, 10, PutAll }, + { "CLB6", 0x0000006, 0xdb, 10, PutAll }, + { "CLB7", 0x0000006, 0xfb, 10, PutAll }, { "CLC", 0x0000001, 0x18, 0, PutAll }, { "CLD", 0x0000001, 0xd8, 0, PutAll }, { "CLI", 0x0000001, 0x58, 0, PutAll }, @@ -1111,7 +1119,7 @@ static const struct { { "JMP", 0x0000C08, 0x00, 12, PutAll }, { "JSR", 0x0080808, 0x00, 13, PutAll }, { "LDA", 0x080A26C, 0xa0, 0, PutAll }, - { "LDM", 0x0000004, 0x3c, 6, PutLDMm740 }, + { "LDM", 0x10000000, 0x3c, 0, PutLDM_m740 }, { "LDX", 0x080030C, 0xa2, 1, PutAll }, { "LDY", 0x080006C, 0xa0, 1, PutAll }, { "LSR", 0x000006F, 0x42, 1, PutAll }, @@ -1135,25 +1143,26 @@ static const struct { { "RTI", 0x0000001, 0x40, 0, PutAll }, { "RTS", 0x0000001, 0x60, 0, PutAll }, { "SBC", 0x080A26C, 0xe0, 0, PutAll }, + { "SEB0", 0x0000006, 0x0b, 10, PutAll }, + { "SEB1", 0x0000006, 0x2b, 10, PutAll }, + { "SEB2", 0x0000006, 0x4b, 10, PutAll }, + { "SEB3", 0x0000006, 0x6b, 10, PutAll }, + { "SEB4", 0x0000006, 0x8b, 10, PutAll }, + { "SEB5", 0x0000006, 0xab, 10, PutAll }, + { "SEB6", 0x0000006, 0xcb, 10, PutAll }, + { "SEB7", 0x0000006, 0xeb, 10, PutAll }, { "SEC", 0x0000001, 0x38, 0, PutAll }, { "SED", 0x0000001, 0xf8, 0, PutAll }, { "SEI", 0x0000001, 0x78, 0, PutAll }, { "SET", 0x0000001, 0x32, 0, PutAll }, { "SLW", 0x0000001, 0xC2, 0, PutAll }, - { "SMB0", 0x0000006, 0x0b, 10, PutAll }, - { "SMB1", 0x0000006, 0x2b, 10, PutAll }, - { "SMB2", 0x0000006, 0x4b, 10, PutAll }, - { "SMB3", 0x0000006, 0x6b, 10, PutAll }, - { "SMB4", 0x0000006, 0x8b, 10, PutAll }, - { "SMB5", 0x0000006, 0xab, 10, PutAll }, - { "SMB6", 0x0000006, 0xcb, 10, PutAll }, - { "SMB7", 0x0000006, 0xeb, 10, PutAll }, { "STA", 0x000A26C, 0x80, 0, PutAll }, { "STP", 0x0000001, 0x42, 0, PutAll }, { "STX", 0x000010c, 0x82, 1, PutAll }, { "STY", 0x000002c, 0x80, 1, PutAll }, { "TAX", 0x0000001, 0xaa, 0, PutAll }, { "TAY", 0x0000001, 0xa8, 0, PutAll }, + { "TST", 0x0000004, 0x64, 0, PutAll }, { "TSX", 0x0000001, 0xba, 0, PutAll }, { "TXA", 0x0000001, 0x8a, 0, PutAll }, { "TXS", 0x0000001, 0x9a, 0, PutAll }, @@ -1486,13 +1495,21 @@ static void EmitCode (EffAddr* A) } -static void PutLDMm740 (const InsDesc* Ins) +static void PutLDM_m740 (const InsDesc* Ins) { - + EffAddr A; + /* Evaluate the addressing mode */ + if (EvalEA (Ins, &A) == 0) { + /* An error occurred */ + return; + } Emit0 (Ins->BaseCode); - EmitWord (Expression ()); + EmitByte (A.Expr); + Consume (TOK_HASH, "'#' expected"); + EmitByte (Expression ()); } + static long PutImmed8 (const InsDesc* Ins) /* Parse and emit an immediate 8 bit instruction. Return the value of the ** operand if it's available and const. @@ -1612,21 +1629,29 @@ static void PutBitBranch (const InsDesc* Ins) EmitSigned (GenBranchExpr (1), 1); } -static void PutBitBranchm740 (const InsDesc* Ins) -/* Handle 65C02 branch on bit condition */ +static void PutBitBranch_m740 (const InsDesc* Ins) +/* Handle m740 branch on bit condition */ { EffAddr A; - /* HACK: hardcoded for zp addressing mode, this doesn't work all the time */ - A.AddrMode = 2; - - A.Opcode = Ins->BaseCode | EATab[Ins->ExtCode][A.AddrMode]; /* Evaluate the addressing mode used */ - /* No error, output code */ - Emit0 (A.Opcode); - EmitByte (Expression ()); - ConsumeComma (); - EmitSigned (GenBranchExpr (1), 1); + GetEA(&A); + + A.AddrMode = 2; /* HACK */ + A.Opcode = Ins->BaseCode; + + if (A.AddrModeSet == 0x00000002) { + /* Accu */ + Emit0 (A.Opcode); + ConsumeComma (); + EmitSigned (GenBranchExpr (1), 1); + } else if (A.AddrModeSet == 0x10000000) { + A.Opcode += 0x04; + /* Zeropage */ + Emit0 (A.Opcode); + EmitByte (A.Expr); + EmitSigned (GenBranchExpr (1), 1); + } } diff --git a/src/ca65/instr.h b/src/ca65/instr.h index 823aa5659..fff5a0f34 100644 --- a/src/ca65/instr.h +++ b/src/ca65/instr.h @@ -86,6 +86,9 @@ #define AM65_BLOCKXFER 0x02000000UL /* -- */ #define AM65_ABS_IND_LONG 0x04000000UL /* -- */ #define AM65_IMM_IMPLICIT_WORD 0x08000000UL /* PHW #$1234 (4510 only) */ +#define AM65_ZP_REL 0x10000000UL /* ZP, REL (m740) */ + + /* Bitmask for all ZP operations that have correspondent ABS ops */ /* $8524 */ diff --git a/src/da65/handler.c b/src/da65/handler.c index 3e448635d..674769369 100644 --- a/src/da65/handler.c +++ b/src/da65/handler.c @@ -92,6 +92,29 @@ static void OneLine (const OpcDesc* D, const char* Arg, ...) LineFeed (); } +static void OneLineNoIndent (const OpcDesc* D, const char* Arg, ...) attribute ((format(printf, 2, 3))); +static void OneLineNoIndent (const OpcDesc* D, const char* Arg, ...) +/* Output one line with the given mnemonic and argument */ +{ + char Buf [256]; + va_list ap; + + /* Mnemonic */ + Mnemonic (D->Mnemo); + + /* Argument */ + va_start (ap, Arg); + xvsprintf (Buf, sizeof (Buf), Arg, ap); + va_end (ap); + + Output ("%s", Buf); + + /* Add the code stuff as comment */ + LineComment (PC, D->Size); + + /* End the line */ + LineFeed (); +} static const char* GetAbsOverride (unsigned Flags, unsigned Addr) @@ -531,7 +554,7 @@ void OH_BitBranch (const OpcDesc* D) xfree (BranchLabel); } -void OH_BitBranchm740 (const OpcDesc* D) +void OH_BitBranch_m740 (const OpcDesc* D) { unsigned Bit = GetCodeByte (PC) >> 5; unsigned Addr = GetCodeByte (PC+1); @@ -545,7 +568,7 @@ void OH_BitBranchm740 (const OpcDesc* D) GenerateLabel (flLabel, BranchAddr); /* Output the line */ - OneLine (D, "%01X,%s,%s", Bit, GetAddrArg (D->Flags, Addr), GetAddrArg (flLabel, BranchAddr)); + OneLineNoIndent (D, "%01X %s,%s", Bit, GetAddrArg (D->Flags, Addr), GetAddrArg (flLabel, BranchAddr)); } void OH_ImmediateDirect (const OpcDesc* D) @@ -743,7 +766,7 @@ void OH_ZeroPageBit (const OpcDesc* D) GenerateLabel (D->Flags, Addr); /* Output the line */ - OneLine (D, "%01X,%s", Bit, GetAddrArg (D->Flags, Addr)); + OneLineNoIndent (D, "%01X %s", Bit, GetAddrArg (D->Flags, Addr)); } @@ -753,7 +776,7 @@ void OH_AccumulatorBit (const OpcDesc* D) unsigned Bit = GetCodeByte (PC) >> 5; /* Output the line */ - OneLine (D, "%01X,a", Bit); + OneLineNoIndent (D, "%01X a", Bit); } @@ -770,7 +793,7 @@ void OH_AccumulatorBitBranch (const OpcDesc* D) GenerateLabel (flLabel, BranchAddr); /* Output the line */ - OneLine (D, "%01X,a,%s", Bit, GetAddrArg (flLabel, BranchAddr)); + OneLineNoIndent (D, "%01X a, %s", Bit, GetAddrArg (flLabel, BranchAddr)); } diff --git a/src/da65/handler.h b/src/da65/handler.h index 7688ff1c8..fb0c40200 100644 --- a/src/da65/handler.h +++ b/src/da65/handler.h @@ -78,7 +78,7 @@ void OH_DirectXIndirect (const OpcDesc*); void OH_AbsoluteIndirect (const OpcDesc*); void OH_BitBranch (const OpcDesc*); -void OH_BitBranchm740 (const OpcDesc*); +void OH_BitBranch_m740 (const OpcDesc*); void OH_ImmediateDirect (const OpcDesc*); void OH_ImmediateDirectX (const OpcDesc*); diff --git a/src/da65/opcm740.c b/src/da65/opcm740.c index 791f7f7a8..e4bd3370f 100644 --- a/src/da65/opcm740.c +++ b/src/da65/opcm740.c @@ -55,7 +55,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $04 */ { "ora", 2, flUseLabel, OH_Direct }, /* $05 */ { "asl", 2, flUseLabel, OH_Direct }, /* $06 */ - { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $07 */ + { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $07 */ { "php", 1, flNone, OH_Implicit }, /* $08 */ { "ora", 2, flNone, OH_Immediate }, /* $09 */ { "asl", 1, flNone, OH_Accumulator }, /* $0a */ @@ -71,7 +71,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $14 */ { "ora", 2, flUseLabel, OH_DirectX }, /* $15 */ { "asl", 2, flUseLabel, OH_DirectX }, /* $16 */ - { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $17 */ + { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $17 */ { "clc", 1, flNone, OH_Implicit }, /* $18 */ { "ora", 3, flUseLabel, OH_AbsoluteY }, /* $19 */ { "dec", 1, flNone, OH_Accumulator }, /* $1a */ @@ -87,7 +87,7 @@ const OpcDesc OpcTable_M740[256] = { { "bit", 2, flUseLabel, OH_Direct }, /* $24 */ { "and", 2, flUseLabel, OH_Direct }, /* $25 */ { "rol", 2, flUseLabel, OH_Direct }, /* $26 */ - { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $27 */ + { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $27 */ { "plp", 1, flNone, OH_Implicit }, /* $28 */ { "and", 2, flNone, OH_Immediate }, /* $29 */ { "rol", 1, flNone, OH_Accumulator }, /* $2a */ @@ -103,7 +103,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $34 */ { "and", 2, flUseLabel, OH_DirectX }, /* $35 */ { "rol", 2, flUseLabel, OH_DirectX }, /* $36 */ - { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $37 */ + { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $37 */ { "sec", 1, flNone, OH_Implicit }, /* $38 */ { "and", 3, flUseLabel, OH_AbsoluteY }, /* $39 */ { "inc", 1, flNone, OH_Accumulator }, /* $3a */ @@ -119,7 +119,7 @@ const OpcDesc OpcTable_M740[256] = { { "com", 2, flUseLabel, OH_Direct }, /* $44 */ { "eor", 2, flUseLabel, OH_Direct }, /* $45 */ { "lsr", 2, flUseLabel, OH_Direct }, /* $46 */ - { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $47 */ + { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $47 */ { "pha", 1, flNone, OH_Implicit }, /* $48 */ { "eor", 2, flNone, OH_Immediate }, /* $49 */ { "lsr", 1, flNone, OH_Accumulator }, /* $4a */ @@ -135,7 +135,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $54 */ { "eor", 2, flUseLabel, OH_DirectX }, /* $55 */ { "lsr", 2, flUseLabel, OH_DirectX }, /* $56 */ - { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $57 */ + { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $57 */ { "cli", 1, flNone, OH_Implicit }, /* $58 */ { "eor", 3, flUseLabel, OH_AbsoluteY }, /* $59 */ { "", 1, flIllegal, OH_Illegal }, /* $5a */ @@ -146,12 +146,12 @@ const OpcDesc OpcTable_M740[256] = { { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $5f */ { "rts", 1, flNone, OH_Rts }, /* $60 */ { "adc", 2, flUseLabel, OH_DirectXIndirect }, /* $61 */ - { "mul", 2, flUseLabel, OH_DirectX }, /* $62 */ + { "", 1, flIllegal, OH_Illegal }, /* $62 */ { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $63 */ { "tst", 2, flUseLabel, OH_Direct }, /* $64 */ { "adc", 2, flUseLabel, OH_Direct }, /* $65 */ { "ror", 2, flUseLabel, OH_Direct }, /* $66 */ - { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $67 */ + { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $67 */ { "pla", 1, flNone, OH_Implicit }, /* $68 */ { "adc", 2, flNone, OH_Immediate }, /* $69 */ { "ror", 1, flNone, OH_Accumulator }, /* $6a */ @@ -167,7 +167,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $74 */ { "adc", 2, flUseLabel, OH_DirectX }, /* $75 */ { "ror", 2, flUseLabel, OH_DirectX }, /* $76 */ - { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $77 */ + { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $77 */ { "sei", 1, flNone, OH_Implicit }, /* $78 */ { "adc", 3, flUseLabel, OH_AbsoluteY }, /* $79 */ { "", 1, flIllegal, OH_Illegal }, /* $7a */ @@ -183,7 +183,7 @@ const OpcDesc OpcTable_M740[256] = { { "sty", 2, flUseLabel, OH_Direct }, /* $84 */ { "sta", 2, flUseLabel, OH_Direct }, /* $85 */ { "stx", 2, flUseLabel, OH_Direct }, /* $86 */ - { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $87 */ + { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $87 */ { "dey", 1, flNone, OH_Implicit }, /* $88 */ { "", 1, flIllegal, OH_Illegal }, /* $89 */ { "txa", 1, flNone, OH_Implicit }, /* $8a */ @@ -199,7 +199,7 @@ const OpcDesc OpcTable_M740[256] = { { "sty", 2, flUseLabel, OH_DirectX }, /* $94 */ { "sta", 2, flUseLabel, OH_DirectX }, /* $95 */ { "stx", 2, flUseLabel, OH_DirectY }, /* $96 */ - { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $97 */ + { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $97 */ { "tya", 1, flNone, OH_Implicit }, /* $98 */ { "sta", 3, flUseLabel, OH_AbsoluteY }, /* $99 */ { "txs", 1, flNone, OH_Implicit }, /* $9a */ @@ -215,7 +215,7 @@ const OpcDesc OpcTable_M740[256] = { { "ldy", 2, flUseLabel, OH_Direct }, /* $a4 */ { "lda", 2, flUseLabel, OH_Direct }, /* $a5 */ { "ldx", 2, flUseLabel, OH_Direct }, /* $a6 */ - { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $a7 */ + { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $a7 */ { "tay", 1, flNone, OH_Implicit }, /* $a8 */ { "lda", 2, flNone, OH_Immediate }, /* $a9 */ { "tax", 1, flNone, OH_Implicit }, /* $aa */ @@ -231,7 +231,7 @@ const OpcDesc OpcTable_M740[256] = { { "ldy", 2, flUseLabel, OH_DirectX }, /* $b4 */ { "lda", 2, flUseLabel, OH_DirectX }, /* $b5 */ { "ldx", 2, flUseLabel, OH_DirectY }, /* $b6 */ - { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $b7 */ + { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $b7 */ { "clv", 1, flNone, OH_Implicit }, /* $b8 */ { "lda", 3, flUseLabel, OH_AbsoluteY }, /* $b9 */ { "tsx", 1, flNone, OH_Implicit }, /* $ba */ @@ -242,12 +242,12 @@ const OpcDesc OpcTable_M740[256] = { { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $bf */ { "cpy", 2, flNone, OH_Immediate }, /* $c0 */ { "cmp", 2, flUseLabel, OH_DirectXIndirect }, /* $c1 */ - { "wit", 1, flNone, OH_Implicit, }, /* $c2 */ + { "slw", 1, flNone, OH_Implicit, }, /* $c2 */ { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $c3 */ { "cpy", 2, flUseLabel, OH_Direct }, /* $c4 */ { "cmp", 2, flUseLabel, OH_Direct }, /* $c5 */ { "dec", 2, flUseLabel, OH_Direct }, /* $c6 */ - { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $c7 */ + { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $c7 */ { "iny", 1, flNone, OH_Implicit }, /* $c8 */ { "cmp", 2, flNone, OH_Immediate }, /* $c9 */ { "dex", 1, flNone, OH_Implicit }, /* $ca */ @@ -263,7 +263,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $d4 */ { "cmp", 2, flUseLabel, OH_DirectX }, /* $d5 */ { "dec", 2, flUseLabel, OH_DirectX }, /* $d6 */ - { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $d7 */ + { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $d7 */ { "cld", 1, flNone, OH_Implicit }, /* $d8 */ { "cmp", 3, flUseLabel, OH_AbsoluteY }, /* $d9 */ { "", 1, flIllegal, OH_Illegal }, /* $da */ @@ -274,12 +274,12 @@ const OpcDesc OpcTable_M740[256] = { { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $df */ { "cpx", 2, flNone, OH_Immediate }, /* $e0 */ { "sbc", 2, flUseLabel, OH_DirectXIndirect }, /* $e1 */ - { "div", 2, flUseLabel, OH_DirectX }, /* $e2 */ + { "fst", 1, flNone, OH_Implicit }, /* $e2 */ { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $e3 */ { "cpx", 2, flUseLabel, OH_Direct }, /* $e4 */ { "sbc", 2, flUseLabel, OH_Direct }, /* $e5 */ { "inc", 2, flUseLabel, OH_Direct }, /* $e6 */ - { "bbs", 3, flUseLabel, OH_BitBranchm740 }, /* $e7 */ + { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $e7 */ { "inx", 1, flNone, OH_Implicit }, /* $e8 */ { "sbc", 2, flNone, OH_Immediate }, /* $e9 */ { "nop", 1, flNone, OH_Implicit }, /* $ea */ @@ -295,7 +295,7 @@ const OpcDesc OpcTable_M740[256] = { { "", 1, flIllegal, OH_Illegal }, /* $f4 */ { "sbc", 2, flUseLabel, OH_DirectX }, /* $f5 */ { "inc", 2, flUseLabel, OH_DirectX }, /* $f6 */ - { "bbc", 3, flUseLabel, OH_BitBranchm740 }, /* $f7 */ + { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $f7 */ { "sed", 1, flNone, OH_Implicit }, /* $f8 */ { "sbc", 3, flUseLabel, OH_AbsoluteY }, /* $f9 */ { "", 1, flIllegal, OH_Illegal }, /* $fa */ From ef33c4b71ddf2bae73566fce92fca1c667070c53 Mon Sep 17 00:00:00 2001 From: mrdudz Date: Mon, 16 Jun 2025 01:35:23 +0200 Subject: [PATCH 03/26] fix script to deal with more than 9 tables --- .github/checks/sorted.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/checks/sorted.sh b/.github/checks/sorted.sh index 0a4a90db7..4f53b0484 100755 --- a/.github/checks/sorted.sh +++ b/.github/checks/sorted.sh @@ -13,8 +13,8 @@ function checkarray_quoted_name START="\\/\\* BEGIN SORTED.SH \\*\\/" END="\\/\\* END SORTED.SH \\*\\/" - awk '/'"$START"'/{flag=1; count++; next} /'"$END"'/{flag=0;} flag {print count,"##",$0}' "$CHECK_FILE" | \ - sed -e 's:\(.*\) ##.*\"\(.*\)\".*:\1##\2:g' > .a.tmp + awk '/'"$START"'/{flag=1; count++; next} /'"$END"'/{flag=0;} flag {printf("%04d##%s\n", count, $0)}' "$CHECK_FILE" | \ + sed -e 's:\(.*\)##.*\"\(.*\)\".*:\1##\2:g' > .a.tmp if [[ -z $(grep '[^[:space:]]' .a.tmp) ]] ; then echo "error: "$1" table is empty" From 2184ba80c7d5b116e86f490791e61e8be5c41164 Mon Sep 17 00:00:00 2001 From: mrdudz Date: Mon, 16 Jun 2025 17:39:23 +0200 Subject: [PATCH 04/26] make part of the instruction, like in the huc6280 --- src/da65/handler.c | 48 ++++++----------- src/da65/opcm740.c | 128 ++++++++++++++++++++++----------------------- 2 files changed, 80 insertions(+), 96 deletions(-) diff --git a/src/da65/handler.c b/src/da65/handler.c index 674769369..356e84429 100644 --- a/src/da65/handler.c +++ b/src/da65/handler.c @@ -92,29 +92,6 @@ static void OneLine (const OpcDesc* D, const char* Arg, ...) LineFeed (); } -static void OneLineNoIndent (const OpcDesc* D, const char* Arg, ...) attribute ((format(printf, 2, 3))); -static void OneLineNoIndent (const OpcDesc* D, const char* Arg, ...) -/* Output one line with the given mnemonic and argument */ -{ - char Buf [256]; - va_list ap; - - /* Mnemonic */ - Mnemonic (D->Mnemo); - - /* Argument */ - va_start (ap, Arg); - xvsprintf (Buf, sizeof (Buf), Arg, ap); - va_end (ap); - - Output ("%s", Buf); - - /* Add the code stuff as comment */ - LineComment (PC, D->Size); - - /* End the line */ - LineFeed (); -} static const char* GetAbsOverride (unsigned Flags, unsigned Addr) @@ -554,9 +531,11 @@ void OH_BitBranch (const OpcDesc* D) xfree (BranchLabel); } +/* zp, rel */ +/* NOTE: currently is part of the instruction */ void OH_BitBranch_m740 (const OpcDesc* D) { - unsigned Bit = GetCodeByte (PC) >> 5; + /* unsigned Bit = GetCodeByte (PC) >> 5; */ unsigned Addr = GetCodeByte (PC+1); signed char BranchOffs = GetCodeByte (PC+2); @@ -568,7 +547,7 @@ void OH_BitBranch_m740 (const OpcDesc* D) GenerateLabel (flLabel, BranchAddr); /* Output the line */ - OneLineNoIndent (D, "%01X %s,%s", Bit, GetAddrArg (D->Flags, Addr), GetAddrArg (flLabel, BranchAddr)); + OneLine (D, "%s, %s", GetAddrArg (D->Flags, Addr), GetAddrArg (flLabel, BranchAddr)); } void OH_ImmediateDirect (const OpcDesc* D) @@ -757,33 +736,38 @@ void OH_DirectImmediate (const OpcDesc* D) +/* zp */ +/* NOTE: currently is part of the instruction */ void OH_ZeroPageBit (const OpcDesc* D) { - unsigned Bit = GetCodeByte (PC) >> 5; + /* unsigned Bit = GetCodeByte (PC) >> 5; */ unsigned Addr = GetCodeByte (PC+1); /* Generate a label in pass 1 */ GenerateLabel (D->Flags, Addr); /* Output the line */ - OneLineNoIndent (D, "%01X %s", Bit, GetAddrArg (D->Flags, Addr)); + OneLine (D, "%s", GetAddrArg (D->Flags, Addr)); } +/* A */ +/* NOTE: currently is part of the instruction */ void OH_AccumulatorBit (const OpcDesc* D) { - unsigned Bit = GetCodeByte (PC) >> 5; + /* unsigned Bit = GetCodeByte (PC) >> 5; */ /* Output the line */ - OneLineNoIndent (D, "%01X a", Bit); + OneLine (D, "a"); } - +/* A, rel */ +/* NOTE: currently is part of the instruction */ void OH_AccumulatorBitBranch (const OpcDesc* D) { - unsigned Bit = GetCodeByte (PC) >> 5; + /* unsigned Bit = GetCodeByte (PC) >> 5; */ signed char BranchOffs = GetCodeByte (PC+1); /* Calculate the target address for the branch */ @@ -793,7 +777,7 @@ void OH_AccumulatorBitBranch (const OpcDesc* D) GenerateLabel (flLabel, BranchAddr); /* Output the line */ - OneLineNoIndent (D, "%01X a, %s", Bit, GetAddrArg (flLabel, BranchAddr)); + OneLine (D, "a, %s", GetAddrArg (flLabel, BranchAddr)); } diff --git a/src/da65/opcm740.c b/src/da65/opcm740.c index e4bd3370f..676bf4dd4 100644 --- a/src/da65/opcm740.c +++ b/src/da65/opcm740.c @@ -51,257 +51,257 @@ const OpcDesc OpcTable_M740[256] = { { "brk", 1, flNone, OH_Implicit }, /* $00 */ { "ora", 2, flUseLabel, OH_DirectXIndirect }, /* $01 */ { "jsr", 2, flLabel, OH_JmpDirectIndirect }, /* $02 */ - { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $03 */ + { "bbs0", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $03 */ { "", 1, flIllegal, OH_Illegal }, /* $04 */ { "ora", 2, flUseLabel, OH_Direct }, /* $05 */ { "asl", 2, flUseLabel, OH_Direct }, /* $06 */ - { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $07 */ + { "bbs0", 3, flUseLabel, OH_BitBranch_m740 }, /* $07 */ { "php", 1, flNone, OH_Implicit }, /* $08 */ { "ora", 2, flNone, OH_Immediate }, /* $09 */ { "asl", 1, flNone, OH_Accumulator }, /* $0a */ - { "seb", 1, flNone, OH_AccumulatorBit }, /* $0b */ + { "seb0", 1, flNone, OH_AccumulatorBit }, /* $0b */ { "", 1, flIllegal, OH_Illegal, }, /* $0c */ { "ora", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0d */ { "asl", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $0e */ - { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $0f */ + { "seb0", 2, flUseLabel, OH_ZeroPageBit }, /* $0f */ { "bpl", 2, flLabel, OH_Relative }, /* $10 */ { "ora", 2, flUseLabel, OH_DirectIndirectY }, /* $11 */ { "clt", 1, flNone, OH_Implicit }, /* $12 */ - { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $13 */ + { "bbc0", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $13 */ { "", 1, flIllegal, OH_Illegal }, /* $14 */ { "ora", 2, flUseLabel, OH_DirectX }, /* $15 */ { "asl", 2, flUseLabel, OH_DirectX }, /* $16 */ - { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $17 */ + { "bbc0", 3, flUseLabel, OH_BitBranch_m740 }, /* $17 */ { "clc", 1, flNone, OH_Implicit }, /* $18 */ { "ora", 3, flUseLabel, OH_AbsoluteY }, /* $19 */ { "dec", 1, flNone, OH_Accumulator }, /* $1a */ - { "clb", 1, flNone, OH_AccumulatorBit }, /* $1b */ + { "clb0", 1, flNone, OH_AccumulatorBit }, /* $1b */ { "", 1, flIllegal, OH_Illegal }, /* $1c */ { "ora", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1d */ { "asl", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1e */ - { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $1f */ + { "clb0", 2, flUseLabel, OH_ZeroPageBit }, /* $1f */ { "jsr", 3, flLabel, OH_Absolute }, /* $20 */ { "and", 2, flUseLabel, OH_DirectXIndirect }, /* $21 */ { "jsr", 2, flLabel, OH_SpecialPage }, /* $22 */ - { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $23 */ + { "bbs1", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $23 */ { "bit", 2, flUseLabel, OH_Direct }, /* $24 */ { "and", 2, flUseLabel, OH_Direct }, /* $25 */ { "rol", 2, flUseLabel, OH_Direct }, /* $26 */ - { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $27 */ + { "bbs1", 3, flUseLabel, OH_BitBranch_m740 }, /* $27 */ { "plp", 1, flNone, OH_Implicit }, /* $28 */ { "and", 2, flNone, OH_Immediate }, /* $29 */ { "rol", 1, flNone, OH_Accumulator }, /* $2a */ - { "seb", 1, flNone, OH_AccumulatorBit }, /* $2b */ + { "seb1", 1, flNone, OH_AccumulatorBit }, /* $2b */ { "bit", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2c */ { "and", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2d */ { "rol", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $2e */ - { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $2f */ + { "seb1", 2, flUseLabel, OH_ZeroPageBit }, /* $2f */ { "bmi", 2, flLabel, OH_Relative }, /* $30 */ { "and", 2, flUseLabel, OH_DirectIndirectY }, /* $31 */ { "set", 1, flNone, OH_Implicit }, /* $32 */ - { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $33 */ + { "bbc1", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $33 */ { "", 1, flIllegal, OH_Illegal }, /* $34 */ { "and", 2, flUseLabel, OH_DirectX }, /* $35 */ { "rol", 2, flUseLabel, OH_DirectX }, /* $36 */ - { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $37 */ + { "bbc1", 3, flUseLabel, OH_BitBranch_m740 }, /* $37 */ { "sec", 1, flNone, OH_Implicit }, /* $38 */ { "and", 3, flUseLabel, OH_AbsoluteY }, /* $39 */ { "inc", 1, flNone, OH_Accumulator }, /* $3a */ - { "clb", 1, flNone, OH_AccumulatorBit }, /* $3b */ + { "clb1", 1, flNone, OH_AccumulatorBit }, /* $3b */ { "ldm", 3, flLabel, OH_DirectImmediate }, /* $3c */ { "and", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3d */ { "rol", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3e */ - { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $3f */ + { "clb1", 2, flUseLabel, OH_ZeroPageBit }, /* $3f */ { "rti", 1, flNone, OH_Rts }, /* $40 */ { "eor", 2, flUseLabel, OH_DirectXIndirect }, /* $41 */ { "stp", 1, flNone, OH_Implicit }, /* $42 */ - { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $43 */ + { "bbs2", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $43 */ { "com", 2, flUseLabel, OH_Direct }, /* $44 */ { "eor", 2, flUseLabel, OH_Direct }, /* $45 */ { "lsr", 2, flUseLabel, OH_Direct }, /* $46 */ - { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $47 */ + { "bbs2", 3, flUseLabel, OH_BitBranch_m740 }, /* $47 */ { "pha", 1, flNone, OH_Implicit }, /* $48 */ { "eor", 2, flNone, OH_Immediate }, /* $49 */ { "lsr", 1, flNone, OH_Accumulator }, /* $4a */ - { "seb", 1, flNone, OH_AccumulatorBit }, /* $4b */ + { "seb2", 1, flNone, OH_AccumulatorBit }, /* $4b */ { "jmp", 3, flLabel, OH_JmpAbsolute }, /* $4c */ { "eor", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $4d */ { "lsr", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $4e */ - { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $4f */ + { "seb2", 2, flUseLabel, OH_ZeroPageBit }, /* $4f */ { "bvc", 2, flLabel, OH_Relative }, /* $50 */ { "eor", 2, flUseLabel, OH_DirectIndirectY }, /* $51 */ { "", 1, flIllegal, OH_Illegal }, /* $52 */ - { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $53 */ + { "bbc2", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $53 */ { "", 1, flIllegal, OH_Illegal }, /* $54 */ { "eor", 2, flUseLabel, OH_DirectX }, /* $55 */ { "lsr", 2, flUseLabel, OH_DirectX }, /* $56 */ - { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $57 */ + { "bbc2", 3, flUseLabel, OH_BitBranch_m740 }, /* $57 */ { "cli", 1, flNone, OH_Implicit }, /* $58 */ { "eor", 3, flUseLabel, OH_AbsoluteY }, /* $59 */ { "", 1, flIllegal, OH_Illegal }, /* $5a */ - { "clb", 1, flNone, OH_AccumulatorBit }, /* $5b */ + { "clb2", 1, flNone, OH_AccumulatorBit }, /* $5b */ { "", 1, flIllegal, OH_Illegal }, /* $5c */ { "eor", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $5d */ { "lsr", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $5e */ - { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $5f */ + { "clb2", 2, flUseLabel, OH_ZeroPageBit }, /* $5f */ { "rts", 1, flNone, OH_Rts }, /* $60 */ { "adc", 2, flUseLabel, OH_DirectXIndirect }, /* $61 */ { "", 1, flIllegal, OH_Illegal }, /* $62 */ - { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $63 */ + { "bbs3", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $63 */ { "tst", 2, flUseLabel, OH_Direct }, /* $64 */ { "adc", 2, flUseLabel, OH_Direct }, /* $65 */ { "ror", 2, flUseLabel, OH_Direct }, /* $66 */ - { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $67 */ + { "bbs3", 3, flUseLabel, OH_BitBranch_m740 }, /* $67 */ { "pla", 1, flNone, OH_Implicit }, /* $68 */ { "adc", 2, flNone, OH_Immediate }, /* $69 */ { "ror", 1, flNone, OH_Accumulator }, /* $6a */ - { "seb", 1, flNone, OH_AccumulatorBit }, /* $6b */ + { "seb3", 1, flNone, OH_AccumulatorBit }, /* $6b */ { "jmp", 3, flLabel, OH_JmpAbsoluteIndirect }, /* $6c */ { "adc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $6d */ { "ror", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $6e */ - { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $6f */ + { "seb3", 2, flUseLabel, OH_ZeroPageBit }, /* $6f */ { "bvs", 2, flLabel, OH_Relative }, /* $70 */ { "adc", 2, flUseLabel, OH_DirectIndirectY }, /* $71 */ { "", 1, flIllegal, OH_Illegal }, /* $72 */ - { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $73 */ + { "bbc3", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $73 */ { "", 1, flIllegal, OH_Illegal }, /* $74 */ { "adc", 2, flUseLabel, OH_DirectX }, /* $75 */ { "ror", 2, flUseLabel, OH_DirectX }, /* $76 */ - { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $77 */ + { "bbc3", 3, flUseLabel, OH_BitBranch_m740 }, /* $77 */ { "sei", 1, flNone, OH_Implicit }, /* $78 */ { "adc", 3, flUseLabel, OH_AbsoluteY }, /* $79 */ { "", 1, flIllegal, OH_Illegal }, /* $7a */ - { "clb", 1, flNone, OH_AccumulatorBit }, /* $7b */ + { "clb3", 1, flNone, OH_AccumulatorBit }, /* $7b */ { "", 1, flIllegal, OH_Illegal }, /* $7c */ { "adc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $7d */ { "ror", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $7e */ - { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $7f */ + { "clb3", 2, flUseLabel, OH_ZeroPageBit }, /* $7f */ { "bra", 2, flLabel, OH_Relative }, /* $80 */ { "sta", 2, flUseLabel, OH_DirectXIndirect }, /* $81 */ { "rrf", 2, flLabel, OH_Direct }, /* $82 */ - { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $83 */ + { "bbs4", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $83 */ { "sty", 2, flUseLabel, OH_Direct }, /* $84 */ { "sta", 2, flUseLabel, OH_Direct }, /* $85 */ { "stx", 2, flUseLabel, OH_Direct }, /* $86 */ - { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $87 */ + { "bbs4", 3, flUseLabel, OH_BitBranch_m740 }, /* $87 */ { "dey", 1, flNone, OH_Implicit }, /* $88 */ { "", 1, flIllegal, OH_Illegal }, /* $89 */ { "txa", 1, flNone, OH_Implicit }, /* $8a */ - { "seb", 1, flNone, OH_AccumulatorBit }, /* $8b */ + { "seb4", 1, flNone, OH_AccumulatorBit }, /* $8b */ { "sty", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8c */ { "sta", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8d */ { "stx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $8e */ - { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $8f */ + { "seb4", 2, flUseLabel, OH_ZeroPageBit }, /* $8f */ { "bcc", 2, flLabel, OH_Relative }, /* $90 */ { "sta", 2, flUseLabel, OH_DirectIndirectY }, /* $91 */ { "", 1, flIllegal, OH_Illegal }, /* $92 */ - { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $93 */ + { "bbc4", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $93 */ { "sty", 2, flUseLabel, OH_DirectX }, /* $94 */ { "sta", 2, flUseLabel, OH_DirectX }, /* $95 */ { "stx", 2, flUseLabel, OH_DirectY }, /* $96 */ - { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $97 */ + { "bbc4", 3, flUseLabel, OH_BitBranch_m740 }, /* $97 */ { "tya", 1, flNone, OH_Implicit }, /* $98 */ { "sta", 3, flUseLabel, OH_AbsoluteY }, /* $99 */ { "txs", 1, flNone, OH_Implicit }, /* $9a */ - { "clb", 1, flNone, OH_AccumulatorBit }, /* $9b */ + { "clb4", 1, flNone, OH_AccumulatorBit }, /* $9b */ { "", 1, flIllegal, OH_Illegal }, /* $9c */ { "sta", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $9d */ { "", 1, flIllegal, OH_Illegal }, /* $9e */ - { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $9f */ + { "clb4", 2, flUseLabel, OH_ZeroPageBit }, /* $9f */ { "ldy", 2, flNone, OH_Immediate }, /* $a0 */ { "lda", 2, flUseLabel, OH_DirectXIndirect }, /* $a1 */ { "ldx", 2, flNone, OH_Immediate }, /* $a2 */ - { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $a3 */ + { "bbs5", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $a3 */ { "ldy", 2, flUseLabel, OH_Direct }, /* $a4 */ { "lda", 2, flUseLabel, OH_Direct }, /* $a5 */ { "ldx", 2, flUseLabel, OH_Direct }, /* $a6 */ - { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $a7 */ + { "bbs5", 3, flUseLabel, OH_BitBranch_m740 }, /* $a7 */ { "tay", 1, flNone, OH_Implicit }, /* $a8 */ { "lda", 2, flNone, OH_Immediate }, /* $a9 */ { "tax", 1, flNone, OH_Implicit }, /* $aa */ - { "seb", 1, flNone, OH_AccumulatorBit }, /* $ab */ + { "seb5", 1, flNone, OH_AccumulatorBit }, /* $ab */ { "ldy", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ac */ { "lda", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ad */ { "ldx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ae */ - { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $af */ + { "seb5", 2, flUseLabel, OH_ZeroPageBit }, /* $af */ { "bcs", 2, flLabel, OH_Relative }, /* $b0 */ { "lda", 2, flUseLabel, OH_DirectIndirectY }, /* $b1 */ { "jmp", 2, flLabel, OH_JmpDirectIndirect }, /* $b2 */ - { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $b3 */ + { "bbc5", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $b3 */ { "ldy", 2, flUseLabel, OH_DirectX }, /* $b4 */ { "lda", 2, flUseLabel, OH_DirectX }, /* $b5 */ { "ldx", 2, flUseLabel, OH_DirectY }, /* $b6 */ - { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $b7 */ + { "bbc5", 3, flUseLabel, OH_BitBranch_m740 }, /* $b7 */ { "clv", 1, flNone, OH_Implicit }, /* $b8 */ { "lda", 3, flUseLabel, OH_AbsoluteY }, /* $b9 */ { "tsx", 1, flNone, OH_Implicit }, /* $ba */ - { "clb", 1, flNone, OH_AccumulatorBit }, /* $bb */ + { "clb5", 1, flNone, OH_AccumulatorBit }, /* $bb */ { "ldy", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $bc */ { "lda", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $bd */ { "ldx", 3, flUseLabel|flAbsOverride, OH_AbsoluteY }, /* $be */ - { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $bf */ + { "clb5", 2, flUseLabel, OH_ZeroPageBit }, /* $bf */ { "cpy", 2, flNone, OH_Immediate }, /* $c0 */ { "cmp", 2, flUseLabel, OH_DirectXIndirect }, /* $c1 */ { "slw", 1, flNone, OH_Implicit, }, /* $c2 */ - { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $c3 */ + { "bbs6", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $c3 */ { "cpy", 2, flUseLabel, OH_Direct }, /* $c4 */ { "cmp", 2, flUseLabel, OH_Direct }, /* $c5 */ { "dec", 2, flUseLabel, OH_Direct }, /* $c6 */ - { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $c7 */ + { "bbs6", 3, flUseLabel, OH_BitBranch_m740 }, /* $c7 */ { "iny", 1, flNone, OH_Implicit }, /* $c8 */ { "cmp", 2, flNone, OH_Immediate }, /* $c9 */ { "dex", 1, flNone, OH_Implicit }, /* $ca */ - { "seb", 1, flNone, OH_AccumulatorBit }, /* $cb */ + { "seb6", 1, flNone, OH_AccumulatorBit }, /* $cb */ { "cpy", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cc */ { "cmp", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $cd */ { "dec", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ce */ - { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $cf */ + { "seb6", 2, flUseLabel, OH_ZeroPageBit }, /* $cf */ { "bne", 2, flLabel, OH_Relative }, /* $d0 */ { "cmp", 2, flUseLabel, OH_DirectIndirectY }, /* $d1 */ { "", 1, flIllegal, OH_Illegal }, /* $d2 */ - { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $d3 */ + { "bbc6", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $d3 */ { "", 1, flIllegal, OH_Illegal }, /* $d4 */ { "cmp", 2, flUseLabel, OH_DirectX }, /* $d5 */ { "dec", 2, flUseLabel, OH_DirectX }, /* $d6 */ - { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $d7 */ + { "bbc6", 3, flUseLabel, OH_BitBranch_m740 }, /* $d7 */ { "cld", 1, flNone, OH_Implicit }, /* $d8 */ { "cmp", 3, flUseLabel, OH_AbsoluteY }, /* $d9 */ { "", 1, flIllegal, OH_Illegal }, /* $da */ - { "clb", 1, flNone, OH_AccumulatorBit }, /* $db */ + { "clb6", 1, flNone, OH_AccumulatorBit }, /* $db */ { "", 1, flIllegal, OH_Illegal }, /* $dc */ { "cmp", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $dd */ { "dec", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $de */ - { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $df */ + { "clb6", 2, flUseLabel, OH_ZeroPageBit }, /* $df */ { "cpx", 2, flNone, OH_Immediate }, /* $e0 */ { "sbc", 2, flUseLabel, OH_DirectXIndirect }, /* $e1 */ { "fst", 1, flNone, OH_Implicit }, /* $e2 */ - { "bbs", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $e3 */ + { "bbs7", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $e3 */ { "cpx", 2, flUseLabel, OH_Direct }, /* $e4 */ { "sbc", 2, flUseLabel, OH_Direct }, /* $e5 */ { "inc", 2, flUseLabel, OH_Direct }, /* $e6 */ - { "bbs", 3, flUseLabel, OH_BitBranch_m740 }, /* $e7 */ + { "bbs7", 3, flUseLabel, OH_BitBranch_m740 }, /* $e7 */ { "inx", 1, flNone, OH_Implicit }, /* $e8 */ { "sbc", 2, flNone, OH_Immediate }, /* $e9 */ { "nop", 1, flNone, OH_Implicit }, /* $ea */ - { "seb", 1, flNone, OH_AccumulatorBit }, /* $eb */ + { "seb7", 1, flNone, OH_AccumulatorBit }, /* $eb */ { "cpx", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ec */ { "sbc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ed */ { "inc", 3, flUseLabel|flAbsOverride, OH_Absolute }, /* $ee */ - { "seb", 2, flUseLabel, OH_ZeroPageBit }, /* $ef */ + { "seb7", 2, flUseLabel, OH_ZeroPageBit }, /* $ef */ { "beq", 2, flLabel, OH_Relative }, /* $f0 */ { "sbc", 2, flUseLabel, OH_DirectIndirectY }, /* $f1 */ { "", 1, flIllegal, OH_Illegal }, /* $f2 */ - { "bbc", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $f3 */ + { "bbc7", 2, flUseLabel, OH_AccumulatorBitBranch }, /* $f3 */ { "", 1, flIllegal, OH_Illegal }, /* $f4 */ { "sbc", 2, flUseLabel, OH_DirectX }, /* $f5 */ { "inc", 2, flUseLabel, OH_DirectX }, /* $f6 */ - { "bbc", 3, flUseLabel, OH_BitBranch_m740 }, /* $f7 */ + { "bbc7", 3, flUseLabel, OH_BitBranch_m740 }, /* $f7 */ { "sed", 1, flNone, OH_Implicit }, /* $f8 */ { "sbc", 3, flUseLabel, OH_AbsoluteY }, /* $f9 */ { "", 1, flIllegal, OH_Illegal }, /* $fa */ - { "clb", 1, flNone, OH_AccumulatorBit }, /* $fb */ + { "clb7", 1, flNone, OH_AccumulatorBit }, /* $fb */ { "", 1, flIllegal, OH_Illegal }, /* $fc */ { "sbc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $fd */ { "inc", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $fe */ - { "clb", 2, flUseLabel, OH_ZeroPageBit }, /* $ff */ + { "clb7", 2, flUseLabel, OH_ZeroPageBit }, /* $ff */ }; From 20e7c54fa36f2b4a1746b625662b71aa729d4f4c Mon Sep 17 00:00:00 2001 From: mrdudz Date: Mon, 16 Jun 2025 20:32:54 +0200 Subject: [PATCH 05/26] more m740 fixes, makes the regression test work --- src/ca65/ea65.c | 9 +- src/ca65/instr.c | 229 ++++++--- src/ca65/instr.h | 55 +- src/da65/handler.c | 12 +- src/da65/opcm740.c | 7 +- test/asm/opcodes/m740-opcodes.ref | Bin 0 -> 768 bytes test/asm/opcodes/m740-opcodes.s | 823 ++++++++++++++++++++---------- 7 files changed, 759 insertions(+), 376 deletions(-) create mode 100644 test/asm/opcodes/m740-opcodes.ref diff --git a/src/ca65/ea65.c b/src/ca65/ea65.c index 965d15b2d..da11b268a 100644 --- a/src/ca65/ea65.c +++ b/src/ca65/ea65.c @@ -186,10 +186,11 @@ void GetEA (EffAddr* A) /* Remaining stuff: ** - ** adr - ** adr,x - ** adr,y - ** adr,s + ** addr + ** addr, x + ** addr, y + ** addr, s + ** addr, relative addr */ A->Expr = Expression (); diff --git a/src/ca65/instr.c b/src/ca65/instr.c index 1b33bcd7d..9fffd312f 100644 --- a/src/ca65/instr.c +++ b/src/ca65/instr.c @@ -138,6 +138,11 @@ static void PutJSR816 (const InsDesc* Ins); ** Allowing the long_jsr_jmp_rts feature to permit a long JSR. */ +static void PutJSR_m740 (const InsDesc* Ins); +/* Handle the JSR instruction for the m740 +** Allowing the special page feature. +*/ + static void PutRTS (const InsDesc* Ins attribute ((unused))); /* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if ** the enclosing scope is FAR, but only if the long_jsr_jmp_rts feature applies. @@ -1053,6 +1058,9 @@ static const struct { } }; +/* CAUTION: in the pdf $1a is dec a, and $3a is inc a - if that is really the case, + * the table below (and the handler) should be fixed and this notice removed */ + /* Instruction table for the m740 CPU */ static const struct { unsigned Count; @@ -1091,82 +1099,82 @@ static const struct { { "BRK", 0x00000001, 0x00, 0, PutAll }, { "BVC", 0x00020000, 0x50, 0, PutPCRel8 }, { "BVS", 0x00020000, 0x70, 0, PutPCRel8 }, - { "CLB0", 0x0000006, 0x1b, 10, PutAll }, - { "CLB1", 0x0000006, 0x3b, 10, PutAll }, - { "CLB2", 0x0000006, 0x5b, 10, PutAll }, - { "CLB3", 0x0000006, 0x7b, 10, PutAll }, - { "CLB4", 0x0000006, 0x9b, 10, PutAll }, - { "CLB5", 0x0000006, 0xbb, 10, PutAll }, - { "CLB6", 0x0000006, 0xdb, 10, PutAll }, - { "CLB7", 0x0000006, 0xfb, 10, PutAll }, - { "CLC", 0x0000001, 0x18, 0, PutAll }, - { "CLD", 0x0000001, 0xd8, 0, PutAll }, - { "CLI", 0x0000001, 0x58, 0, PutAll }, - { "CLT", 0x0000001, 0x12, 0, PutAll }, - { "CLV", 0x0000001, 0xb8, 0, PutAll }, - { "CMP", 0x080A26C, 0xc0, 0, PutAll }, - { "COM", 0x0000004, 0x44, 1, PutAll }, - { "CPX", 0x080000C, 0xe0, 1, PutAll }, - { "CPY", 0x080000C, 0xc0, 1, PutAll }, - { "DEC", 0x000006F, 0x00, 3, PutAll }, - { "DEX", 0x0000001, 0xca, 0, PutAll }, - { "DEY", 0x0000001, 0x88, 0, PutAll }, - { "EOR", 0x080A26C, 0x40, 0, PutAll }, - { "FST", 0x0000001, 0xe2, 0, PutAll }, - { "INC", 0x000006f, 0x00, 4, PutAll }, - { "INX", 0x0000001, 0xe8, 0, PutAll }, - { "INY", 0x0000001, 0xc8, 0, PutAll }, - { "JMP", 0x0000C08, 0x00, 12, PutAll }, - { "JSR", 0x0080808, 0x00, 13, PutAll }, - { "LDA", 0x080A26C, 0xa0, 0, PutAll }, + { "CLB0", 0x00000006, 0x1b, 10, PutAll }, + { "CLB1", 0x00000006, 0x3b, 10, PutAll }, + { "CLB2", 0x00000006, 0x5b, 10, PutAll }, + { "CLB3", 0x00000006, 0x7b, 10, PutAll }, + { "CLB4", 0x00000006, 0x9b, 10, PutAll }, + { "CLB5", 0x00000006, 0xbb, 10, PutAll }, + { "CLB6", 0x00000006, 0xdb, 10, PutAll }, + { "CLB7", 0x00000006, 0xfb, 10, PutAll }, + { "CLC", 0x00000001, 0x18, 0, PutAll }, + { "CLD", 0x00000001, 0xd8, 0, PutAll }, + { "CLI", 0x00000001, 0x58, 0, PutAll }, + { "CLT", 0x00000001, 0x12, 0, PutAll }, + { "CLV", 0x00000001, 0xb8, 0, PutAll }, + { "CMP", 0x0080A26C, 0xc0, 0, PutAll }, + { "COM", 0x00000004, 0x44, 1, PutAll }, + { "CPX", 0x0080000C, 0xe0, 1, PutAll }, + { "CPY", 0x0080000C, 0xc0, 1, PutAll }, + { "DEC", 0x0000006F, 0x00, 3, PutAll }, + { "DEX", 0x00000001, 0xca, 0, PutAll }, + { "DEY", 0x00000001, 0x88, 0, PutAll }, + { "EOR", 0x0080A26C, 0x40, 0, PutAll }, + { "FST", 0x00000001, 0xe2, 0, PutAll }, + { "INC", 0x0000006f, 0x00, 4, PutAll }, + { "INX", 0x00000001, 0xe8, 0, PutAll }, + { "INY", 0x00000001, 0xc8, 0, PutAll }, + { "JMP", 0x00000C08, 0x00, 12, PutAll }, + { "JSR", 0x20000408, 0x00, 13, PutJSR_m740 }, + { "LDA", 0x0080A26C, 0xa0, 0, PutAll }, { "LDM", 0x10000000, 0x3c, 0, PutLDM_m740 }, - { "LDX", 0x080030C, 0xa2, 1, PutAll }, - { "LDY", 0x080006C, 0xa0, 1, PutAll }, - { "LSR", 0x000006F, 0x42, 1, PutAll }, - { "NOP", 0x0000001, 0xea, 0, PutAll }, - { "ORA", 0x080A26C, 0x00, 0, PutAll }, - { "PHA", 0x0000001, 0x48, 0, PutAll }, - { "PHP", 0x0000001, 0x08, 0, PutAll }, - { "PLA", 0x0000001, 0x68, 0, PutAll }, - { "PLP", 0x0000001, 0x28, 0, PutAll }, - { "RMB0", 0x0000006, 0x1b, 10, PutAll }, - { "RMB1", 0x0000006, 0x3b, 10, PutAll }, - { "RMB2", 0x0000006, 0x5b, 10, PutAll }, - { "RMB3", 0x0000006, 0x7b, 10, PutAll }, - { "RMB4", 0x0000006, 0x9b, 10, PutAll }, - { "RMB5", 0x0000006, 0xbb, 10, PutAll }, - { "RMB6", 0x0000006, 0xdb, 10, PutAll }, - { "RMB7", 0x0000006, 0xfb, 10, PutAll }, - { "ROL", 0x000006F, 0x22, 1, PutAll }, - { "ROR", 0x000006F, 0x62, 1, PutAll }, - { "RRF", 0x0000004, 0x82, 6, PutAll }, - { "RTI", 0x0000001, 0x40, 0, PutAll }, - { "RTS", 0x0000001, 0x60, 0, PutAll }, - { "SBC", 0x080A26C, 0xe0, 0, PutAll }, - { "SEB0", 0x0000006, 0x0b, 10, PutAll }, - { "SEB1", 0x0000006, 0x2b, 10, PutAll }, - { "SEB2", 0x0000006, 0x4b, 10, PutAll }, - { "SEB3", 0x0000006, 0x6b, 10, PutAll }, - { "SEB4", 0x0000006, 0x8b, 10, PutAll }, - { "SEB5", 0x0000006, 0xab, 10, PutAll }, - { "SEB6", 0x0000006, 0xcb, 10, PutAll }, - { "SEB7", 0x0000006, 0xeb, 10, PutAll }, - { "SEC", 0x0000001, 0x38, 0, PutAll }, - { "SED", 0x0000001, 0xf8, 0, PutAll }, - { "SEI", 0x0000001, 0x78, 0, PutAll }, - { "SET", 0x0000001, 0x32, 0, PutAll }, - { "SLW", 0x0000001, 0xC2, 0, PutAll }, - { "STA", 0x000A26C, 0x80, 0, PutAll }, - { "STP", 0x0000001, 0x42, 0, PutAll }, - { "STX", 0x000010c, 0x82, 1, PutAll }, - { "STY", 0x000002c, 0x80, 1, PutAll }, - { "TAX", 0x0000001, 0xaa, 0, PutAll }, - { "TAY", 0x0000001, 0xa8, 0, PutAll }, - { "TST", 0x0000004, 0x64, 0, PutAll }, - { "TSX", 0x0000001, 0xba, 0, PutAll }, - { "TXA", 0x0000001, 0x8a, 0, PutAll }, - { "TXS", 0x0000001, 0x9a, 0, PutAll }, - { "TYA", 0x0000001, 0x98, 0, PutAll } + { "LDX", 0x0080030C, 0xa2, 1, PutAll }, + { "LDY", 0x0080006C, 0xa0, 1, PutAll }, + { "LSR", 0x0000006F, 0x42, 1, PutAll }, + { "NOP", 0x00000001, 0xea, 0, PutAll }, + { "ORA", 0x0080A26C, 0x00, 0, PutAll }, + { "PHA", 0x00000001, 0x48, 0, PutAll }, + { "PHP", 0x00000001, 0x08, 0, PutAll }, + { "PLA", 0x00000001, 0x68, 0, PutAll }, + { "PLP", 0x00000001, 0x28, 0, PutAll }, + { "RMB0", 0x00000006, 0x1b, 10, PutAll }, + { "RMB1", 0x00000006, 0x3b, 10, PutAll }, + { "RMB2", 0x00000006, 0x5b, 10, PutAll }, + { "RMB3", 0x00000006, 0x7b, 10, PutAll }, + { "RMB4", 0x00000006, 0x9b, 10, PutAll }, + { "RMB5", 0x00000006, 0xbb, 10, PutAll }, + { "RMB6", 0x00000006, 0xdb, 10, PutAll }, + { "RMB7", 0x00000006, 0xfb, 10, PutAll }, + { "ROL", 0x0000006F, 0x22, 1, PutAll }, + { "ROR", 0x0000006F, 0x62, 1, PutAll }, + { "RRF", 0x00000004, 0x82, 6, PutAll }, + { "RTI", 0x00000001, 0x40, 0, PutAll }, + { "RTS", 0x00000001, 0x60, 0, PutAll }, + { "SBC", 0x0080A26C, 0xe0, 0, PutAll }, + { "SEB0", 0x00000006, 0x0b, 10, PutAll }, + { "SEB1", 0x00000006, 0x2b, 10, PutAll }, + { "SEB2", 0x00000006, 0x4b, 10, PutAll }, + { "SEB3", 0x00000006, 0x6b, 10, PutAll }, + { "SEB4", 0x00000006, 0x8b, 10, PutAll }, + { "SEB5", 0x00000006, 0xab, 10, PutAll }, + { "SEB6", 0x00000006, 0xcb, 10, PutAll }, + { "SEB7", 0x00000006, 0xeb, 10, PutAll }, + { "SEC", 0x00000001, 0x38, 0, PutAll }, + { "SED", 0x00000001, 0xf8, 0, PutAll }, + { "SEI", 0x00000001, 0x78, 0, PutAll }, + { "SET", 0x00000001, 0x32, 0, PutAll }, + { "SLW", 0x00000001, 0xC2, 0, PutAll }, + { "STA", 0x0000A26C, 0x80, 0, PutAll }, + { "STP", 0x00000001, 0x42, 0, PutAll }, + { "STX", 0x0000010c, 0x82, 1, PutAll }, + { "STY", 0x0000002c, 0x80, 1, PutAll }, + { "TAX", 0x00000001, 0xaa, 0, PutAll }, + { "TAY", 0x00000001, 0xa8, 0, PutAll }, + { "TST", 0x00000004, 0x64, 1, PutAll }, + { "TSX", 0x00000001, 0xba, 0, PutAll }, + { "TXA", 0x00000001, 0x8a, 0, PutAll }, + { "TXS", 0x00000001, 0x9a, 0, PutAll }, + { "TYA", 0x00000001, 0x98, 0, PutAll } /* END SORTED.SH */ } }; @@ -1197,43 +1205,43 @@ static unsigned char EATab[14][AM65I_COUNT] = { 0x00, 0x00, 0x00, 0x03, 0x13, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00 }, - { /* Table 1 */ + { /* Table 1 (rol, ror, stx, sty) */ 0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00, 0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 }, - { /* Table 2 */ + { /* Table 2 (bit) */ 0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { /* Table 3 */ + { /* Table 3 (dec, dea) */ 0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { /* Table 4 */ + { /* Table 4 (inc) */ 0x1A, 0x1A, 0xE6, 0xEE, 0x00, 0xF6, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { /* Table 5 */ + { /* Table 5 (stz) */ 0x00, 0x00, 0x60, 0x98, 0x00, 0x70, 0x9E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { /* Table 6 */ + { /* Table 6 (jmp) */ 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x00 }, - { /* Table 7 (Subroutine opcodes) */ + { /* Table 7 (Subroutine opcodes) (jsr) */ 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1245,7 +1253,7 @@ static unsigned char EATab[14][AM65I_COUNT] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, - { /* Table 9 */ + { /* Table 9 (dew, inw) */ 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1644,7 +1652,7 @@ static void PutBitBranch_m740 (const InsDesc* Ins) /* Accu */ Emit0 (A.Opcode); ConsumeComma (); - EmitSigned (GenBranchExpr (1), 1); + EmitSigned (GenBranchExpr (2), 1); } else if (A.AddrModeSet == 0x10000000) { A.Opcode += 0x04; /* Zeropage */ @@ -1870,6 +1878,59 @@ static void PutJSR816 (const InsDesc* Ins) } +static void PutJSR_m740 (const InsDesc* Ins) +/* Handle a JSR instruction for m740 */ +{ + EffAddr A; + + /* Evaluate the addressing mode used */ + GetEA (&A); + + /* From the possible addressing modes, remove the ones that are invalid + ** for this instruction or CPU. + */ + A.AddrModeSet &= Ins->AddrMode; + + /* Check if we have any adressing modes left */ + if (A.AddrModeSet == 0) { + Error ("Illegal addressing mode"); + return; + } + A.AddrMode = BitFind (A.AddrModeSet); + A.AddrModeBit = (0x01UL << A.AddrMode); + + /* Build the opcode */ + /* A.Opcode = Ins->BaseCode | EATab[Ins->ExtCode][A.AddrMode] | A.Reg; */ + A.Opcode = Ins->BaseCode; + + switch (A.AddrMode) { + case AM65I_DIR_IND: + A.Opcode = 0x02; + Emit1 (A.Opcode, A.Expr); + break; + case AM65I_ABS: + /* If we have an expression and it's const, get it's value */ + if (A.Expr) { + long Val = -1; + if (IsConstExpr (A.Expr, &Val)) { + if ((Val & 0xff00) == 0xff00) { + /* direct page */ + A.Opcode = 0x22; + Emit0 (A.Opcode); + EmitByte(GenByteExpr(A.Expr)); + return; + } + } + } + A.Opcode = 0x20; + Emit2 (A.Opcode, A.Expr); + break; + default: + Internal ("Invalid Opcode 0x%02x", A.Opcode); + } + +} + static void PutRTS (const InsDesc* Ins attribute ((unused))) /* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if diff --git a/src/ca65/instr.h b/src/ca65/instr.h index fff5a0f34..e31ae0734 100644 --- a/src/ca65/instr.h +++ b/src/ca65/instr.h @@ -68,8 +68,8 @@ #define AM65_ABS_LONG_X 0x00000080UL /* -- */ #define AM65_DIR_Y 0x00000100UL /* ZP, Y */ #define AM65_ABS_Y 0x00000200UL /* ABS, Y */ -#define AM65_DIR_IND 0x00000400UL /* ZP, IND */ -#define AM65_ABS_IND 0x00000800UL /* IND */ +#define AM65_DIR_IND 0x00000400UL /* (ZP IND) */ +#define AM65_ABS_IND 0x00000800UL /* (IND) */ #define AM65_DIR_IND_LONG 0x00001000UL /* -- */ #define AM65_DIR_IND_Y 0x00002000UL /* IND, Y */ #define AM65_DIR_IND_LONG_Y 0x00004000UL /* -- */ @@ -87,40 +87,55 @@ #define AM65_ABS_IND_LONG 0x04000000UL /* -- */ #define AM65_IMM_IMPLICIT_WORD 0x08000000UL /* PHW #$1234 (4510 only) */ #define AM65_ZP_REL 0x10000000UL /* ZP, REL (m740) */ +#define AM65_SPECIAL_PAGE 0x20000000UL /* $FFxx (m740) */ /* Bitmask for all ZP operations that have correspondent ABS ops */ -/* $8524 */ #define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND) - /*$4 $20 $100 $400 $8000 */ /* Bitmask for all ABS operations that have correspondent FAR ops */ -/* $48 */ #define AM65_SET_ABS (AM65_ABS | AM65_ABS_X) -/* $8 $40 */ /* Bitmask for all ZP operations */ -/* $8524 */ #define AM65_ALL_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND) - /*$4 $20 $100 $400 $8000 */ /* Bitmask for all ABS operations */ -/* $10a48 */ #define AM65_ALL_ABS (AM65_ABS | AM65_ABS_X | AM65_ABS_Y | AM65_ABS_IND | AM65_ABS_X_IND) -/* $8 $40 $200 $800 $10000 */ /* Bitmask for all FAR operations */ -/* $90 */ #define AM65_ALL_FAR (AM65_ABS_LONG | AM65_ABS_LONG_X) - /* $10 $80 */ - /* Bitmask for all immediate operations */ -/* $8e00 000 */ #define AM65_ALL_IMM (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT | AM65_IMM_IMPLICIT_WORD) -/* $200000 $400000 $800000 $8000000 */ + /* Bit numbers and count */ -#define AM65I_IMM_ACCU 21 -#define AM65I_IMM_INDEX 22 -#define AM65I_IMM_IMPLICIT 23 -#define AM65I_IMM_IMPLICIT_WORD 27 -#define AM65I_COUNT 28 +#define AM65I_IMPLICIT 0 +#define AM65I_ACCU 1 +#define AM65I_DIR 2 +#define AM65I_ABS 3 +#define AM65I_ABS_LONG 4 +#define AM65I_DIR_X 5 +#define AM65I_ABS_X 6 +#define AM65I_ABS_LONG_X 7 +#define AM65I_DIR_Y 8 +#define AM65I_ABS_Y 9 +#define AM65I_DIR_IND 10 +#define AM65I_ABS_IND 11 +#define AM65I_DIR_IND_LONG 12 +#define AM65I_DIR_IND_Y 13 +#define AM65I_DIR_IND_LONG_Y 14 +#define AM65I_DIR_X_IND 15 +#define AM65I_ABS_X_IND 16 +#define AM65I_REL 17 +#define AM65I_REL_LONG 18 +#define AM65I_STACK_REL 19 +#define AM65I_STACK_REL_IND_Y 20 +#define AM65I_IMM_ACCU 21 +#define AM65I_IMM_INDEX 22 +#define AM65I_IMM_IMPLICIT 23 +#define AM65I_BLOCKMOVE 24 +#define AM65I_BLOCKXFER 25 +#define AM65I_ABS_IND_LONG 26 +#define AM65I_IMM_IMPLICIT_WORD 27 +#define AM65I_ZP_REL 28 +#define AM65I_SPECIAL_PAGE 29 +#define AM65I_COUNT 30 diff --git a/src/da65/handler.c b/src/da65/handler.c index 356e84429..4f35fbaa3 100644 --- a/src/da65/handler.c +++ b/src/da65/handler.c @@ -795,14 +795,14 @@ void OH_JmpDirectIndirect (const OpcDesc* D) void OH_SpecialPage (const OpcDesc* D) { - /* Get the operand */ - unsigned Addr = 0xFF00 + GetCodeByte (PC+1); + /* Get the operand */ + unsigned Addr = 0xFF00 + GetCodeByte (PC+1); - /* Generate a label in pass 1 */ - GenerateLabel (D->Flags, Addr); + /* Generate a label in pass 1 */ + GenerateLabel (D->Flags, Addr); - /* OneLine (D, "$FF%02X", (CodeByte (PC+1)); */ - OneLine (D, "%s", GetAddrArg (D->Flags, Addr)); + /* OneLine (D, "$FF%02X", (CodeByte (PC+1)); */ + OneLine (D, "%s", GetAddrArg (D->Flags, Addr)); } diff --git a/src/da65/opcm740.c b/src/da65/opcm740.c index 676bf4dd4..6d12a7d37 100644 --- a/src/da65/opcm740.c +++ b/src/da65/opcm740.c @@ -44,7 +44,8 @@ /* Data */ /*****************************************************************************/ - +/* CAUTION: in the pdf $1a is dec, and $3a is inc - if that is really the case, + * the table below should be fixed and this notice removed */ /* Descriptions for all opcodes */ const OpcDesc OpcTable_M740[256] = { @@ -74,7 +75,7 @@ const OpcDesc OpcTable_M740[256] = { { "bbc0", 3, flUseLabel, OH_BitBranch_m740 }, /* $17 */ { "clc", 1, flNone, OH_Implicit }, /* $18 */ { "ora", 3, flUseLabel, OH_AbsoluteY }, /* $19 */ - { "dec", 1, flNone, OH_Accumulator }, /* $1a */ + { "inc", 1, flNone, OH_Accumulator }, /* $1a */ { "clb0", 1, flNone, OH_AccumulatorBit }, /* $1b */ { "", 1, flIllegal, OH_Illegal }, /* $1c */ { "ora", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1d */ @@ -106,7 +107,7 @@ const OpcDesc OpcTable_M740[256] = { { "bbc1", 3, flUseLabel, OH_BitBranch_m740 }, /* $37 */ { "sec", 1, flNone, OH_Implicit }, /* $38 */ { "and", 3, flUseLabel, OH_AbsoluteY }, /* $39 */ - { "inc", 1, flNone, OH_Accumulator }, /* $3a */ + { "dec", 1, flNone, OH_Accumulator }, /* $3a */ { "clb1", 1, flNone, OH_AccumulatorBit }, /* $3b */ { "ldm", 3, flLabel, OH_DirectImmediate }, /* $3c */ { "and", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3d */ diff --git a/test/asm/opcodes/m740-opcodes.ref b/test/asm/opcodes/m740-opcodes.ref new file mode 100644 index 0000000000000000000000000000000000000000..b3cffc9b6c66b8de4f1cdec2e9ae8304a0b02588 GIT binary patch literal 768 zcmV~$0{|cd006OYdD*sY+qP}n{A}B{ZQHhO+qDg(fi;K*RT@l#YX}Xgp)|CH5e=*1 zG`vR8h#E;FYZQ&D(KNco(3l!aV{06ZtMN3xCeVbMNE2%kO{&Q>xu(#Rno3h^8cnO| zG`(ifjG9R^YZlF_*)+T6(43k}b88;WtNAp)7SMuPNDFHbEvm(|xR%h8T1rc687-^j zw7gc(idso4YZa}k)wH_S(3)CHYik{?tM#StZK}<*xwg=j+Dcn%8*QuY zw7quFj@n5(YZvXR-L$**(4N{$dut!kOT#vvju3(YZQL=j#GpsEc&5F43jBOqc5lU8$>dwXV^% zx=z>Y2HmKebhB>Jt-4LO>ki$iyL7ki(Y?A)_v-;YsE72h9?_$EOpogcJ*lVkw4Twk zdQQ*l1-+=3^s-*jt9nhZ>kYlBxAeB&(Ytz2@9P77sE_oqKGCQ8OrPrueW|bXwZ74} h`cB{L2mPp@^s|1^ulh~D>ks{@zx22M(ZBjn{{s(bkAVOH literal 0 HcmV?d00001 diff --git a/test/asm/opcodes/m740-opcodes.s b/test/asm/opcodes/m740-opcodes.s index df6d71488..e4f8562cc 100644 --- a/test/asm/opcodes/m740-opcodes.s +++ b/test/asm/opcodes/m740-opcodes.s @@ -1,260 +1,565 @@ -.setcpu "65C02" -; copy of 65c02, comments note changes to the m740 according to -; http://documentation.renesas.com/doc/products/mpumcu/rej09b0322_740sm.pdf +; da65 V2.19 - Git 89651fd8b +; Created: 2025-06-16 20:10:42 +; Input file: testfile +; Page: 1 - brk - ora ($12,x) - .byte $02,$00,$00 ; jsr zp,ind - .byte $03,$00,$00 ; bbs 0,a - tsb $12 ; .byte $04 - ora $12 - asl $12 - rmb0 $12 ; bbs 0,zp - php - ora #$12 - asl a - .byte $0B,$00,$00 ; seb 0,a - tsb $3456 ; .byte $0c - ora $3456 - asl $3456 - bbr0 $12,*+122 ; seb 0,zp - bpl *+122 - ora ($12),y - ora ($12) ; clt - .byte $13,$00,$00 ; bbc 0,a - trb $12 ; .byte $14 - ora $12,x - asl $12,x - rmb1 $12 ; bbc 0,zp - clc - ora $3456,y - inc a - .byte $1B,$00,$00 ; clb 0,a - trb $3456 ; .byte $1c - ora $3456,x - asl $3456,x - bbr1 $12,*+122 ; clb 0,zp - jsr $3456 - and ($12,x) - .byte $22,$00,$00 ; jsr sp - .byte $23,$00,$00 ; bbs 1,a - bit $12 - and $12 - rol $12 - rmb2 $12 ; bbs 1,zp - plp - and #$12 - rol a - .byte $2B,$00,$00 ; seb 1,a - bit $3456 - and $3456 - rol $3456 - bbr2 $12,*+122 ; seb 1,zp - bmi *+122 - and ($12),y - and ($12) ; set - .byte $33,$00,$00 ; bbc 1,a - bit $12,x ; .byte $34 - and $12,x - rol $12,x - rmb3 $12 ; bbc 1,zp - sec - and $3456,y - dec a - .byte $3B,$00,$00 ; clb 1,a - bit $3456,x ; ldm zp - and $3456,x - rol $3456,x - bbr3 $12,*+122 ; clb 1,zp - rti - eor ($12,x) - .byte $42,$00,$00 ; stp - .byte $43,$00,$00 ; bbs 2,a - .byte $44,$00,$00 ; com zp - eor $12 - lsr $12 - rmb4 $12 ; bbs 2,zp - pha - eor #$12 - lsr a - .byte $4B,$00,$00 ; seb 2,a - jmp $3456 - eor $3456 - lsr $3456 - bbr4 $12,*+122 ; seb 2,zp - bvc *+122 - eor ($12),y - eor ($12) ; .byte $52 - .byte $53,$00,$00 ; bbc 2,a - .byte $54,$00,$00 - eor $12,x - lsr $12,x - rmb5 $12 ; bbc 2,zp - cli - eor $3456,y - phy - .byte $5B,$00,$00 ; clb 2,a - .byte $5C,$00,$00 - eor $3456,x - lsr $3456,x - bbr5 $12,*+122 ; clb 2,zp - rts - adc ($12,x) - .byte $62,$00,$00 ; mul zp,x - .byte $63,$00,$00 ; bbs 3,a - stz $12 ; tst zp - adc $12 - ror $12 - rmb6 $12 ; bbs 3,zp - pla - adc #$12 - ror a - .byte $6B,$00,$00 ; seb 3,a - jmp ($3456) - adc $3456 - ror $3456 - bbr6 $12,*+122 ; seb 3,zp - bvs *+122 - adc ($12),y - adc ($12) ; .byte $72 - .byte $73,$00,$00 ; bbc 3,a - stz $12,x ; .byte $74 - adc $12,x - ror $12,x - rmb7 $12 ; bbc 3,zp - sei - adc $3456,y - ply - .byte $7B,$00,$00 ; clb 3,a - jmp ($3456,x) ; .byte $7c - adc $3456,x - ror $3456,x - bbr7 $12,*+122 ; clb 3,zp - bra *+122 - sta ($12,x) - .byte $82,$00,$00 ; rrf zp - .byte $83,$00,$00 ; bbs 4,a - sty $12 - sta $12 - stx $12 - smb0 $12 ; bbs 4,zp - dey - bit #$12 - txa - .byte $8B,$00,$00 ; seb 4,a - sty $3456 - sta $3456 - stx $3456 - bbs0 $12,*+122 ; seb 4,zp - bcc *+122 - sta ($12),y - sta ($12) ; .byte $92 - .byte $93,$00,$00 ; bbc 4,a - sty $12,x - sta $12,x - stx $12,y - smb1 $12 ; bbc 4,zp - tya - sta $3456,y - txs - .byte $9B,$00,$00 ; clb 4,a - stz $3456 ; .byte $9c - sta $3456,x - stz $3456,x ; .byte $9e - bbs1 $12,*+122 ; clb 4,zp - ldy #$12 - lda ($12,x) - ldx #$12 - .byte $A3,$00,$00 ; bbs 5,a - ldy $12 - lda $12 - ldx $12 - smb2 $12 ; bbs 5,zp - tay - lda #$12 - tax - .byte $AB,$00,$00 ; seb 5,a - ldy $3456 - lda $3456 - ldx $3456 - bbs2 $12,*+122 ; seb 5,zp - bcs *+122 - lda ($12),y - lda ($12) ; .byte $b2 - .byte $B3,$00,$00 ; bbc 5,a - ldy $12,x - lda $12,x - ldx $12,y - smb3 $12 ; bbc 5,zp - clv - lda $3456,y - tsx - .byte $BB,$00,$00 ; clb 5,a - ldy $3456,x - lda $3456,x - ldx $3456,y - bbs3 $12,*+122 ; clb 5,zp - cpy #$12 - cmp ($12,x) - .byte $C2,$00,$00 ; wit - .byte $C3,$00,$00 ; bbs 6,a - cpy $12 - cmp $12 - dec $12 - smb4 $12 ; bbs 6,zp - iny - cmp #$12 - dex - .byte $CB,$00,$00 ; seb 6,a - cpy $3456 - cmp $3456 - dec $3456 - bbs4 $12,*+122 ; seb 6,zp - bne *+122 - cmp ($12),y - cmp ($12) ; .byte $d2 - .byte $D3,$00,$00 ; bbc 6,a - .byte $D4,$00,$00 - cmp $12,x - dec $12,x - smb5 $12 ; bbc 6,zp - cld - cmp $3456,y - phx - .byte $DB,$00,$00 ; clb 6,a - .byte $DC,$00,$00 - cmp $3456,x - dec $3456,x - bbs5 $12,*+122 ; clb 6,zp - cpx #$12 - sbc ($12,x) - .byte $E2,$00,$00 ; div zp,x - .byte $E3,$00,$00 ; bbs 7,a - cpx $12 - sbc $12 - inc $12 - smb6 $12 ; bbs 7,zp - inx - sbc #$12 - nop - .byte $EB,$00,$00 ; seb 7,a - cpx $3456 - sbc $3456 - inc $3456 - bbs6 $12,*+122 ; seb 7,zp - beq *+122 - sbc ($12),y - sbc ($12) ; .byte $f2 - .byte $F3,$00,$00 ; bbc 7,a - .byte $F4,$00,$00 - sbc $12,x - inc $12,x - smb7 $12 ; bbc 7,zp - sed - sbc $3456,y - plx - .byte $FB,$00,$00 ; clb 7,a - .byte $FC,$00,$00 - sbc $3456,x - inc $3456,x - bbs7 $12,*+122 ; clb 7,zp + + .setcpu "m740" + +L000C := $000C +L040C := $040C +LFF0C := $FF0C + brk + .byte $0C + .byte $04 + ora (L000C,x) + .byte $04 + jsr (L000C) + + .byte $04 + bbs0 a, L8018 + .byte $04 + .byte $04 + .byte $0C + .byte $04 + ora L000C + .byte $04 + asl L000C + .byte $04 + bbs0 L000C, L801C +L8018: php + .byte $0C + .byte $04 + .byte $09 +L801C: .byte $0C + .byte $04 + asl a + .byte $0C + .byte $04 + seb0 a + .byte $0C + .byte $04 + .byte $0C + .byte $0C + .byte $04 + ora L040C + asl L040C + seb0 L000C + .byte $04 + bpl L803E + .byte $04 + ora (L000C),y + .byte $04 + clt + .byte $0C + .byte $04 + bbc0 a, L8048 + .byte $04 + .byte $14 + .byte $0C +L803E: .byte $04 + ora L000C,x + .byte $04 + asl L000C,x + .byte $04 + bbc0 L000C, L804C +L8048: clc + .byte $0C + .byte $04 + .byte $19 +L804C: .byte $0C + .byte $04 + inc a + .byte $0C + .byte $04 + clb0 a + .byte $0C + .byte $04 + .byte $1C + .byte $0C + .byte $04 + ora L040C,x + asl L040C,x + clb0 L000C + .byte $04 + jsr L040C + and (L000C,x) + .byte $04 + jsr LFF0C + .byte $04 + bbs1 a, L8078 + .byte $04 + bit L000C + .byte $04 + and L000C + .byte $04 + rol L000C + .byte $04 + bbs1 L000C, L807C +L8078: plp + .byte $0C + .byte $04 + .byte $29 +L807C: .byte $0C + .byte $04 + rol a + .byte $0C + .byte $04 + seb1 a + .byte $0C + .byte $04 + bit L040C + and L040C + rol L040C + seb1 L000C + .byte $04 + bmi L809E + .byte $04 + and (L000C),y + .byte $04 + set + .byte $0C + .byte $04 + bbc1 a, L80A8 + .byte $04 + .byte $34 + .byte $0C +L809E: .byte $04 + and L000C,x + .byte $04 + rol L000C,x + .byte $04 + bbc1 L000C, L80AC +L80A8: sec + .byte $0C + .byte $04 + .byte $39 +L80AC: .byte $0C + .byte $04 + dec a + .byte $0C + .byte $04 + clb1 a + .byte $0C + .byte $04 + ldm L000C, #$04 + and L040C,x + rol L040C,x + clb1 L000C + .byte $04 + rti + + .byte $0C + .byte $04 + eor (L000C,x) + .byte $04 + stp + .byte $0C + .byte $04 + bbs2 a, L80D8 + .byte $04 + com L000C + .byte $04 + eor L000C + .byte $04 + lsr L000C + .byte $04 + bbs2 L000C, L80DC +L80D8: pha + .byte $0C + .byte $04 + .byte $49 +L80DC: .byte $0C + .byte $04 + lsr a + .byte $0C + .byte $04 + seb2 a + .byte $0C + .byte $04 + jmp L040C + + eor L040C + lsr L040C + seb2 L000C + .byte $04 + bvc L80FE + .byte $04 + eor (L000C),y + .byte $04 + .byte $52 + .byte $0C + .byte $04 + bbc2 a, L8108 + .byte $04 + .byte $54 + .byte $0C +L80FE: .byte $04 + eor L000C,x + .byte $04 + lsr L000C,x + .byte $04 + bbc2 L000C, L810C +L8108: cli + .byte $0C + .byte $04 + .byte $59 +L810C: .byte $0C + .byte $04 + .byte $5A + .byte $0C + .byte $04 + clb2 a + .byte $0C + .byte $04 + .byte $5C + .byte $0C + .byte $04 + eor L040C,x + lsr L040C,x + clb2 L000C + .byte $04 + rts + + .byte $0C + .byte $04 + adc (L000C,x) + .byte $04 + .byte $62 + .byte $0C + .byte $04 + bbs3 a, L8138 + .byte $04 + tst L000C + .byte $04 + adc L000C + .byte $04 + ror L000C + .byte $04 + bbs3 L000C, L813C +L8138: pla + .byte $0C + .byte $04 + .byte $69 +L813C: .byte $0C + .byte $04 + ror a + .byte $0C + .byte $04 + seb3 a + .byte $0C + .byte $04 + jmp (L040C) + + adc L040C + ror L040C + seb3 L000C + .byte $04 + bvs L815E + .byte $04 + adc (L000C),y + .byte $04 + .byte $72 + .byte $0C + .byte $04 + bbc3 a, L8168 + .byte $04 + .byte $74 + .byte $0C +L815E: .byte $04 + adc L000C,x + .byte $04 + ror L000C,x + .byte $04 + bbc3 L000C, L816C +L8168: sei + .byte $0C + .byte $04 + .byte $79 +L816C: .byte $0C + .byte $04 + .byte $7A + .byte $0C + .byte $04 + clb3 a + .byte $0C + .byte $04 + .byte $7C + .byte $0C + .byte $04 + adc L040C,x + ror L040C,x + clb3 L000C + .byte $04 + bra L818E + .byte $04 + sta (L000C,x) + .byte $04 + rrf L000C + .byte $04 + bbs4 a, L8198 + .byte $04 + sty L000C +L818E: .byte $04 + sta L000C + .byte $04 + stx L000C + .byte $04 + bbs4 L000C, L819C +L8198: dey + .byte $0C + .byte $04 + .byte $89 +L819C: .byte $0C + .byte $04 + txa + .byte $0C + .byte $04 + seb4 a + .byte $0C + .byte $04 + sty L040C + sta L040C + stx L040C + seb4 L000C + .byte $04 + bcc L81BE + .byte $04 + sta (L000C),y + .byte $04 + .byte $92 + .byte $0C + .byte $04 + bbc4 a, L81C8 + .byte $04 + sty L000C,x +L81BE: .byte $04 + sta L000C,x + .byte $04 + stx L000C,y + .byte $04 + bbc4 L000C, L81CC +L81C8: tya + .byte $0C + .byte $04 + .byte $99 +L81CC: .byte $0C + .byte $04 + txs + .byte $0C + .byte $04 + clb4 a + .byte $0C + .byte $04 + .byte $9C + .byte $0C + .byte $04 + sta L040C,x + .byte $9E + .byte $0C + .byte $04 + clb4 L000C + .byte $04 + ldy #$0C + .byte $04 + lda (L000C,x) + .byte $04 + ldx #$0C + .byte $04 + bbs5 a, L81F8 + .byte $04 + ldy L000C + .byte $04 + lda L000C + .byte $04 + ldx L000C + .byte $04 + bbs5 L000C, L81FC +L81F8: tay + .byte $0C + .byte $04 + .byte $A9 +L81FC: .byte $0C + .byte $04 + tax + .byte $0C + .byte $04 + seb5 a + .byte $0C + .byte $04 + ldy L040C + lda L040C + ldx L040C + seb5 L000C + .byte $04 + bcs L821E + .byte $04 + lda (L000C),y + .byte $04 + jmp (L000C) + + .byte $04 + bbc5 a, L8228 + .byte $04 + ldy L000C,x +L821E: .byte $04 + lda L000C,x + .byte $04 + ldx L000C,y + .byte $04 + bbc5 L000C, L822C +L8228: clv + .byte $0C + .byte $04 + .byte $B9 +L822C: .byte $0C + .byte $04 + tsx + .byte $0C + .byte $04 + clb5 a + .byte $0C + .byte $04 + ldy L040C,x + lda L040C,x + ldx L040C,y + clb5 L000C + .byte $04 + cpy #$0C + .byte $04 + cmp (L000C,x) + .byte $04 + slw + .byte $0C + .byte $04 + bbs6 a, L8258 + .byte $04 + cpy L000C + .byte $04 + cmp L000C + .byte $04 + dec L000C + .byte $04 + bbs6 L000C, L825C +L8258: iny + .byte $0C + .byte $04 + .byte $C9 +L825C: .byte $0C + .byte $04 + dex + .byte $0C + .byte $04 + seb6 a + .byte $0C + .byte $04 + cpy L040C + cmp L040C + dec L040C + seb6 L000C + .byte $04 + bne L827E + .byte $04 + cmp (L000C),y + .byte $04 + .byte $D2 + .byte $0C + .byte $04 + bbc6 a, L8288 + .byte $04 + .byte $D4 + .byte $0C +L827E: .byte $04 + cmp L000C,x + .byte $04 + dec L000C,x + .byte $04 + bbc6 L000C, L828C +L8288: cld + .byte $0C + .byte $04 + .byte $D9 +L828C: .byte $0C + .byte $04 + .byte $DA + .byte $0C + .byte $04 + clb6 a + .byte $0C + .byte $04 + .byte $DC + .byte $0C + .byte $04 + cmp L040C,x + dec L040C,x + clb6 L000C + .byte $04 + cpx #$0C + .byte $04 + sbc (L000C,x) + .byte $04 + fst + .byte $0C + .byte $04 + bbs7 a, L82B8 + .byte $04 + cpx L000C + .byte $04 + sbc L000C + .byte $04 + inc L000C + .byte $04 + bbs7 L000C, L82BC +L82B8: inx + .byte $0C + .byte $04 + .byte $E9 +L82BC: .byte $0C + .byte $04 + nop + .byte $0C + .byte $04 + seb7 a + .byte $0C + .byte $04 + cpx L040C + sbc L040C + inc L040C + seb7 L000C + .byte $04 + beq L82DE + .byte $04 + sbc (L000C),y + .byte $04 + .byte $F2 + .byte $0C + .byte $04 + bbc7 a, L82E8 + .byte $04 + .byte $F4 + .byte $0C +L82DE: .byte $04 + sbc L000C,x + .byte $04 + inc L000C,x + .byte $04 + bbc7 L000C, L82EC +L82E8: sed + .byte $0C + .byte $04 + .byte $F9 +L82EC: .byte $0C + .byte $04 + .byte $FA + .byte $0C + .byte $04 + clb7 a + .byte $0C + .byte $04 + .byte $FC + .byte $0C + .byte $04 + sbc L040C,x + inc L040C,x + clb7 L000C + .byte $04 From 0b74ae8c2d80fcba49ed5b0557da414363f0f9c0 Mon Sep 17 00:00:00 2001 From: mrdudz Date: Mon, 16 Jun 2025 21:59:38 +0200 Subject: [PATCH 06/26] add m740 to macpack cpu, add .ifpm740, add regression test for those --- asminc/cpu.mac | 3 ++- src/ca65/condasm.c | 11 +++++++++++ src/ca65/pseudo.c | 1 + src/ca65/scanner.c | 1 + src/ca65/token.h | 1 + test/asm/cpudetect/cpudetect.s | 8 ++++++++ test/asm/cpudetect/m740-cpudetect.ref | Bin 0 -> 30 bytes 7 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 test/asm/cpudetect/m740-cpudetect.ref diff --git a/asminc/cpu.mac b/asminc/cpu.mac index 084a42119..1f5c0758e 100644 --- a/asminc/cpu.mac +++ b/asminc/cpu.mac @@ -8,7 +8,7 @@ CPU_ISET_65C02 = $0020 CPU_ISET_65816 = $0040 CPU_ISET_SWEET16 = $0080 CPU_ISET_HUC6280 = $0100 -;CPU_ISET_M740 = $0200 not actually implemented +CPU_ISET_M740 = $0200 CPU_ISET_4510 = $0400 ; CPU capabilities @@ -22,3 +22,4 @@ CPU_65816 = CPU_ISET_6502|CPU_ISET_65SC02|CPU_ISET_65816 CPU_SWEET16 = CPU_ISET_SWEET16 CPU_HUC6280 = CPU_ISET_6502|CPU_ISET_65SC02|CPU_ISET_65C02|CPU_ISET_HUC6280 CPU_4510 = CPU_ISET_6502|CPU_ISET_65SC02|CPU_ISET_65C02|CPU_ISET_4510 +CPU_M740 = CPU_ISET_6502|CPU_ISET_M740 diff --git a/src/ca65/condasm.c b/src/ca65/condasm.c index f872ec9ed..049367758 100644 --- a/src/ca65/condasm.c +++ b/src/ca65/condasm.c @@ -434,6 +434,16 @@ void DoConditionals (void) CalcOverallIfCond (); break; + case TOK_IFPM740: + D = AllocIf (".IFPM740", 1); + NextTok (); + if (IfCond) { + SetIfCond (D, GetCPU() == CPU_M740); + } + ExpectSep (); + CalcOverallIfCond (); + break; + case TOK_IFPSC02: D = AllocIf (".IFPSC02", 1); NextTok (); @@ -489,6 +499,7 @@ int CheckConditionals (void) case TOK_IFP816: case TOK_IFPC02: case TOK_IFPDTV: + case TOK_IFPM740: case TOK_IFPSC02: case TOK_IFREF: DoConditionals (); diff --git a/src/ca65/pseudo.c b/src/ca65/pseudo.c index 2ce1ae087..2a14295ab 100644 --- a/src/ca65/pseudo.c +++ b/src/ca65/pseudo.c @@ -2135,6 +2135,7 @@ static CtrlDesc CtrlCmdTab [] = { { ccKeepToken, DoConditionals }, /* .IFP816 */ { ccKeepToken, DoConditionals }, /* .IFPC02 */ { ccKeepToken, DoConditionals }, /* .IFPDTV */ + { ccKeepToken, DoConditionals }, /* .IFPM740 */ { ccKeepToken, DoConditionals }, /* .IFPSC02 */ { ccKeepToken, DoConditionals }, /* .IFREF */ { ccNone, DoImport }, diff --git a/src/ca65/scanner.c b/src/ca65/scanner.c index 94c84d897..f93ae977e 100644 --- a/src/ca65/scanner.c +++ b/src/ca65/scanner.c @@ -225,6 +225,7 @@ struct DotKeyword { { ".IFP816", TOK_IFP816 }, { ".IFPC02", TOK_IFPC02 }, { ".IFPDTV", TOK_IFPDTV }, + { ".IFPM740", TOK_IFPM740 }, { ".IFPSC02", TOK_IFPSC02 }, { ".IFREF", TOK_IFREF }, { ".IMPORT", TOK_IMPORT }, diff --git a/src/ca65/token.h b/src/ca65/token.h index 8f935f7a1..a29c6e5ab 100644 --- a/src/ca65/token.h +++ b/src/ca65/token.h @@ -197,6 +197,7 @@ typedef enum token_t { TOK_IFP816, TOK_IFPC02, TOK_IFPDTV, + TOK_IFPM740, TOK_IFPSC02, TOK_IFREF, TOK_IMPORT, diff --git a/test/asm/cpudetect/cpudetect.s b/test/asm/cpudetect/cpudetect.s index 7b2363b7f..d4d5b9f9f 100644 --- a/test/asm/cpudetect/cpudetect.s +++ b/test/asm/cpudetect/cpudetect.s @@ -28,6 +28,10 @@ sac #$00 .endif +.ifpm740 + jsr $ff12 +.endif + ; step 2: check for bitwise compatibility of instructions sets ; (made verbose for better reading with hexdump/hd(1)) @@ -72,3 +76,7 @@ .byte 0,"CPU_ISET_6502DTV" .endif +.if (.cpu .bitand CPU_ISET_M740) + .byte 0,"CPU_ISET_M740" +.endif + diff --git a/test/asm/cpudetect/m740-cpudetect.ref b/test/asm/cpudetect/m740-cpudetect.ref new file mode 100644 index 0000000000000000000000000000000000000000..7788f3ed95ee9e39843989436875ff8889986a60 GIT binary patch literal 30 ccmY!qVsH)!jrR<84T(21H84W(e9cV^0C1ECpa1{> literal 0 HcmV?d00001 From 2e27ee1702a3691731570ab1a2529ffb5cf2b8cb Mon Sep 17 00:00:00 2001 From: mrdudz Date: Mon, 16 Jun 2025 22:55:58 +0200 Subject: [PATCH 07/26] added .IFM740 and .PM470, and while at it also .IFP02X and .P02X. Updated regression test to use these --- src/ca65/condasm.c | 11 ++ src/ca65/pseudo.c | 199 ++++++++++++++----------- src/ca65/scanner.c | 3 + src/ca65/token.h | 3 + test/asm/cpudetect/6502x-cpudetect.ref | Bin 29 -> 31 bytes test/asm/cpudetect/cpudetect.s | 15 ++ 6 files changed, 142 insertions(+), 89 deletions(-) diff --git a/src/ca65/condasm.c b/src/ca65/condasm.c index 049367758..a65fbebba 100644 --- a/src/ca65/condasm.c +++ b/src/ca65/condasm.c @@ -394,6 +394,16 @@ void DoConditionals (void) CalcOverallIfCond (); break; + case TOK_IFP02X: + D = AllocIf (".IFP02X", 1); + NextTok (); + if (IfCond) { + SetIfCond (D, GetCPU() == CPU_6502X); + } + ExpectSep (); + CalcOverallIfCond (); + break; + case TOK_IFP4510: D = AllocIf (".IFP4510", 1); NextTok (); @@ -495,6 +505,7 @@ int CheckConditionals (void) case TOK_IFNDEF: case TOK_IFNREF: case TOK_IFP02: + case TOK_IFP02X: case TOK_IFP4510: case TOK_IFP816: case TOK_IFPC02: diff --git a/src/ca65/pseudo.c b/src/ca65/pseudo.c index 2a14295ab..6cad9ed51 100644 --- a/src/ca65/pseudo.c +++ b/src/ca65/pseudo.c @@ -1562,6 +1562,14 @@ static void DoP02 (void) +static void DoP02X (void) +/* Switch to 6502X CPU */ +{ + SetCPU (CPU_6502X); +} + + + static void DoPC02 (void) /* Switch to 65C02 CPU */ { @@ -1594,6 +1602,14 @@ static void DoPDTV (void) +static void DoPM740 (void) +/* Switch to M740 CPU */ +{ + SetCPU (CPU_M740); +} + + + static void DoPageLength (void) /* Set the page length for the listing */ { @@ -2057,70 +2073,72 @@ struct CtrlDesc { void (*Handler) (void); /* Command handler */ }; +/* NOTE: .AND, .BITAND, .BITNOT, .BITOR, .BITXOR, .MOD, .NOT, .OR, .SHL, .SHR + and .XOR do NOT go into this table */ #define PSEUDO_COUNT (sizeof (CtrlCmdTab) / sizeof (CtrlCmdTab [0])) static CtrlDesc CtrlCmdTab [] = { - { ccNone, DoA16 }, - { ccNone, DoA8 }, + { ccNone, DoA16 }, /* .A16 */ + { ccNone, DoA8 }, /* .A8 */ { ccNone, DoAddr }, /* .ADDR */ { ccNone, DoUnexpected }, /* .ADDRSIZE */ - { ccNone, DoAlign }, - { ccNone, DoASCIIZ }, + { ccNone, DoAlign }, /* .ALIGN */ + { ccNone, DoASCIIZ }, /* .ASCIIZ */ { ccNone, DoUnexpected }, /* .ASIZE */ - { ccNone, DoAssert }, - { ccNone, DoAutoImport }, + { ccNone, DoAssert }, /* .ASSERT */ + { ccNone, DoAutoImport }, /* .AUTOIMPORT */ { ccNone, DoUnexpected }, /* .BANK */ { ccNone, DoUnexpected }, /* .BANKBYTE */ - { ccNone, DoBankBytes }, + { ccNone, DoBankBytes }, /* .BANKBYTES */ { ccNone, DoUnexpected }, /* .BLANK */ - { ccNone, DoBss }, - { ccNone, DoByte }, - { ccNone, DoCase }, - { ccNone, DoCharMap }, - { ccNone, DoCode }, + { ccNone, DoBss }, /* .BSS */ + { ccNone, DoByte }, /* .BYT, .BYTE */ + { ccNone, DoCase }, /* .CASE */ + { ccNone, DoCharMap }, /* .CHARMAP */ + { ccNone, DoCode }, /* .CODE */ { ccNone, DoUnexpected, }, /* .CONCAT */ - { ccNone, DoConDes }, + { ccNone, DoConDes }, /* .CONDES */ { ccNone, DoUnexpected }, /* .CONST */ - { ccNone, DoConstructor }, + { ccNone, DoConstructor }, /* .CONSTRUCTOR */ { ccNone, DoUnexpected }, /* .CPU */ - { ccNone, DoData }, - { ccNone, DoDbg, }, - { ccNone, DoDByt }, - { ccNone, DoDebugInfo }, - { ccKeepToken, DoDefine }, + { ccNone, DoData }, /* .DATA */ + { ccNone, DoDbg, }, /* .DBG */ + { ccNone, DoDByt }, /* .DBYT */ + { ccNone, DoDebugInfo }, /* .DEBUGINFO */ + { ccKeepToken, DoDefine }, /* .DEF, .DEFINE */ { ccNone, DoUnexpected }, /* .DEFINED */ { ccNone, DoUnexpected }, /* .DEFINEDMACRO */ - { ccNone, DoDelMac }, - { ccNone, DoDestructor }, - { ccNone, DoDWord }, + { ccNone, DoDelMac }, /* .DELMAC, .DELMACRO */ + { ccNone, DoDestructor }, /* .DESTRUCTOR */ + { ccNone, DoDWord }, /* .DWORD */ { ccKeepToken, DoConditionals }, /* .ELSE */ { ccKeepToken, DoConditionals }, /* .ELSEIF */ - { ccKeepToken, DoEnd }, + { ccKeepToken, DoEnd }, /* .END */ { ccNone, DoUnexpected }, /* .ENDENUM */ { ccKeepToken, DoConditionals }, /* .ENDIF */ - { ccNone, DoUnexpected }, /* .ENDMACRO */ - { ccNone, DoEndProc }, - { ccNone, DoUnexpected }, /* .ENDREPEAT */ - { ccNone, DoEndScope }, + { ccNone, DoUnexpected }, /* .ENDMAC, .ENDMACRO */ + { ccNone, DoEndProc }, /* .ENDPROC */ + { ccNone, DoUnexpected }, /* .ENDREP, .ENDREPEAT */ + { ccNone, DoEndScope }, /* .ENDSCOPE */ { ccNone, DoUnexpected }, /* .ENDSTRUCT */ { ccNone, DoUnexpected }, /* .ENDUNION */ - { ccNone, DoEnum }, - { ccNone, DoError }, - { ccNone, DoExitMacro }, - { ccNone, DoExport }, - { ccNone, DoExportZP }, - { ccNone, DoFarAddr }, - { ccNone, DoFatal }, - { ccNone, DoFeature }, - { ccNone, DoFileOpt }, - { ccNone, DoForceImport }, + { ccNone, DoEnum }, /* .ENUM */ + { ccNone, DoError }, /* .ERROR */ + { ccNone, DoExitMacro }, /* .EXITMAC, .EXITMACRO */ + { ccNone, DoExport }, /* .EXPORT */ + { ccNone, DoExportZP }, /* .EXPORTZP */ + { ccNone, DoFarAddr }, /* .FARADDR */ + { ccNone, DoFatal }, /* .FATAL */ + { ccNone, DoFeature }, /* .FEATURE */ + { ccNone, DoFileOpt }, /* .FOPT, .FILEOPT */ + { ccNone, DoForceImport }, /* .FORCEIMPORT */ { ccNone, DoUnexpected }, /* .FORCEWORD */ - { ccNone, DoGlobal }, - { ccNone, DoGlobalZP }, + { ccNone, DoGlobal }, /* .GLOBAL */ + { ccNone, DoGlobalZP }, /* .GLOBALZP */ { ccNone, DoUnexpected }, /* .HIBYTE */ - { ccNone, DoHiBytes }, + { ccNone, DoHiBytes }, /* .HIBYTES */ { ccNone, DoUnexpected }, /* .HIWORD */ - { ccNone, DoI16 }, - { ccNone, DoI8 }, + { ccNone, DoI16 }, /* .I16 */ + { ccNone, DoI8 }, /* .I8 */ { ccNone, DoUnexpected }, /* .IDENT */ { ccKeepToken, DoConditionals }, /* .IF */ { ccKeepToken, DoConditionals }, /* .IFBLANK */ @@ -2131,6 +2149,7 @@ static CtrlDesc CtrlCmdTab [] = { { ccKeepToken, DoConditionals }, /* .IFNDEF */ { ccKeepToken, DoConditionals }, /* .IFNREF */ { ccKeepToken, DoConditionals }, /* .IFP02 */ + { ccKeepToken, DoConditionals }, /* .IFP02X */ { ccKeepToken, DoConditionals }, /* .IFP4510 */ { ccKeepToken, DoConditionals }, /* .IFP816 */ { ccKeepToken, DoConditionals }, /* .IFPC02 */ @@ -2138,75 +2157,77 @@ static CtrlDesc CtrlCmdTab [] = { { ccKeepToken, DoConditionals }, /* .IFPM740 */ { ccKeepToken, DoConditionals }, /* .IFPSC02 */ { ccKeepToken, DoConditionals }, /* .IFREF */ - { ccNone, DoImport }, - { ccNone, DoImportZP }, - { ccNone, DoIncBin }, - { ccNone, DoInclude }, - { ccNone, DoInterruptor }, + { ccNone, DoImport }, /* .IMPORT */ + { ccNone, DoImportZP }, /* .IMPORTZP */ + { ccNone, DoIncBin }, /* .INCBIN */ + { ccNone, DoInclude }, /* .INCLUDE */ + { ccNone, DoInterruptor }, /* .INTERRUPTPOR */ { ccNone, DoUnexpected }, /* .ISIZE */ { ccNone, DoUnexpected }, /* .ISMNEMONIC */ { ccNone, DoInvalid }, /* .LEFT */ - { ccNone, DoLineCont }, - { ccNone, DoList }, - { ccNone, DoListBytes }, - { ccNone, DoLiteral }, + { ccNone, DoLineCont }, /* .LINECONT */ + { ccNone, DoList }, /* .LIST */ + { ccNone, DoListBytes }, /* .LISTBYTES */ + { ccNone, DoLiteral }, /* .LITERAL */ { ccNone, DoUnexpected }, /* .LOBYTE */ - { ccNone, DoLoBytes }, + { ccNone, DoLoBytes }, /* .LOBYTES */ { ccNone, DoUnexpected }, /* .LOCAL */ - { ccNone, DoLocalChar }, + { ccNone, DoLocalChar }, /* .LOCALCHAR */ { ccNone, DoUnexpected }, /* .LOWORD */ - { ccNone, DoMacPack }, - { ccNone, DoMacro }, + { ccNone, DoMacPack }, /* .MACPACK */ + { ccNone, DoMacro }, /* .MAC, .MACRO */ { ccNone, DoUnexpected }, /* .MATCH */ { ccNone, DoUnexpected }, /* .MAX */ { ccNone, DoInvalid }, /* .MID */ { ccNone, DoUnexpected }, /* .MIN */ - { ccNone, DoNull }, - { ccNone, DoOrg }, - { ccNone, DoOut }, - { ccNone, DoP02 }, - { ccNone, DoP4510 }, - { ccNone, DoP816 }, - { ccNone, DoPageLength }, + { ccNone, DoNull }, /* .NULL */ + { ccNone, DoOrg }, /* .ORG */ + { ccNone, DoOut }, /* .OUT */ + { ccNone, DoP02 }, /* .P02 */ + { ccNone, DoP02X }, /* .P02X */ + { ccNone, DoP4510 }, /* .P4510 */ + { ccNone, DoP816 }, /* .P816 */ + { ccNone, DoPageLength }, /* .PAGELEN, .PAGELENGTH */ { ccNone, DoUnexpected }, /* .PARAMCOUNT */ - { ccNone, DoPC02 }, - { ccNone, DoPDTV }, - { ccNone, DoPopCharmap }, - { ccNone, DoPopCPU }, - { ccNone, DoPopSeg }, - { ccNone, DoProc }, - { ccNone, DoPSC02 }, - { ccNone, DoPushCharmap }, - { ccNone, DoPushCPU }, - { ccNone, DoPushSeg }, - { ccNone, DoUnexpected }, /* .REFERENCED */ - { ccNone, DoReferTo }, /* .REFERTO */ - { ccNone, DoReloc }, - { ccNone, DoRepeat }, - { ccNone, DoRes }, + { ccNone, DoPC02 }, /* .PSC02 */ + { ccNone, DoPDTV }, /* .PDTV */ + { ccNone, DoPM740 }, /* .PM740 */ + { ccNone, DoPopCharmap }, /* .POPCHARMAP */ + { ccNone, DoPopCPU }, /* .POPCPU */ + { ccNone, DoPopSeg }, /* .POPSEG */ + { ccNone, DoProc }, /* .PROC */ + { ccNone, DoPSC02 }, /* .PSC02 */ + { ccNone, DoPushCharmap }, /* .PUSHCHARMAP */ + { ccNone, DoPushCPU }, /* .PUSHCPU */ + { ccNone, DoPushSeg }, /* .PUSHSEG */ + { ccNone, DoUnexpected }, /* .REF, .REFERENCED */ + { ccNone, DoReferTo }, /* .REFTO, .REFERTO */ + { ccNone, DoReloc }, /* .RELOC */ + { ccNone, DoRepeat }, /* .REPEAT */ + { ccNone, DoRes }, /* .RES */ { ccNone, DoInvalid }, /* .RIGHT */ - { ccNone, DoROData }, - { ccNone, DoScope }, - { ccNone, DoSegment }, + { ccNone, DoROData }, /* .RODATA */ + { ccNone, DoScope }, /* .SCOPE */ + { ccNone, DoSegment }, /* .SEGMENT */ { ccNone, DoUnexpected }, /* .SET */ - { ccNone, DoSetCPU }, + { ccNone, DoSetCPU }, /* .SETCPU */ { ccNone, DoUnexpected }, /* .SIZEOF */ - { ccNone, DoSmart }, + { ccNone, DoSmart }, /* .SMART */ { ccNone, DoUnexpected }, /* .SPRINTF */ { ccNone, DoUnexpected }, /* .STRAT */ { ccNone, DoUnexpected }, /* .STRING */ { ccNone, DoUnexpected }, /* .STRLEN */ - { ccNone, DoStruct }, - { ccNone, DoTag }, + { ccNone, DoStruct }, /* .STRUCT */ + { ccNone, DoTag }, /* .TAG */ { ccNone, DoUnexpected }, /* .TCOUNT */ { ccNone, DoUnexpected }, /* .TIME */ - { ccKeepToken, DoUnDef }, - { ccNone, DoUnion }, + { ccKeepToken, DoUnDef }, /* .UNDEF, .UNDEFINE */ + { ccNone, DoUnion }, /* .UNION */ { ccNone, DoUnexpected }, /* .VERSION */ - { ccNone, DoWarning }, - { ccNone, DoWord }, + { ccNone, DoWarning }, /* .WARNING */ + { ccNone, DoWord }, /* .WORD */ { ccNone, DoUnexpected }, /* .XMATCH */ - { ccNone, DoZeropage }, + { ccNone, DoZeropage }, /* .ZEROPAGE */ }; diff --git a/src/ca65/scanner.c b/src/ca65/scanner.c index f93ae977e..0d90ddc7f 100644 --- a/src/ca65/scanner.c +++ b/src/ca65/scanner.c @@ -221,6 +221,7 @@ struct DotKeyword { { ".IFNDEF", TOK_IFNDEF }, { ".IFNREF", TOK_IFNREF }, { ".IFP02", TOK_IFP02 }, + { ".IFP02X", TOK_IFP02X }, { ".IFP4510", TOK_IFP4510 }, { ".IFP816", TOK_IFP816 }, { ".IFPC02", TOK_IFPC02 }, @@ -260,6 +261,7 @@ struct DotKeyword { { ".ORG", TOK_ORG }, { ".OUT", TOK_OUT }, { ".P02", TOK_P02 }, + { ".P02X", TOK_P02X }, { ".P4510", TOK_P4510 }, { ".P816", TOK_P816 }, { ".PAGELEN", TOK_PAGELENGTH }, @@ -267,6 +269,7 @@ struct DotKeyword { { ".PARAMCOUNT", TOK_PARAMCOUNT }, { ".PC02", TOK_PC02 }, { ".PDTV", TOK_PDTV }, + { ".PM740", TOK_PM740 }, { ".POPCHARMAP", TOK_POPCHARMAP }, { ".POPCPU", TOK_POPCPU }, { ".POPSEG", TOK_POPSEG }, diff --git a/src/ca65/token.h b/src/ca65/token.h index a29c6e5ab..d4fa3a697 100644 --- a/src/ca65/token.h +++ b/src/ca65/token.h @@ -193,6 +193,7 @@ typedef enum token_t { TOK_IFNDEF, TOK_IFNREF, TOK_IFP02, + TOK_IFP02X, TOK_IFP4510, TOK_IFP816, TOK_IFPC02, @@ -227,12 +228,14 @@ typedef enum token_t { TOK_ORG, TOK_OUT, TOK_P02, + TOK_P02X, TOK_P4510, TOK_P816, TOK_PAGELENGTH, TOK_PARAMCOUNT, TOK_PC02, TOK_PDTV, + TOK_PM740, TOK_POPCHARMAP, TOK_POPCPU, TOK_POPSEG, diff --git a/test/asm/cpudetect/6502x-cpudetect.ref b/test/asm/cpudetect/6502x-cpudetect.ref index 3434ecbea7fb1e119879fae346989933fd09bacd..9e7abe573ffc65dce67d2b8b95d1c3ef9827bd71 100644 GIT binary patch delta 7 Ocmb1@XIlMgf-C?CJpzFM literal 29 ZcmZQ@4hW6+40a8PH#0RbVnE?V0042#2dMx6 diff --git a/test/asm/cpudetect/cpudetect.s b/test/asm/cpudetect/cpudetect.s index d4d5b9f9f..cf2f5cb26 100644 --- a/test/asm/cpudetect/cpudetect.s +++ b/test/asm/cpudetect/cpudetect.s @@ -8,6 +8,10 @@ lda #$ea .endif +.ifp02X + lax #$ea +.endif + .ifpsc02 jmp ($1234,x) .endif @@ -80,3 +84,14 @@ .byte 0,"CPU_ISET_M740" .endif + +; step 3: switch through all supported cpus to verify the pseudo-op is there + +.p02 +.p02X +.psc02 +.pc02 +.p816 +.p4510 +.pdtv +.pm740 From ed86cb84f9cf4a8a73f94b5e8b37987f2751c434 Mon Sep 17 00:00:00 2001 From: mrdudz Date: Mon, 16 Jun 2025 23:10:49 +0200 Subject: [PATCH 08/26] slightly updated docs --- doc/ca65.sgml | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/doc/ca65.sgml b/doc/ca65.sgml index 80224a84e..4e449d8e5 100644 --- a/doc/ca65.sgml +++ b/doc/ca65.sgml @@ -152,7 +152,7 @@ Here is a description of all the command line options: Set the default for the CPU type. The option takes a parameter, which may be one of - 6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, sweet16, HuC6280, 4510 + 6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, sweet16, HuC6280, 4510, m740