From f333b300f1c542b952580420259f6d79db7977f1 Mon Sep 17 00:00:00 2001 From: Kugel Fuhr <98353208+kugelfuhr@users.noreply.github.com> Date: Tue, 1 Jul 2025 07:16:33 +0200 Subject: [PATCH] Added the CPU_HAS_BITIMM capability. --- doc/ca65.sgml | 3 ++ src/common/capability.c | 1 + src/common/capability.h | 1 + src/common/cpu.c | 81 ++++++++++++++++++++++------------------- 4 files changed, 48 insertions(+), 38 deletions(-) diff --git a/doc/ca65.sgml b/doc/ca65.sgml index 552309ff9..cfe73a2f0 100644 --- a/doc/ca65.sgml +++ b/doc/ca65.sgml @@ -1609,6 +1609,9 @@ either a string or an expression value. + CPU_HAS_BITIMM + Checks for the availability of the "bit #imm" instruction. + CPU_HAS_BRA8 Checks for the availability of a short (8 bit) branch. diff --git a/src/common/capability.c b/src/common/capability.c index f66205e7c..19c3ed838 100644 --- a/src/common/capability.c +++ b/src/common/capability.c @@ -50,6 +50,7 @@ struct Capability { capability_t Cap; } Capabilities [] = { /* BEGIN SORTED.SH */ + { "CPU_HAS_BITIMM", CAP_CPU_HAS_BITIMM }, { "CPU_HAS_BRA8", CAP_CPU_HAS_BRA8 }, { "CPU_HAS_INA", CAP_CPU_HAS_INA }, { "CPU_HAS_PUSHXY", CAP_CPU_HAS_PUSHXY }, diff --git a/src/common/capability.h b/src/common/capability.h index 011e2164f..b0332c72e 100644 --- a/src/common/capability.h +++ b/src/common/capability.h @@ -54,6 +54,7 @@ enum capability_t { CAP_CPU_HAS_PUSHXY = 2, /* CPU has PHX/PHY/PLX/PLY */ CAP_CPU_HAS_ZPIND = 3, /* CPU has "(zp)" mode (no offset) */ CAP_CPU_HAS_STZ = 4, /* CPU has "store zero" (!) instruction */ + CAP_CPU_HAS_BITIMM = 5, /* CPU has "bit #imm" instruction */ }; typedef enum capability_t capability_t; diff --git a/src/common/cpu.c b/src/common/cpu.c index cdc8e52cc..d8c0dbd37 100644 --- a/src/common/cpu.c +++ b/src/common/cpu.c @@ -96,54 +96,59 @@ const unsigned CPUIsets[CPU_COUNT] = { ** is deliberately hidden from the outside so it can be extended to 64 bit or ** even more. */ +#define CAP_BIT(Cap) (UINT32_C (1) << (Cap)) #define CAP_NONE UINT32_C (0) -#define CAP_6502 UINT32_C (0) -#define CAP_6502X UINT32_C (0) -#define CAP_6502DTV UINT32_C (0) +#define CAP_6502 CAP_NONE +#define CAP_6502X CAP_NONE +#define CAP_6502DTV CAP_NONE #define CAP_65SC02 \ - ((UINT32_C (1) << CAP_CPU_HAS_BRA8) | \ - (UINT32_C (1) << CAP_CPU_HAS_INA) | \ - (UINT32_C (1) << CAP_CPU_HAS_PUSHXY) | \ - (UINT32_C (1) << CAP_CPU_HAS_ZPIND) | \ - (UINT32_C (1) << CAP_CPU_HAS_STZ)) + (CAP_BIT (CAP_CPU_HAS_BITIMM) | \ + CAP_BIT (CAP_CPU_HAS_BRA8) | \ + CAP_BIT (CAP_CPU_HAS_INA) | \ + CAP_BIT (CAP_CPU_HAS_PUSHXY) | \ + CAP_BIT (CAP_CPU_HAS_ZPIND) | \ + CAP_BIT (CAP_CPU_HAS_STZ)) #define CAP_65C02 \ - ((UINT32_C (1) << CAP_CPU_HAS_BRA8) | \ - (UINT32_C (1) << CAP_CPU_HAS_INA) | \ - (UINT32_C (1) << CAP_CPU_HAS_PUSHXY) | \ - (UINT32_C (1) << CAP_CPU_HAS_ZPIND) | \ - (UINT32_C (1) << CAP_CPU_HAS_STZ)) + (CAP_BIT (CAP_CPU_HAS_BITIMM) | \ + CAP_BIT (CAP_CPU_HAS_BRA8) | \ + CAP_BIT (CAP_CPU_HAS_INA) | \ + CAP_BIT (CAP_CPU_HAS_PUSHXY) | \ + CAP_BIT (CAP_CPU_HAS_ZPIND) | \ + CAP_BIT (CAP_CPU_HAS_STZ)) #define CAP_65816 \ - ((UINT32_C (1) << CAP_CPU_HAS_BRA8) | \ - (UINT32_C (1) << CAP_CPU_HAS_INA) | \ - (UINT32_C (1) << CAP_CPU_HAS_PUSHXY) | \ - (UINT32_C (1) << CAP_CPU_HAS_ZPIND) | \ - (UINT32_C (1) << CAP_CPU_HAS_STZ)) -#define CAP_SWEET16 UINT32_C (0) + (CAP_BIT (CAP_CPU_HAS_BITIMM) | \ + CAP_BIT (CAP_CPU_HAS_BRA8) | \ + CAP_BIT (CAP_CPU_HAS_INA) | \ + CAP_BIT (CAP_CPU_HAS_PUSHXY) | \ + CAP_BIT (CAP_CPU_HAS_ZPIND) | \ + CAP_BIT (CAP_CPU_HAS_STZ)) +#define CAP_SWEET16 CAP_NONE #define CAP_HUC6280 \ - ((UINT32_C (1) << CAP_CPU_HAS_BRA8) | \ - (UINT32_C (1) << CAP_CPU_HAS_INA) | \ - (UINT32_C (1) << CAP_CPU_HAS_PUSHXY) | \ - (UINT32_C (1) << CAP_CPU_HAS_ZPIND) | \ - (UINT32_C (1) << CAP_CPU_HAS_STZ)) + (CAP_BIT (CAP_CPU_HAS_BITIMM) | \ + CAP_BIT (CAP_CPU_HAS_BRA8) | \ + CAP_BIT (CAP_CPU_HAS_INA) | \ + CAP_BIT (CAP_CPU_HAS_PUSHXY) | \ + CAP_BIT (CAP_CPU_HAS_ZPIND) | \ + CAP_BIT (CAP_CPU_HAS_STZ)) #define CAP_M740 \ - ((UINT32_C (1) << CAP_CPU_HAS_BRA8) | \ - (UINT32_C (1) << CAP_CPU_HAS_INA)) + (CAP_BIT (CAP_CPU_HAS_BRA8) | \ + CAP_BIT (CAP_CPU_HAS_INA)) #define CAP_4510 \ - ((UINT32_C (1) << CAP_CPU_HAS_BRA8) | \ - (UINT32_C (1) << CAP_CPU_HAS_INA) | \ - (UINT32_C (1) << CAP_CPU_HAS_PUSHXY)) + (CAP_BIT (CAP_CPU_HAS_BRA8) | \ + CAP_BIT (CAP_CPU_HAS_INA) | \ + CAP_BIT (CAP_CPU_HAS_PUSHXY)) #define CAP_45GS02 \ - ((UINT32_C (1) << CAP_CPU_HAS_BRA8) | \ - (UINT32_C (1) << CAP_CPU_HAS_INA) | \ - (UINT32_C (1) << CAP_CPU_HAS_PUSHXY)) + (CAP_BIT (CAP_CPU_HAS_BRA8) | \ + CAP_BIT (CAP_CPU_HAS_INA) | \ + CAP_BIT (CAP_CPU_HAS_PUSHXY)) #define CAP_W65C02 \ - ((UINT32_C (1) << CAP_CPU_HAS_BRA8) | \ - (UINT32_C (1) << CAP_CPU_HAS_INA) | \ - (UINT32_C (1) << CAP_CPU_HAS_PUSHXY)) + (CAP_BIT (CAP_CPU_HAS_BRA8) | \ + CAP_BIT (CAP_CPU_HAS_INA) | \ + CAP_BIT (CAP_CPU_HAS_PUSHXY)) #define CAP_65CE02 \ - ((UINT32_C (1) << CAP_CPU_HAS_BRA8) | \ - (UINT32_C (1) << CAP_CPU_HAS_INA) | \ - (UINT32_C (1) << CAP_CPU_HAS_PUSHXY)) + (CAP_BIT (CAP_CPU_HAS_BRA8) | \ + CAP_BIT (CAP_CPU_HAS_INA) | \ + CAP_BIT (CAP_CPU_HAS_PUSHXY)) /* Table containing one capability entry per CPU */ static const uint64_t CPUCaps[CPU_COUNT] = {