diff --git a/src/mem.rs b/src/mem.rs
index a43d333..e6bcf7c 100644
--- a/src/mem.rs
+++ b/src/mem.rs
@@ -658,7 +658,7 @@ impl<'a> CpuMem<'a> {
                         }
                     } else if (addr & 0x6000) >> 13 == 3 {
                         *cur_prg_bank = (val & 0x0F) as usize;
-                        println!("Updating ROM: new {:X}", val);
+                        // println!("Updating ROM: new {:X}", val);
                         match mode {
                             MMC1Mode::Full => {
                                 let bank0 = self.mem.cpu.find(SegmentId::PrgBank0).unwrap();
@@ -686,7 +686,7 @@ impl<'a> CpuMem<'a> {
                 } else {
                     *shift_reg = (*shift_reg >> 1) | ((val & 0x01) << 4);
                     *count += 1;
-                    println!("Mapper SHR {:05b}", *shift_reg);
+                    // println!("Mapper SHR {:05b}", *shift_reg);
                 }
             }
             _ => (),