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Added missing EXEHDR

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This commit is contained in:
Olli Savia
2024-04-02 19:25:15 +03:00
parent b993d88339
commit 074ec82126
3 changed files with 3 additions and 0 deletions
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1
cfg/vic20-asm-32k.cfg
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@@ -14,6 +14,7 @@ MEMORY {
SEGMENTS { SEGMENTS {
ZEROPAGE: load = ZP, type = zp, optional = yes; ZEROPAGE: load = ZP, type = zp, optional = yes;
LOADADDR: load = LOADADDR, type = ro; LOADADDR: load = LOADADDR, type = ro;
EXEHDR: load = MAIN, type = ro, optional = yes;
CODE: load = MAIN, type = ro; CODE: load = MAIN, type = ro;
RODATA: load = MAIN, type = ro; RODATA: load = MAIN, type = ro;
DATA: load = MAIN, type = rw; DATA: load = MAIN, type = rw;

1
cfg/vic20-asm-3k.cfg
View File

@@ -14,6 +14,7 @@ MEMORY {
SEGMENTS { SEGMENTS {
ZEROPAGE: load = ZP, type = zp, optional = yes; ZEROPAGE: load = ZP, type = zp, optional = yes;
LOADADDR: load = LOADADDR, type = ro; LOADADDR: load = LOADADDR, type = ro;
EXEHDR: load = MAIN, type = ro, optional = yes;
CODE: load = MAIN, type = ro; CODE: load = MAIN, type = ro;
RODATA: load = MAIN, type = ro; RODATA: load = MAIN, type = ro;
DATA: load = MAIN, type = rw; DATA: load = MAIN, type = rw;

1
cfg/vic20-asm.cfg
View File

@@ -14,6 +14,7 @@ MEMORY {
SEGMENTS { SEGMENTS {
ZEROPAGE: load = ZP, type = zp, optional = yes; ZEROPAGE: load = ZP, type = zp, optional = yes;
LOADADDR: load = LOADADDR, type = ro; LOADADDR: load = LOADADDR, type = ro;
EXEHDR: load = MAIN, type = ro, optional = yes;
CODE: load = MAIN, type = ro; CODE: load = MAIN, type = ro;
RODATA: load = MAIN, type = ro; RODATA: load = MAIN, type = ro;
DATA: load = MAIN, type = rw; DATA: load = MAIN, type = rw;