more m740 fixes, makes the regression test work
This commit is contained in:
mrdudz
@@ -186,10 +186,11 @@ void GetEA (EffAddr* A)
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/* Remaining stuff:
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**
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** adr
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** adr,x
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** adr,y
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** adr,s
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** addr
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** addr, x
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** addr, y
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** addr, s
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** addr, relative addr
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*/
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A->Expr = Expression ();
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229
src/ca65/instr.c
229
src/ca65/instr.c
@@ -138,6 +138,11 @@ static void PutJSR816 (const InsDesc* Ins);
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** Allowing the long_jsr_jmp_rts feature to permit a long JSR.
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*/
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static void PutJSR_m740 (const InsDesc* Ins);
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/* Handle the JSR instruction for the m740
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** Allowing the special page feature.
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*/
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static void PutRTS (const InsDesc* Ins attribute ((unused)));
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/* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if
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** the enclosing scope is FAR, but only if the long_jsr_jmp_rts feature applies.
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@@ -1053,6 +1058,9 @@ static const struct {
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}
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};
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/* CAUTION: in the pdf $1a is dec a, and $3a is inc a - if that is really the case,
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* the table below (and the handler) should be fixed and this notice removed */
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/* Instruction table for the m740 CPU */
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static const struct {
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unsigned Count;
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@@ -1091,82 +1099,82 @@ static const struct {
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{ "BRK", 0x00000001, 0x00, 0, PutAll },
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{ "BVC", 0x00020000, 0x50, 0, PutPCRel8 },
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{ "BVS", 0x00020000, 0x70, 0, PutPCRel8 },
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{ "CLB0", 0x0000006, 0x1b, 10, PutAll },
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{ "CLB1", 0x0000006, 0x3b, 10, PutAll },
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{ "CLB2", 0x0000006, 0x5b, 10, PutAll },
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{ "CLB3", 0x0000006, 0x7b, 10, PutAll },
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{ "CLB4", 0x0000006, 0x9b, 10, PutAll },
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{ "CLB5", 0x0000006, 0xbb, 10, PutAll },
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{ "CLB6", 0x0000006, 0xdb, 10, PutAll },
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{ "CLB7", 0x0000006, 0xfb, 10, PutAll },
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{ "CLC", 0x0000001, 0x18, 0, PutAll },
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{ "CLD", 0x0000001, 0xd8, 0, PutAll },
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{ "CLI", 0x0000001, 0x58, 0, PutAll },
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{ "CLT", 0x0000001, 0x12, 0, PutAll },
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{ "CLV", 0x0000001, 0xb8, 0, PutAll },
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{ "CMP", 0x080A26C, 0xc0, 0, PutAll },
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{ "COM", 0x0000004, 0x44, 1, PutAll },
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{ "CPX", 0x080000C, 0xe0, 1, PutAll },
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{ "CPY", 0x080000C, 0xc0, 1, PutAll },
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{ "DEC", 0x000006F, 0x00, 3, PutAll },
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{ "DEX", 0x0000001, 0xca, 0, PutAll },
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{ "DEY", 0x0000001, 0x88, 0, PutAll },
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{ "EOR", 0x080A26C, 0x40, 0, PutAll },
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{ "FST", 0x0000001, 0xe2, 0, PutAll },
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{ "INC", 0x000006f, 0x00, 4, PutAll },
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{ "INX", 0x0000001, 0xe8, 0, PutAll },
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{ "INY", 0x0000001, 0xc8, 0, PutAll },
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{ "JMP", 0x0000C08, 0x00, 12, PutAll },
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{ "JSR", 0x0080808, 0x00, 13, PutAll },
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{ "LDA", 0x080A26C, 0xa0, 0, PutAll },
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{ "CLB0", 0x00000006, 0x1b, 10, PutAll },
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{ "CLB1", 0x00000006, 0x3b, 10, PutAll },
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{ "CLB2", 0x00000006, 0x5b, 10, PutAll },
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{ "CLB3", 0x00000006, 0x7b, 10, PutAll },
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{ "CLB4", 0x00000006, 0x9b, 10, PutAll },
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{ "CLB5", 0x00000006, 0xbb, 10, PutAll },
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{ "CLB6", 0x00000006, 0xdb, 10, PutAll },
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{ "CLB7", 0x00000006, 0xfb, 10, PutAll },
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{ "CLC", 0x00000001, 0x18, 0, PutAll },
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{ "CLD", 0x00000001, 0xd8, 0, PutAll },
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{ "CLI", 0x00000001, 0x58, 0, PutAll },
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{ "CLT", 0x00000001, 0x12, 0, PutAll },
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{ "CLV", 0x00000001, 0xb8, 0, PutAll },
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{ "CMP", 0x0080A26C, 0xc0, 0, PutAll },
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{ "COM", 0x00000004, 0x44, 1, PutAll },
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{ "CPX", 0x0080000C, 0xe0, 1, PutAll },
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{ "CPY", 0x0080000C, 0xc0, 1, PutAll },
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{ "DEC", 0x0000006F, 0x00, 3, PutAll },
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{ "DEX", 0x00000001, 0xca, 0, PutAll },
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{ "DEY", 0x00000001, 0x88, 0, PutAll },
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{ "EOR", 0x0080A26C, 0x40, 0, PutAll },
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{ "FST", 0x00000001, 0xe2, 0, PutAll },
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{ "INC", 0x0000006f, 0x00, 4, PutAll },
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{ "INX", 0x00000001, 0xe8, 0, PutAll },
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{ "INY", 0x00000001, 0xc8, 0, PutAll },
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{ "JMP", 0x00000C08, 0x00, 12, PutAll },
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{ "JSR", 0x20000408, 0x00, 13, PutJSR_m740 },
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{ "LDA", 0x0080A26C, 0xa0, 0, PutAll },
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{ "LDM", 0x10000000, 0x3c, 0, PutLDM_m740 },
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{ "LDX", 0x080030C, 0xa2, 1, PutAll },
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{ "LDY", 0x080006C, 0xa0, 1, PutAll },
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{ "LSR", 0x000006F, 0x42, 1, PutAll },
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{ "NOP", 0x0000001, 0xea, 0, PutAll },
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{ "ORA", 0x080A26C, 0x00, 0, PutAll },
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{ "PHA", 0x0000001, 0x48, 0, PutAll },
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{ "PHP", 0x0000001, 0x08, 0, PutAll },
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{ "PLA", 0x0000001, 0x68, 0, PutAll },
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{ "PLP", 0x0000001, 0x28, 0, PutAll },
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{ "RMB0", 0x0000006, 0x1b, 10, PutAll },
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{ "RMB1", 0x0000006, 0x3b, 10, PutAll },
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{ "RMB2", 0x0000006, 0x5b, 10, PutAll },
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{ "RMB3", 0x0000006, 0x7b, 10, PutAll },
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{ "RMB4", 0x0000006, 0x9b, 10, PutAll },
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{ "RMB5", 0x0000006, 0xbb, 10, PutAll },
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{ "RMB6", 0x0000006, 0xdb, 10, PutAll },
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{ "RMB7", 0x0000006, 0xfb, 10, PutAll },
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{ "ROL", 0x000006F, 0x22, 1, PutAll },
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{ "ROR", 0x000006F, 0x62, 1, PutAll },
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{ "RRF", 0x0000004, 0x82, 6, PutAll },
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{ "RTI", 0x0000001, 0x40, 0, PutAll },
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{ "RTS", 0x0000001, 0x60, 0, PutAll },
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{ "SBC", 0x080A26C, 0xe0, 0, PutAll },
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{ "SEB0", 0x0000006, 0x0b, 10, PutAll },
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{ "SEB1", 0x0000006, 0x2b, 10, PutAll },
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{ "SEB2", 0x0000006, 0x4b, 10, PutAll },
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{ "SEB3", 0x0000006, 0x6b, 10, PutAll },
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{ "SEB4", 0x0000006, 0x8b, 10, PutAll },
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{ "SEB5", 0x0000006, 0xab, 10, PutAll },
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{ "SEB6", 0x0000006, 0xcb, 10, PutAll },
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{ "SEB7", 0x0000006, 0xeb, 10, PutAll },
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{ "SEC", 0x0000001, 0x38, 0, PutAll },
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{ "SED", 0x0000001, 0xf8, 0, PutAll },
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{ "SEI", 0x0000001, 0x78, 0, PutAll },
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{ "SET", 0x0000001, 0x32, 0, PutAll },
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{ "SLW", 0x0000001, 0xC2, 0, PutAll },
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{ "STA", 0x000A26C, 0x80, 0, PutAll },
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{ "STP", 0x0000001, 0x42, 0, PutAll },
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{ "STX", 0x000010c, 0x82, 1, PutAll },
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{ "STY", 0x000002c, 0x80, 1, PutAll },
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{ "TAX", 0x0000001, 0xaa, 0, PutAll },
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{ "TAY", 0x0000001, 0xa8, 0, PutAll },
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{ "TST", 0x0000004, 0x64, 0, PutAll },
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{ "TSX", 0x0000001, 0xba, 0, PutAll },
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{ "TXA", 0x0000001, 0x8a, 0, PutAll },
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{ "TXS", 0x0000001, 0x9a, 0, PutAll },
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{ "TYA", 0x0000001, 0x98, 0, PutAll }
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{ "LDX", 0x0080030C, 0xa2, 1, PutAll },
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{ "LDY", 0x0080006C, 0xa0, 1, PutAll },
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{ "LSR", 0x0000006F, 0x42, 1, PutAll },
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{ "NOP", 0x00000001, 0xea, 0, PutAll },
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{ "ORA", 0x0080A26C, 0x00, 0, PutAll },
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{ "PHA", 0x00000001, 0x48, 0, PutAll },
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{ "PHP", 0x00000001, 0x08, 0, PutAll },
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{ "PLA", 0x00000001, 0x68, 0, PutAll },
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{ "PLP", 0x00000001, 0x28, 0, PutAll },
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{ "RMB0", 0x00000006, 0x1b, 10, PutAll },
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{ "RMB1", 0x00000006, 0x3b, 10, PutAll },
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{ "RMB2", 0x00000006, 0x5b, 10, PutAll },
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{ "RMB3", 0x00000006, 0x7b, 10, PutAll },
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{ "RMB4", 0x00000006, 0x9b, 10, PutAll },
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{ "RMB5", 0x00000006, 0xbb, 10, PutAll },
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{ "RMB6", 0x00000006, 0xdb, 10, PutAll },
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{ "RMB7", 0x00000006, 0xfb, 10, PutAll },
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{ "ROL", 0x0000006F, 0x22, 1, PutAll },
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{ "ROR", 0x0000006F, 0x62, 1, PutAll },
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{ "RRF", 0x00000004, 0x82, 6, PutAll },
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{ "RTI", 0x00000001, 0x40, 0, PutAll },
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{ "RTS", 0x00000001, 0x60, 0, PutAll },
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{ "SBC", 0x0080A26C, 0xe0, 0, PutAll },
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{ "SEB0", 0x00000006, 0x0b, 10, PutAll },
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{ "SEB1", 0x00000006, 0x2b, 10, PutAll },
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{ "SEB2", 0x00000006, 0x4b, 10, PutAll },
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{ "SEB3", 0x00000006, 0x6b, 10, PutAll },
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{ "SEB4", 0x00000006, 0x8b, 10, PutAll },
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{ "SEB5", 0x00000006, 0xab, 10, PutAll },
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{ "SEB6", 0x00000006, 0xcb, 10, PutAll },
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{ "SEB7", 0x00000006, 0xeb, 10, PutAll },
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{ "SEC", 0x00000001, 0x38, 0, PutAll },
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{ "SED", 0x00000001, 0xf8, 0, PutAll },
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{ "SEI", 0x00000001, 0x78, 0, PutAll },
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{ "SET", 0x00000001, 0x32, 0, PutAll },
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{ "SLW", 0x00000001, 0xC2, 0, PutAll },
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{ "STA", 0x0000A26C, 0x80, 0, PutAll },
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{ "STP", 0x00000001, 0x42, 0, PutAll },
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{ "STX", 0x0000010c, 0x82, 1, PutAll },
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{ "STY", 0x0000002c, 0x80, 1, PutAll },
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{ "TAX", 0x00000001, 0xaa, 0, PutAll },
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{ "TAY", 0x00000001, 0xa8, 0, PutAll },
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{ "TST", 0x00000004, 0x64, 1, PutAll },
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{ "TSX", 0x00000001, 0xba, 0, PutAll },
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{ "TXA", 0x00000001, 0x8a, 0, PutAll },
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{ "TXS", 0x00000001, 0x9a, 0, PutAll },
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{ "TYA", 0x00000001, 0x98, 0, PutAll }
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/* END SORTED.SH */
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}
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};
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@@ -1197,43 +1205,43 @@ static unsigned char EATab[14][AM65I_COUNT] = {
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0x00, 0x00, 0x00, 0x03, 0x13, 0x09, 0x00, 0x09,
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0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 1 */
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{ /* Table 1 (rol, ror, stx, sty) */
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0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
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0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x80, 0x00
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},
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{ /* Table 2 */
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{ /* Table 2 (bit) */
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0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 3 */
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{ /* Table 3 (dec, dea) */
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0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 4 */
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{ /* Table 4 (inc) */
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0x1A, 0x1A, 0xE6, 0xEE, 0x00, 0xF6, 0xFE, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 5 */
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{ /* Table 5 (stz) */
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0x00, 0x00, 0x60, 0x98, 0x00, 0x70, 0x9E, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 6 */
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{ /* Table 6 (jmp) */
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0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
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0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x90, 0x00
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},
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{ /* Table 7 (Subroutine opcodes) */
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{ /* Table 7 (Subroutine opcodes) (jsr) */
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0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
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0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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@@ -1245,7 +1253,7 @@ static unsigned char EATab[14][AM65I_COUNT] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00
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},
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{ /* Table 9 */
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{ /* Table 9 (dew, inw) */
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0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x30, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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@@ -1644,7 +1652,7 @@ static void PutBitBranch_m740 (const InsDesc* Ins)
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/* Accu */
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Emit0 (A.Opcode);
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ConsumeComma ();
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EmitSigned (GenBranchExpr (1), 1);
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EmitSigned (GenBranchExpr (2), 1);
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} else if (A.AddrModeSet == 0x10000000) {
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A.Opcode += 0x04;
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/* Zeropage */
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@@ -1870,6 +1878,59 @@ static void PutJSR816 (const InsDesc* Ins)
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}
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static void PutJSR_m740 (const InsDesc* Ins)
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/* Handle a JSR instruction for m740 */
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{
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EffAddr A;
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/* Evaluate the addressing mode used */
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GetEA (&A);
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/* From the possible addressing modes, remove the ones that are invalid
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** for this instruction or CPU.
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*/
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A.AddrModeSet &= Ins->AddrMode;
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/* Check if we have any adressing modes left */
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if (A.AddrModeSet == 0) {
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Error ("Illegal addressing mode");
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return;
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}
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A.AddrMode = BitFind (A.AddrModeSet);
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A.AddrModeBit = (0x01UL << A.AddrMode);
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/* Build the opcode */
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/* A.Opcode = Ins->BaseCode | EATab[Ins->ExtCode][A.AddrMode] | A.Reg; */
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A.Opcode = Ins->BaseCode;
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switch (A.AddrMode) {
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case AM65I_DIR_IND:
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A.Opcode = 0x02;
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Emit1 (A.Opcode, A.Expr);
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break;
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case AM65I_ABS:
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/* If we have an expression and it's const, get it's value */
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if (A.Expr) {
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long Val = -1;
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if (IsConstExpr (A.Expr, &Val)) {
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if ((Val & 0xff00) == 0xff00) {
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/* direct page */
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A.Opcode = 0x22;
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Emit0 (A.Opcode);
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EmitByte(GenByteExpr(A.Expr));
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return;
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}
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}
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}
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A.Opcode = 0x20;
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Emit2 (A.Opcode, A.Expr);
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break;
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default:
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Internal ("Invalid Opcode 0x%02x", A.Opcode);
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}
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}
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static void PutRTS (const InsDesc* Ins attribute ((unused)))
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/* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if
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@@ -68,8 +68,8 @@
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#define AM65_ABS_LONG_X 0x00000080UL /* -- */
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#define AM65_DIR_Y 0x00000100UL /* ZP, Y */
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#define AM65_ABS_Y 0x00000200UL /* ABS, Y */
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#define AM65_DIR_IND 0x00000400UL /* ZP, IND */
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#define AM65_ABS_IND 0x00000800UL /* IND */
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#define AM65_DIR_IND 0x00000400UL /* (ZP IND) */
|
||||
#define AM65_ABS_IND 0x00000800UL /* (IND) */
|
||||
#define AM65_DIR_IND_LONG 0x00001000UL /* -- */
|
||||
#define AM65_DIR_IND_Y 0x00002000UL /* IND, Y */
|
||||
#define AM65_DIR_IND_LONG_Y 0x00004000UL /* -- */
|
||||
@@ -87,40 +87,55 @@
|
||||
#define AM65_ABS_IND_LONG 0x04000000UL /* -- */
|
||||
#define AM65_IMM_IMPLICIT_WORD 0x08000000UL /* PHW #$1234 (4510 only) */
|
||||
#define AM65_ZP_REL 0x10000000UL /* ZP, REL (m740) */
|
||||
#define AM65_SPECIAL_PAGE 0x20000000UL /* $FFxx (m740) */
|
||||
|
||||
|
||||
|
||||
/* Bitmask for all ZP operations that have correspondent ABS ops */
|
||||
/* $8524 */
|
||||
#define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
|
||||
/*$4 $20 $100 $400 $8000 */
|
||||
/* Bitmask for all ABS operations that have correspondent FAR ops */
|
||||
/* $48 */
|
||||
#define AM65_SET_ABS (AM65_ABS | AM65_ABS_X)
|
||||
/* $8 $40 */
|
||||
/* Bitmask for all ZP operations */
|
||||
/* $8524 */
|
||||
#define AM65_ALL_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
|
||||
/*$4 $20 $100 $400 $8000 */
|
||||
/* Bitmask for all ABS operations */
|
||||
/* $10a48 */
|
||||
#define AM65_ALL_ABS (AM65_ABS | AM65_ABS_X | AM65_ABS_Y | AM65_ABS_IND | AM65_ABS_X_IND)
|
||||
/* $8 $40 $200 $800 $10000 */
|
||||
/* Bitmask for all FAR operations */
|
||||
/* $90 */
|
||||
#define AM65_ALL_FAR (AM65_ABS_LONG | AM65_ABS_LONG_X)
|
||||
/* $10 $80 */
|
||||
|
||||
/* Bitmask for all immediate operations */
|
||||
/* $8e00 000 */
|
||||
#define AM65_ALL_IMM (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT | AM65_IMM_IMPLICIT_WORD)
|
||||
/* $200000 $400000 $800000 $8000000 */
|
||||
|
||||
/* Bit numbers and count */
|
||||
#define AM65I_IMM_ACCU 21
|
||||
#define AM65I_IMM_INDEX 22
|
||||
#define AM65I_IMM_IMPLICIT 23
|
||||
#define AM65I_IMM_IMPLICIT_WORD 27
|
||||
#define AM65I_COUNT 28
|
||||
#define AM65I_IMPLICIT 0
|
||||
#define AM65I_ACCU 1
|
||||
#define AM65I_DIR 2
|
||||
#define AM65I_ABS 3
|
||||
#define AM65I_ABS_LONG 4
|
||||
#define AM65I_DIR_X 5
|
||||
#define AM65I_ABS_X 6
|
||||
#define AM65I_ABS_LONG_X 7
|
||||
#define AM65I_DIR_Y 8
|
||||
#define AM65I_ABS_Y 9
|
||||
#define AM65I_DIR_IND 10
|
||||
#define AM65I_ABS_IND 11
|
||||
#define AM65I_DIR_IND_LONG 12
|
||||
#define AM65I_DIR_IND_Y 13
|
||||
#define AM65I_DIR_IND_LONG_Y 14
|
||||
#define AM65I_DIR_X_IND 15
|
||||
#define AM65I_ABS_X_IND 16
|
||||
#define AM65I_REL 17
|
||||
#define AM65I_REL_LONG 18
|
||||
#define AM65I_STACK_REL 19
|
||||
#define AM65I_STACK_REL_IND_Y 20
|
||||
#define AM65I_IMM_ACCU 21
|
||||
#define AM65I_IMM_INDEX 22
|
||||
#define AM65I_IMM_IMPLICIT 23
|
||||
#define AM65I_BLOCKMOVE 24
|
||||
#define AM65I_BLOCKXFER 25
|
||||
#define AM65I_ABS_IND_LONG 26
|
||||
#define AM65I_IMM_IMPLICIT_WORD 27
|
||||
#define AM65I_ZP_REL 28
|
||||
#define AM65I_SPECIAL_PAGE 29
|
||||
#define AM65I_COUNT 30
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -795,14 +795,14 @@ void OH_JmpDirectIndirect (const OpcDesc* D)
|
||||
|
||||
void OH_SpecialPage (const OpcDesc* D)
|
||||
{
|
||||
/* Get the operand */
|
||||
unsigned Addr = 0xFF00 + GetCodeByte (PC+1);
|
||||
/* Get the operand */
|
||||
unsigned Addr = 0xFF00 + GetCodeByte (PC+1);
|
||||
|
||||
/* Generate a label in pass 1 */
|
||||
GenerateLabel (D->Flags, Addr);
|
||||
/* Generate a label in pass 1 */
|
||||
GenerateLabel (D->Flags, Addr);
|
||||
|
||||
/* OneLine (D, "$FF%02X", (CodeByte (PC+1)); */
|
||||
OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
|
||||
/* OneLine (D, "$FF%02X", (CodeByte (PC+1)); */
|
||||
OneLine (D, "%s", GetAddrArg (D->Flags, Addr));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -44,7 +44,8 @@
|
||||
/* Data */
|
||||
/*****************************************************************************/
|
||||
|
||||
|
||||
/* CAUTION: in the pdf $1a is dec, and $3a is inc - if that is really the case,
|
||||
* the table below should be fixed and this notice removed */
|
||||
|
||||
/* Descriptions for all opcodes */
|
||||
const OpcDesc OpcTable_M740[256] = {
|
||||
@@ -74,7 +75,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "bbc0", 3, flUseLabel, OH_BitBranch_m740 }, /* $17 */
|
||||
{ "clc", 1, flNone, OH_Implicit }, /* $18 */
|
||||
{ "ora", 3, flUseLabel, OH_AbsoluteY }, /* $19 */
|
||||
{ "dec", 1, flNone, OH_Accumulator }, /* $1a */
|
||||
{ "inc", 1, flNone, OH_Accumulator }, /* $1a */
|
||||
{ "clb0", 1, flNone, OH_AccumulatorBit }, /* $1b */
|
||||
{ "", 1, flIllegal, OH_Illegal }, /* $1c */
|
||||
{ "ora", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $1d */
|
||||
@@ -106,7 +107,7 @@ const OpcDesc OpcTable_M740[256] = {
|
||||
{ "bbc1", 3, flUseLabel, OH_BitBranch_m740 }, /* $37 */
|
||||
{ "sec", 1, flNone, OH_Implicit }, /* $38 */
|
||||
{ "and", 3, flUseLabel, OH_AbsoluteY }, /* $39 */
|
||||
{ "inc", 1, flNone, OH_Accumulator }, /* $3a */
|
||||
{ "dec", 1, flNone, OH_Accumulator }, /* $3a */
|
||||
{ "clb1", 1, flNone, OH_AccumulatorBit }, /* $3b */
|
||||
{ "ldm", 3, flLabel, OH_DirectImmediate }, /* $3c */
|
||||
{ "and", 3, flUseLabel|flAbsOverride, OH_AbsoluteX }, /* $3d */
|
||||
|
||||
Reference in New Issue
Block a user