Reorganized test/asm

test/asm/cpudetect/Makefile

@@ -0,0 +1,61 @@
+# Makefile for the assembler regression tests
+
+ifneq ($(shell echo),)
+  CMD_EXE = 1
+endif
+
+ifdef CMD_EXE
+  EXE = .exe
+  MKDIR = mkdir $(subst /,\,$1)
+  RMDIR = -rmdir /q /s $(subst /,\,$1)
+else
+  EXE =
+  MKDIR = mkdir -p $1
+  RMDIR = $(RM) -r $1
+endif
+
+ifdef QUIET
+  .SILENT:
+endif
+
+CA65 := $(if $(wildcard ../../../bin/ca65*),../../../bin/ca65,ca65)
+LD65 := $(if $(wildcard ../../../bin/ld65*),../../../bin/ld65,ld65)
+
+WORKDIR = ../../../testwrk/asm/cpudetect
+
+ISEQUAL = ../../../testwrk/isequal$(EXE)
+
+CC = gcc
+CFLAGS = -O2
+
+.PHONY: all clean
+
+CPUDETECT_REFS := $(wildcard *-cpudetect.ref)
+CPUDETECT_BINS = $(CPUDETECT_REFS:%.ref=$(WORKDIR)/%.bin)
+CPUDETECT_CPUS = $(CPUDETECT_REFS:%-cpudetect.ref=%)
+
+all: $(CPUDETECT_BINS)
+
+$(WORKDIR):
+	$(call MKDIR,$(WORKDIR))
+
+$(ISEQUAL): ../../isequal.c | $(WORKDIR)
+	$(CC) $(CFLAGS) -o $@ $<
+
+define CPUDETECT_template
+
+$(WORKDIR)/$1-cpudetect.bin: cpudetect.s $1-cpudetect.ref $(ISEQUAL)
+	$(if $(QUIET),echo asm/$1-cpudetect.bin)
+	$(CA65) -t none --cpu $1 -l $$(@:.bin=.lst) -o $$(@:.bin=.o) $$<
+	$(LD65) -t none -o $$@ $$(@:.bin=.o) none.lib
+	$(ISEQUAL) $1-cpudetect.ref $$@
+
+endef # CPUDETECT_template
+
+$(foreach cpu,$(CPUDETECT_CPUS),$(eval $(call CPUDETECT_template,$(cpu))))
+
+$(WORKDIR)/%.o: %.s | $(WORKDIR)
+	$(CA65) -l $(@:.o=.lst) -o $@ $<
+
+clean:
+	@$(call RMDIR,$(WORKDIR))

test/asm/cpudetect/cpudetect.s

@@ -0,0 +1,74 @@
+
+.macpack cpu
+
+; step 1: try to assemble an instruction that's exclusive to this set
+;         (when possible)
+
+.ifp02
+   lda #$ea
+.endif
+
+.ifpsc02
+   jmp ($1234,x)
+.endif
+
+.ifpc02
+   rmb0 $12
+.endif
+
+.ifp816
+   xba
+.endif
+
+.ifp4510
+   taz
+.endif
+
+.ifpdtv
+   sac #$00
+.endif
+
+
+; step 2: check for bitwise compatibility of instructions sets
+;         (made verbose for better reading with hexdump/hd(1))
+
+.if (.cpu .bitand CPU_ISET_NONE)
+   .byte 0,"CPU_ISET_NONE"
+.endif
+
+.if (.cpu .bitand CPU_ISET_6502)
+   .byte 0,"CPU_ISET_6502"
+.endif
+
+.if (.cpu .bitand CPU_ISET_6502X)
+   .byte 0,"CPU_ISET_6502X"
+.endif
+
+.if (.cpu .bitand CPU_ISET_65SC02)
+   .byte 0,"CPU_ISET_65SC02"
+.endif
+
+.if (.cpu .bitand CPU_ISET_65C02)
+   .byte 0,"CPU_ISET_65C02"
+.endif
+
+.if (.cpu .bitand CPU_ISET_65816)
+   .byte 0,"CPU_ISET_65816"
+.endif
+
+.if (.cpu .bitand CPU_ISET_SWEET16)
+   .byte 0,"CPU_ISET_SWEET16"
+.endif
+
+.if (.cpu .bitand CPU_ISET_HUC6280)
+   .byte 0,"CPU_ISET_HUC6280"
+.endif
+
+.if (.cpu .bitand CPU_ISET_4510)
+   .byte 0,"CPU_ISET_4510"
+.endif
+
+.if (.cpu .bitand CPU_ISET_6502DTV)
+   .byte 0,"CPU_ISET_6502DTV"
+.endif
+