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Updated the cx16 library to the Commander X16 Kernal's prerelease 35.

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This commit is contained in:
Greg King
2019-12-25 10:56:32 -05:00
parent cab4910a7d
commit 3fa253d31f
31 changed files with 508 additions and 271 deletions
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2
cfg/cx16-asm.cfg
View File

@@ -6,7 +6,7 @@ SYMBOLS {
__HIMEM__: type = weak, value = $9F00;
}
MEMORY {
ZP: file = "", start = $0002, size = $0080 - $0002, define = yes;
ZP: file = "", start = $0022, size = $0080 - $0022, define = yes;
LOADADDR: file = %O, start = %S - 2, size = $0002;
MAIN: file = %O, start = %S, size = __HIMEM__ - %S;
}

10
cfg/cx16-bank.cfg
View File

@@ -11,13 +11,13 @@ SYMBOLS {
__BANKRAMSIZE__: type = weak, value = $2000; # 8K banked RAM
}
MEMORY {
ZP: file = "", define = yes, start = $0002, size = $0080 - $0002;
ZP: file = "", define = yes, start = $0022, size = $0080 - $0022;
LOADADDR: file = %O, start = %S - 2, size = $0002;
HEADER: file = %O, define = yes, start = %S, size = $000D;
MAIN: file = %O, define = yes, start = __HEADER_LAST__, size = __HIMEM__ - __HEADER_LAST__;
BSS: file = "", start = __ONCE_RUN__, size = __HIMEM__ - __ONCE_RUN__ - __STACKSIZE__;
BRAM00ADDR: file = "%O.00", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM00: file = "%O.00", start = __BANKRAMSTART__, size = __BANKRAMSIZE__;
# BRAM00ADDR: file = "%O.00", start = __BANKRAMSTART__ - 2, size = $0002;
# BRAM00: file = "%O.00", start = __BANKRAMSTART__, size = __BANKRAMSIZE__;
BRAM01ADDR: file = "%O.01", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM01: file = "%O.01", start = __BANKRAMSTART__, size = __BANKRAMSIZE__;
BRAM02ADDR: file = "%O.02", start = __BANKRAMSTART__ - 2, size = $0002;
@@ -62,8 +62,8 @@ SEGMENTS {
INIT: load = MAIN, type = rw;
ONCE: load = MAIN, type = ro, define = yes;
BSS: load = BSS, type = bss, define = yes;
BRAM00ADDR: load = BRAM00ADDR, type = ro, optional = yes;
BANKRAM00: load = BRAM00, type = rw, define = yes, optional = yes;
# BRAM00ADDR: load = BRAM00ADDR, type = ro, optional = yes;
# BANKRAM00: load = BRAM00, type = rw, define = yes, optional = yes;
BRAM01ADDR: load = BRAM01ADDR, type = ro, optional = yes;
BANKRAM01: load = BRAM01, type = rw, define = yes, optional = yes;
BRAM02ADDR: load = BRAM02ADDR, type = ro, optional = yes;

2
cfg/cx16.cfg
View File

@@ -8,7 +8,7 @@ SYMBOLS {
__HIMEM__: type = weak, value = $9F00;
}
MEMORY {
ZP: file = "", define = yes, start = $0002, size = $0080 - $0002;
ZP: file = "", define = yes, start = $0022, size = $0080 - $0022;
LOADADDR: file = %O, start = %S - 2, size = $0002;
HEADER: file = %O, define = yes, start = %S, size = $000D;
MAIN: file = %O, define = yes, start = __HEADER_LAST__, size = __HIMEM__ - __HEADER_LAST__;