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Polishing the peripherals (and counter) interface.

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This commit is contained in:
sidney
2024-12-19 03:48:15 +01:00
parent 8a7cd9c632
commit 5239d3a11b
5 changed files with 117 additions and 102 deletions
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82
src/sim65/peripherals.h
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@@ -35,44 +35,64 @@
#include <stdint.h>
#define PERIPHERALS_APERTURE_BASE_ADDRESS 0xffc0
#define PERIPHERALS_APERTURE_LAST_ADDRESS 0xffc9
/* The memory range where the memory-mapped peripherals can be accessed. */
#define PERIPHERALS_ADDRESS_OFFSET_LATCH 0x00
#define PERIPHERALS_ADDRESS_OFFSET_SELECT 0x01
#define PERIPHERALS_ADDRESS_OFFSET_REG64 0x02
#define PERIPHERALS_APERTURE_BASE_ADDRESS 0xffc0
#define PERIPHERALS_APERTURE_LAST_ADDRESS 0xffc9
#define PERIPHERALS_LATCH (PERIPHERALS_APERTURE_BASE_ADDRESS + PERIPHERALS_ADDRESS_OFFSET_LATCH)
#define PERIPHERALS_SELECT (PERIPHERALS_APERTURE_BASE_ADDRESS + PERIPHERALS_ADDRESS_OFFSET_SELECT)
#define PERIPHERALS_REG64 (PERIPHERALS_APERTURE_BASE_ADDRESS + PERIPHERALS_ADDRESS_OFFSET_REG64)
/* Declarations for the COUNTER peripheral (currently the only peripheral). */
#define PERIPHERALS_REG64_SELECT_CLOCKCYCLE_COUNTER 0x00
#define PERIPHERALS_REG64_SELECT_INSTRUCTION_COUNTER 0x01
#define PERIPHERALS_REG64_SELECT_IRQ_COUNTER 0x02
#define PERIPHERALS_REG64_SELECT_NMI_COUNTER 0x03
#define PERIPHERALS_REG64_SELECT_WALLCLOCK_TIME 0x80
#define PERIPHERALS_COUNTER_ADDRESS_OFFSET_LATCH 0x00
#define PERIPHERALS_COUNTER_ADDRESS_OFFSET_SELECT 0x01
#define PERIPHERALS_COUNTER_ADDRESS_OFFSET_VALUE 0x02
#define PERIPHERALS_COUNTER_LATCH (PERIPHERALS_APERTURE_BASE_ADDRESS + PERIPHERALS_ADDRESS_OFFSET_COUNTER_LATCH)
#define PERIPHERALS_COUNTER_SELECT (PERIPHERALS_APERTURE_BASE_ADDRESS + PERIPHERALS_ADDRESS_OFFSET_COUNTER_SELECT)
#define PERIPHERALS_COUNTER_VALUE (PERIPHERALS_APERTURE_BASE_ADDRESS + PERIPHERALS_ADDRESS_OFFSET_COUNTER)
#define PERIPHERALS_COUNTER_SELECT_CLOCKCYCLE_COUNTER 0x00
#define PERIPHERALS_COUNTER_SELECT_INSTRUCTION_COUNTER 0x01
#define PERIPHERALS_COUNTER_SELECT_IRQ_COUNTER 0x02
#define PERIPHERALS_COUNTER_SELECT_NMI_COUNTER 0x03
#define PERIPHERALS_COUNTER_SELECT_WALLCLOCK_TIME 0x80
#define PERIPHERALS_COUNTER_SELECT_WALLCLOCK_TIME_SPLIT 0x81
typedef struct {
/* the invisible counters that are continuously updated */
uint64_t counter_clock_cycles;
uint64_t counter_instructions;
uint64_t counter_irq_events;
uint64_t counter_nmi_events;
/* latched counters upon a write to the 'latch' address.
* One of these will be visible (read only) through an each-byte aperture. */
uint64_t latched_counter_clock_cycles;
uint64_t latched_counter_instructions;
uint64_t latched_counter_irq_events;
uint64_t latched_counter_nmi_events;
/* The invisible counters that keep processor state. */
uint64_t clock_cycles;
uint64_t cpu_instructions;
uint64_t irq_events;
uint64_t nmi_events;
/* Latched counters upon a write to the PERIPHERALS_COUNTER_LATCH address.
* One of these will be visible (read only) through an eight-byte aperture.
* The purpose of these latched registers is to read 64-bit values one byte
* at a time, without having to worry that their content will change along
* the way.
*/
uint64_t latched_clock_cycles;
uint64_t latched_cpu_instructions;
uint64_t latched_irq_events;
uint64_t latched_nmi_events;
uint64_t latched_wallclock_time;
/* Select which of the five latched registers will be visible.
* This is a Read/Write byte-wide register.
* If a non-existent register is selected, the 8-byte aperture will read as zero.
uint64_t latched_wallclock_time_split;
/* Select which of the six latched registers will be visible.
* This is a single byte, read/write register, accessible via address PERIPHERALS_COUNTER_SELECT.
* If a non-existent latch register is selected, the PERIPHERALS_REGS64 value will be zero.
*/
uint8_t visible_latch_register;
} PeripheralRegs;
} CounterPeripheral;
extern PeripheralRegs PRegs;
/* Declare the 'Sim65Peripherals' type and its single instance 'Peripherals'. */
typedef struct {
/* State of the peripherals simulated by sim65.
* Currently, there is only one: the COUNTER peripheral. */
CounterPeripheral Counter;
} Sim65Peripherals;
extern Sim65Peripherals Peripherals;
/*****************************************************************************/
/* Code */
@@ -80,11 +100,11 @@ extern PeripheralRegs PRegs;
void PeripheralWriteByte (uint8_t Addr, uint8_t Val);
void PeripheralsWriteByte (uint8_t Addr, uint8_t Val);
/* Write a byte to a memory location in the peripheral address aperture. */
uint8_t PeripheralReadByte (uint8_t Addr);
uint8_t PeripheralsReadByte (uint8_t Addr);
/* Read a byte from a memory location in the peripheral address aperture. */