test #2674

2025-06-23 17:09:06 +02:00
parent 4863a3e29b
commit 5fc15a7a60
204 changed files with 915 additions and 912 deletions
--- a/libsrc/sim6502/crt0.s
+++ b/libsrc/sim6502/crt0.s
@@ -22,8 +22,8 @@ startup:cld
        txs
        lda     #<(__MAIN_START__ + __MAIN_SIZE__ + __STACKSIZE__)
        ldx     #>(__MAIN_START__ + __MAIN_SIZE__ + __STACKSIZE__)
-        sta     sp
-        stx     sp+1
+        sta     c_sp
+        stx     c_sp+1
        jsr     zerobss
        jsr     initlib
        jsr     callmain
--- a/libsrc/sim6502/exehdr.s
+++ b/libsrc/sim6502/exehdr.s
@@ -5,7 +5,7 @@
 ;

        .export         __EXEHDR__ : absolute = 1       ; Linker referenced
-        .importzp       sp
+        .importzp       c_sp
        .import         __MAIN_START__
        .import         startup

@@ -24,6 +24,6 @@
 .else
        .error Unknown CPU type.
 .endif
-        .byte   sp                             ; sp address
+        .byte   c_sp                           ; c_sp address
        .addr   __MAIN_START__                 ; load address
        .addr   startup                        ; reset address