part of #1792 - 48GS02 assembler support
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@@ -152,7 +152,7 @@ Here is a description of all the command line options:
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Set the default for the CPU type. The option takes a parameter, which
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may be one of
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6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, sweet16, HuC6280, 4510, M740
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6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, sweet16, HuC6280, 4510, 45GS02, M740
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<label id="option-create-dep">
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@@ -442,6 +442,8 @@ The assembler accepts
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<tt><ref id=".P816" name=".P816"></tt> command was given).
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<item>all valid 4510 mnemonics when in <ref id="4510-mode" name="4510 mode"> (after the
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<tt><ref id=".P4510" name=".P4510"></tt> command was given).
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<item>all valid 45GS02 mnemonics when in <ref id="45GS02-mode" name="45GS02 mode"> (after the
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<tt><ref id=".P45GS02" name=".P45GS02"></tt> command was given).
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<item>all valid M740 mnemonics when in <ref id="M740-mode" name="M740 mode"> (after the
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<tt><ref id=".PM740" name=".PM740"></tt> command was given).
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</itemize>
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@@ -607,6 +609,11 @@ For more information about the Commodore C65/C64DX and the 4510 CPU, see
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<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/"> and
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<url url="https://en.wikipedia.org/wiki/Commodore_65" name="Wikipedia">.
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<sect1>45GS02 mode<label id="45GS02-mode"><p>
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The 45GS02 is a microcontroller that is the core of the MEGA65.
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It is an extension of the 4510 CPU and adds 32-bit addressing and a 32-bit
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pseudo register Q that is comprised of the four registers A, X, Y, and Z.
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<sect1>HUC6280 mode<label id="HUC6280-mode"><p>
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@@ -3399,6 +3406,12 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".CHARMAP" name=".CH
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(see <tt><ref id=".P4510" name=".P4510"></tt> command).
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<sect1><tt>.IFP45GS02</tt><label id=".IFP45GS02"><p>
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Conditional assembly: Check if the assembler is currently in 45GS02 mode
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(see <tt><ref id=".P45GS02" name=".P45GS02"></tt> command).
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<sect1><tt>.IFP816</tt><label id=".IFP816"><p>
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Conditional assembly: Check if the assembler is currently in 65816 mode
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@@ -3782,8 +3795,9 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
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<tt><ref id="option--cpu" name="--cpu"></tt> command line option.
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See: <tt><ref id=".PC02" name=".PC02"></tt>, <tt><ref id=".PSC02"
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name=".PSC02"></tt>, <tt><ref id=".P816" name=".P816"></tt> and
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<tt><ref id=".P4510" name=".P4510"></tt>
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name=".PSC02"></tt>, <tt><ref id=".P816" name=".P816"></tt>,
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<tt><ref id=".P4510" name=".P4510"></tt>, and
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<tt><ref id=".P45GS02" name=".P45GS02"></tt>
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<sect1><tt>.P02X</tt><label id=".P02X"><p>
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@@ -3802,19 +3816,30 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
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6502 instruction sets.
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See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PSC02"
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name=".PSC02"></tt>, <tt><ref id=".PC02" name=".PC02"></tt> and
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<tt><ref id=".P816" name=".P816"></tt>
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name=".PSC02"></tt>, <tt><ref id=".PC02" name=".PC02"></tt>,
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<tt><ref id=".P816" name=".P816"></tt>, and
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<tt><ref id=".P45GS02" name=".P45GS02"></tt>
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<sect1><tt>.P45GS02</tt><label id=".P45GS02"><p>
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Enable the 45GS02 instruction set. This is a superset of the 4510, 65C02, and
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6502 instruction sets.
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See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PSC02"
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name=".PSC02"></tt>, <tt><ref id=".PC02" name=".PC02"></tt>,
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<tt><ref id=".P816" name=".P816"></tt>, and
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<tt><ref id=".P4510" name=".P4510"></tt>
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<sect1><tt>.P816</tt><label id=".P816"><p>
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Enable the 65816 instruction set. This is a superset of the 65SC02 and
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6502 instruction sets.
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See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PSC02"
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name=".PSC02"></tt>, <tt><ref id=".PC02" name=".PC02"></tt> and
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<tt><ref id=".P4510" name=".P4510"></tt>
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name=".PSC02"></tt>, <tt><ref id=".PC02" name=".PC02"></tt>,
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<tt><ref id=".P4510" name=".P4510"></tt>, and
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<tt><ref id=".P45GS02" name=".P45GS02"></tt>
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<sect1><tt>.PAGELEN, .PAGELENGTH</tt><label id=".PAGELENGTH"><p>
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@@ -3841,9 +3866,9 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
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6502 and 65SC02 instructions.
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See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PSC02"
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name=".PSC02"></tt>, <tt><ref id=".P816" name=".P816"></tt> and
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<tt><ref id=".P4510" name=".P4510"></tt>
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name=".PSC02"></tt>, <tt><ref id=".P816" name=".P816"></tt>,
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<tt><ref id=".P4510" name=".P4510"></tt>, and
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<tt><ref id=".P45GS02" name=".P45GS02"></tt>
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<sect1><tt>.PDTV</tt><label id=".PDTV"><p>
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@@ -3946,9 +3971,9 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
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6502 instructions.
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See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PC02"
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name=".PC02"></tt>, <tt><ref id=".P816" name=".P816"></tt> and
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<tt><ref id=".P4510" name=".P4510"></tt>
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name=".PC02"></tt>, <tt><ref id=".P816" name=".P816"></tt>,
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<tt><ref id=".P4510" name=".P4510"></tt>, and
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<tt><ref id=".P45GS02" name=".P45GS02"></tt>
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<sect1><tt>.PUSHCHARMAP</tt><label id=".PUSHCHARMAP"><p>
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@@ -4195,7 +4220,7 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
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Switch the CPU instruction set. The command is followed by a string that
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specifies the CPU. Possible values are those that can also be supplied to
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the <tt><ref id="option--cpu" name="--cpu"></tt> command line option,
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namely: 6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, 4510, HuC6280 and m740.
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namely: 6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, 4510, 45GS02, HuC6280 and m740.
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See: <tt><ref id=".CPU" name=".CPU"></tt>,
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<tt><ref id=".IFP02" name=".IFP02"></tt>,
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@@ -4209,6 +4234,7 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
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<tt><ref id=".P02X" name=".P02X"></tt>,
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<tt><ref id=".P816" name=".P816"></tt>,
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<tt><ref id=".P4510" name=".P4510"></tt>,
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<tt><ref id=".P45GS02" name=".P45GS02"></tt>,
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<tt><ref id=".PC02" name=".PC02"></tt>,
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<tt><ref id=".PM740" name=".PM740"></tt>,
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<tt><ref id=".PSC02" name=".PSC02"></tt>
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@@ -4948,6 +4974,7 @@ each supported CPU a constant similar to
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CPU_SWEET16
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CPU_HUC6280
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CPU_4510
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CPU_45GS02
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CPU_6502DTV
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CPU_M740
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</verb></tscreen>
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@@ -4964,6 +4991,7 @@ another constant is defined:
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CPU_ISET_SWEET16
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CPU_ISET_HUC6280
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CPU_ISET_4510
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CPU_ISET_45GS02
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CPU_ISET_6502DTV
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CPU_ISET_M740
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</verb></tscreen>
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