part of #1792 - 48GS02 assembler support
This commit is contained in:
mrdudz
@@ -10,6 +10,7 @@ CPU_ISET_SWEET16 = $0080
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CPU_ISET_HUC6280 = $0100
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CPU_ISET_M740 = $0200
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CPU_ISET_4510 = $0400
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CPU_ISET_45GS02 = $0800
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; CPU capabilities
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CPU_NONE = CPU_ISET_NONE
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@@ -24,4 +25,5 @@ CPU_SWEET16 = CPU_ISET_SWEET16
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CPU_HUC6280 = CPU_ISET_6502|CPU_ISET_65SC02|CPU_ISET_65C02|CPU_ISET_HUC6280
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; NOTE: 45100 replaces "wai" ($cb) and "stp" ($db) of the 65C02 instruction set
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CPU_4510 = CPU_ISET_6502|CPU_ISET_65SC02|CPU_ISET_65C02|CPU_ISET_4510
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CPU_45GS02 = CPU_ISET_6502|CPU_ISET_65SC02|CPU_ISET_65C02|CPU_ISET_4510|CPU_ISET_45GS02
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CPU_M740 = CPU_ISET_6502|CPU_ISET_M740
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@@ -152,7 +152,7 @@ Here is a description of all the command line options:
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Set the default for the CPU type. The option takes a parameter, which
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may be one of
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6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, sweet16, HuC6280, 4510, M740
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6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, sweet16, HuC6280, 4510, 45GS02, M740
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<label id="option-create-dep">
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@@ -442,6 +442,8 @@ The assembler accepts
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<tt><ref id=".P816" name=".P816"></tt> command was given).
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<item>all valid 4510 mnemonics when in <ref id="4510-mode" name="4510 mode"> (after the
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<tt><ref id=".P4510" name=".P4510"></tt> command was given).
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<item>all valid 45GS02 mnemonics when in <ref id="45GS02-mode" name="45GS02 mode"> (after the
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<tt><ref id=".P45GS02" name=".P45GS02"></tt> command was given).
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<item>all valid M740 mnemonics when in <ref id="M740-mode" name="M740 mode"> (after the
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<tt><ref id=".PM740" name=".PM740"></tt> command was given).
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</itemize>
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@@ -607,6 +609,11 @@ For more information about the Commodore C65/C64DX and the 4510 CPU, see
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<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/"> and
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<url url="https://en.wikipedia.org/wiki/Commodore_65" name="Wikipedia">.
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<sect1>45GS02 mode<label id="45GS02-mode"><p>
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The 45GS02 is a microcontroller that is the core of the MEGA65.
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It is an extension of the 4510 CPU and adds 32-bit addressing and a 32-bit
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pseudo register Q that is comprised of the four registers A, X, Y, and Z.
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<sect1>HUC6280 mode<label id="HUC6280-mode"><p>
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@@ -3399,6 +3406,12 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".CHARMAP" name=".CH
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(see <tt><ref id=".P4510" name=".P4510"></tt> command).
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<sect1><tt>.IFP45GS02</tt><label id=".IFP45GS02"><p>
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Conditional assembly: Check if the assembler is currently in 45GS02 mode
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(see <tt><ref id=".P45GS02" name=".P45GS02"></tt> command).
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<sect1><tt>.IFP816</tt><label id=".IFP816"><p>
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Conditional assembly: Check if the assembler is currently in 65816 mode
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@@ -3782,8 +3795,9 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
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<tt><ref id="option--cpu" name="--cpu"></tt> command line option.
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See: <tt><ref id=".PC02" name=".PC02"></tt>, <tt><ref id=".PSC02"
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name=".PSC02"></tt>, <tt><ref id=".P816" name=".P816"></tt> and
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<tt><ref id=".P4510" name=".P4510"></tt>
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name=".PSC02"></tt>, <tt><ref id=".P816" name=".P816"></tt>,
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<tt><ref id=".P4510" name=".P4510"></tt>, and
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<tt><ref id=".P45GS02" name=".P45GS02"></tt>
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<sect1><tt>.P02X</tt><label id=".P02X"><p>
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@@ -3802,19 +3816,30 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
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6502 instruction sets.
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See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PSC02"
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name=".PSC02"></tt>, <tt><ref id=".PC02" name=".PC02"></tt> and
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<tt><ref id=".P816" name=".P816"></tt>
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name=".PSC02"></tt>, <tt><ref id=".PC02" name=".PC02"></tt>,
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<tt><ref id=".P816" name=".P816"></tt>, and
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<tt><ref id=".P45GS02" name=".P45GS02"></tt>
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<sect1><tt>.P45GS02</tt><label id=".P45GS02"><p>
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Enable the 45GS02 instruction set. This is a superset of the 4510, 65C02, and
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6502 instruction sets.
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See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PSC02"
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name=".PSC02"></tt>, <tt><ref id=".PC02" name=".PC02"></tt>,
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<tt><ref id=".P816" name=".P816"></tt>, and
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<tt><ref id=".P4510" name=".P4510"></tt>
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<sect1><tt>.P816</tt><label id=".P816"><p>
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Enable the 65816 instruction set. This is a superset of the 65SC02 and
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6502 instruction sets.
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See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PSC02"
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name=".PSC02"></tt>, <tt><ref id=".PC02" name=".PC02"></tt> and
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<tt><ref id=".P4510" name=".P4510"></tt>
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name=".PSC02"></tt>, <tt><ref id=".PC02" name=".PC02"></tt>,
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<tt><ref id=".P4510" name=".P4510"></tt>, and
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<tt><ref id=".P45GS02" name=".P45GS02"></tt>
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<sect1><tt>.PAGELEN, .PAGELENGTH</tt><label id=".PAGELENGTH"><p>
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@@ -3841,9 +3866,9 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
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6502 and 65SC02 instructions.
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See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PSC02"
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name=".PSC02"></tt>, <tt><ref id=".P816" name=".P816"></tt> and
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<tt><ref id=".P4510" name=".P4510"></tt>
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name=".PSC02"></tt>, <tt><ref id=".P816" name=".P816"></tt>,
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<tt><ref id=".P4510" name=".P4510"></tt>, and
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<tt><ref id=".P45GS02" name=".P45GS02"></tt>
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<sect1><tt>.PDTV</tt><label id=".PDTV"><p>
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@@ -3946,9 +3971,9 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
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6502 instructions.
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See: <tt><ref id=".P02" name=".P02"></tt>, <tt><ref id=".PC02"
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name=".PC02"></tt>, <tt><ref id=".P816" name=".P816"></tt> and
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<tt><ref id=".P4510" name=".P4510"></tt>
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name=".PC02"></tt>, <tt><ref id=".P816" name=".P816"></tt>,
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<tt><ref id=".P4510" name=".P4510"></tt>, and
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<tt><ref id=".P45GS02" name=".P45GS02"></tt>
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<sect1><tt>.PUSHCHARMAP</tt><label id=".PUSHCHARMAP"><p>
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@@ -4195,7 +4220,7 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
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Switch the CPU instruction set. The command is followed by a string that
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specifies the CPU. Possible values are those that can also be supplied to
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the <tt><ref id="option--cpu" name="--cpu"></tt> command line option,
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namely: 6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, 4510, HuC6280 and m740.
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namely: 6502, 6502X, 6502DTV, 65SC02, 65C02, 65816, 4510, 45GS02, HuC6280 and m740.
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See: <tt><ref id=".CPU" name=".CPU"></tt>,
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<tt><ref id=".IFP02" name=".IFP02"></tt>,
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@@ -4209,6 +4234,7 @@ See: <tt><ref id=".ASCIIZ" name=".ASCIIZ"></tt>,<tt><ref id=".BYTE" name=".BYTE"
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<tt><ref id=".P02X" name=".P02X"></tt>,
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<tt><ref id=".P816" name=".P816"></tt>,
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<tt><ref id=".P4510" name=".P4510"></tt>,
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<tt><ref id=".P45GS02" name=".P45GS02"></tt>,
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<tt><ref id=".PC02" name=".PC02"></tt>,
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<tt><ref id=".PM740" name=".PM740"></tt>,
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<tt><ref id=".PSC02" name=".PSC02"></tt>
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@@ -4948,6 +4974,7 @@ each supported CPU a constant similar to
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CPU_SWEET16
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CPU_HUC6280
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CPU_4510
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CPU_45GS02
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CPU_6502DTV
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CPU_M740
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</verb></tscreen>
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@@ -4964,6 +4991,7 @@ another constant is defined:
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CPU_ISET_SWEET16
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CPU_ISET_HUC6280
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CPU_ISET_4510
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CPU_ISET_45GS02
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CPU_ISET_6502DTV
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CPU_ISET_M740
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</verb></tscreen>
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@@ -118,13 +118,14 @@ Here is a description of all the command line options:
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<item>65816
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<item>huc6280
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<item>4510
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<item>45GS02
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<item>m740
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</itemize>
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6502x is for the NMOS 6502 with unofficial opcodes. 6502dtv is for the
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emulated CPU of the C64DTV device. huc6280 is the CPU of the PC engine.
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4510 is the CPU of the Commodore C65. 65816 is the CPU of the SNES. M740 is a
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Microcontroller by Mitsubishi.
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4510 is the CPU of the Commodore C65. 45GS02 is the CPU of the MEGA65.
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65816 is the CPU of the SNES. M740 is a Microcontroller by Mitsubishi.
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<label id="option--formfeeds">
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@@ -265,6 +266,8 @@ can produce output that can not be re-assembled, when one or more of those
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branches point outside of the disassembled memory. This can happen when text
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or binary data is processed.
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Disassembling 45GS02 compound instructions currently not supported.
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The 65816 support requires annotating ranges with the M and X flag states.
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This can be recorded with an emulator that supports Code and Data Logging,
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for example. Disassemble one bank at a time.
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@@ -414,6 +414,16 @@ void DoConditionals (void)
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CalcOverallIfCond ();
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break;
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case TOK_IFP45GS02:
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D = AllocIf (".IFP45GS02", 1);
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NextTok ();
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if (IfCond) {
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SetIfCond (D, GetCPU() == CPU_45GS02);
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}
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ExpectSep ();
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CalcOverallIfCond ();
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break;
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case TOK_IFP816:
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D = AllocIf (".IFP816", 1);
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NextTok ();
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@@ -507,6 +517,7 @@ int CheckConditionals (void)
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case TOK_IFP02:
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case TOK_IFP02X:
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case TOK_IFP4510:
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case TOK_IFP45GS02:
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case TOK_IFP816:
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case TOK_IFPC02:
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case TOK_IFPDTV:
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@@ -101,6 +101,9 @@ void GetEA (EffAddr* A)
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if (TokIsSep (CurTok.Tok)) {
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A->AddrModeSet = AM65_IMPLICIT;
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if (GetCPU() == CPU_45GS02) {
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A->AddrModeSet |= AM65_Q;
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}
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} else if (CurTok.Tok == TOK_HASH) {
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@@ -114,6 +117,11 @@ void GetEA (EffAddr* A)
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NextTok ();
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A->AddrModeSet = AM65_ACCU;
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} else if (CurTok.Tok == TOK_Q) {
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NextTok ();
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A->AddrModeSet = AM65_Q;
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} else if (CurTok.Tok == IndirectEnter) {
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/* One of the indirect modes */
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@@ -160,8 +168,19 @@ void GetEA (EffAddr* A)
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}
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} else {
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/* (adr) */
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A->AddrModeSet = (CPU == CPU_4510) ? AM65_ABS_IND
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: AM65_ABS_IND | AM65_ABS_IND_LONG | AM65_DIR_IND;
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switch (CPU) {
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case CPU_4510:
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A->AddrModeSet = AM65_ABS_IND;
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break;
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case CPU_45GS02:
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A->AddrModeSet = AM65_ABS_IND | AM65_DIR_IND;
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break;
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default:
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A->AddrModeSet = AM65_ABS_IND | AM65_ABS_IND_LONG | AM65_DIR_IND;
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break;
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}
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}
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}
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@@ -175,8 +194,14 @@ void GetEA (EffAddr* A)
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if (CurTok.Tok == TOK_COMMA) {
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/* [dir],y */
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NextTok ();
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Consume (TOK_Y, "'Y' expected");
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if (GetCPU() == CPU_45GS02) {
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Consume(TOK_Z, "'Z' expected");
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A->AddrModeSet = AM65_32BIT_BASE_IND_Z;
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}
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else {
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Consume(TOK_Y, "'Y' expected");
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A->AddrModeSet = AM65_DIR_IND_LONG_Y;
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}
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} else {
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/* [dir] */
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A->AddrModeSet = AM65_DIR_IND_LONG | AM65_ABS_IND_LONG;
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319
src/ca65/instr.c
319
src/ca65/instr.c
@@ -154,6 +154,12 @@ static void PutAll (const InsDesc* Ins);
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static void Put4510 (const InsDesc* Ins);
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/* Handle instructions of 4510 not matching any EATab */
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static void Put45GS02 (const InsDesc* Ins);
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/* Handle [adr],z instructions of 45GS02 */
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static void Put45GS02_Q (const InsDesc* Ins);
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/* Handle Q instructions of 45GS02 */
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static void PutSweet16 (const InsDesc* Ins);
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/* Handle a generic sweet16 instruction */
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@@ -758,6 +764,170 @@ static const struct {
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}
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};
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/* Instruction table for the 45GS02 */
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static const struct {
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unsigned Count;
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InsDesc Ins[149];
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} InsTab45GS02 = {
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/* CAUTION: table must be sorted for bsearch */
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sizeof (InsTab45GS02.Ins) / sizeof (InsTab45GS02.Ins[0]),
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{
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/* BEGIN SORTED.SH */
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{ "ADC", 0x4080A66C, 0x60, 0, Put45GS02 },
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{ "ADCQ", 0x0000140C, 0x60, 13, Put45GS02_Q },
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{ "AND", 0x4080A66C, 0x20, 0, Put45GS02 },
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{ "ANDQ", 0x0000140C, 0x20, 13, Put45GS02_Q },
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{ "ASL", 0x0000006e, 0x02, 1, PutAll },
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{ "ASLQ", 0x800000ec, 0x00, 14, Put45GS02_Q },
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{ "ASR", 0x00000026, 0x43, 0, Put4510 },
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{ "ASRQ", 0x80000024, 0x40, 15, Put45GS02_Q },
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{ "ASW", 0x00000008, 0xcb, 6, PutAll },
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{ "BBR0", 0x00000000, 0x0F, 0, PutBitBranch },
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{ "BBR1", 0x00000000, 0x1F, 0, PutBitBranch },
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{ "BBR2", 0x00000000, 0x2F, 0, PutBitBranch },
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{ "BBR3", 0x00000000, 0x3F, 0, PutBitBranch },
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{ "BBR4", 0x00000000, 0x4F, 0, PutBitBranch },
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{ "BBR5", 0x00000000, 0x5F, 0, PutBitBranch },
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{ "BBR6", 0x00000000, 0x6F, 0, PutBitBranch },
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{ "BBR7", 0x00000000, 0x7F, 0, PutBitBranch },
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{ "BBS0", 0x00000000, 0x8F, 0, PutBitBranch },
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{ "BBS1", 0x00000000, 0x9F, 0, PutBitBranch },
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{ "BBS2", 0x00000000, 0xAF, 0, PutBitBranch },
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{ "BBS3", 0x00000000, 0xBF, 0, PutBitBranch },
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{ "BBS4", 0x00000000, 0xCF, 0, PutBitBranch },
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{ "BBS5", 0x00000000, 0xDF, 0, PutBitBranch },
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{ "BBS6", 0x00000000, 0xEF, 0, PutBitBranch },
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{ "BBS7", 0x00000000, 0xFF, 0, PutBitBranch },
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{ "BCC", 0x00020000, 0x90, 0, PutPCRel8 },
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{ "BCS", 0x00020000, 0xb0, 0, PutPCRel8 },
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{ "BEQ", 0x00020000, 0xf0, 0, PutPCRel8 },
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{ "BIT", 0x00A0006C, 0x00, 2, PutAll },
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{ "BITQ", 0x0000000c, 0x20, 15, Put45GS02_Q },
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{ "BMI", 0x00020000, 0x30, 0, PutPCRel8 },
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{ "BNE", 0x00020000, 0xd0, 0, PutPCRel8 },
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{ "BPL", 0x00020000, 0x10, 0, PutPCRel8 },
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{ "BRA", 0x00020000, 0x80, 0, PutPCRel8 },
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{ "BRK", 0x00000001, 0x00, 0, PutAll },
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{ "BSR", 0x00040000, 0x63, 0, PutPCRel4510 },
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{ "BVC", 0x00020000, 0x50, 0, PutPCRel8 },
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{ "BVS", 0x00020000, 0x70, 0, PutPCRel8 },
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{ "CLC", 0x00000001, 0x18, 0, PutAll },
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{ "CLD", 0x00000001, 0xd8, 0, PutAll },
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{ "CLE", 0x00000001, 0x02, 0, PutAll },
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{ "CLI", 0x00000001, 0x58, 0, PutAll },
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{ "CLV", 0x00000001, 0xb8, 0, PutAll },
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{ "CMP", 0x4080A66C, 0xc0, 0, Put45GS02 },
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{ "CMPQ", 0x0000140C, 0xC0, 13, Put45GS02_Q },
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{ "CPX", 0x0080000C, 0xe0, 1, PutAll },
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{ "CPY", 0x0080000C, 0xc0, 1, PutAll },
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{ "CPZ", 0x0080000C, 0xd0, 1, Put4510 },
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{ "DEA", 0x00000001, 0x00, 3, PutAll }, /* == DEC */
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{ "DEC", 0x0000006F, 0x00, 3, PutAll },
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{ "DEQ", 0x800000ec, 0xc0, 14, Put45GS02_Q },
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{ "DEW", 0x00000004, 0xc3, 9, PutAll },
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{ "DEX", 0x00000001, 0xca, 0, PutAll },
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{ "DEY", 0x00000001, 0x88, 0, PutAll },
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{ "DEZ", 0x00000001, 0x3B, 0, PutAll },
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{ "EOM", 0x00000001, 0xea, 0, PutAll },
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{ "EOR", 0x4080A66C, 0x40, 0, Put45GS02 },
|
||||
{ "EORQ", 0x0000140C, 0x40, 13, Put45GS02_Q },
|
||||
{ "INA", 0x00000001, 0x00, 4, PutAll }, /* == INC */
|
||||
{ "INC", 0x0000006f, 0x00, 4, PutAll },
|
||||
{ "INQ", 0x800000ec, 0xe0, 14, Put45GS02_Q },
|
||||
{ "INW", 0x00000004, 0xe3, 9, PutAll },
|
||||
{ "INX", 0x00000001, 0xe8, 0, PutAll },
|
||||
{ "INY", 0x00000001, 0xc8, 0, PutAll },
|
||||
{ "INZ", 0x00000001, 0x1B, 0, PutAll },
|
||||
{ "JMP", 0x00010808, 0x4c, 6, PutAll },
|
||||
{ "JSR", 0x00010808, 0x20, 7, Put4510 },
|
||||
{ "LBCC", 0x00040000, 0x93, 0, PutPCRel4510 },
|
||||
{ "LBCS", 0x00040000, 0xb3, 0, PutPCRel4510 },
|
||||
{ "LBEQ", 0x00040000, 0xf3, 0, PutPCRel4510 },
|
||||
{ "LBMI", 0x00040000, 0x33, 0, PutPCRel4510 },
|
||||
{ "LBNE", 0x00040000, 0xd3, 0, PutPCRel4510 },
|
||||
{ "LBPL", 0x00040000, 0x13, 0, PutPCRel4510 },
|
||||
{ "LBRA", 0x00040000, 0x83, 0, PutPCRel4510 },
|
||||
{ "LBVC", 0x00040000, 0x53, 0, PutPCRel4510 },
|
||||
{ "LBVS", 0x00040000, 0x73, 0, PutPCRel4510 },
|
||||
{ "LDA", 0x4090A66C, 0xa0, 0, Put45GS02 },
|
||||
{ "LDQ", 0x4000140C, 0xa0, 13, Put45GS02_Q },
|
||||
{ "LDX", 0x0080030C, 0xa2, 1, PutAll },
|
||||
{ "LDY", 0x0080006C, 0xa0, 1, PutAll },
|
||||
{ "LDZ", 0x00800048, 0xa3, 1, Put4510 },
|
||||
{ "LSR", 0x0000006F, 0x42, 1, PutAll },
|
||||
{ "LSRQ", 0x800000ec, 0x40, 14, Put45GS02_Q },
|
||||
{ "MAP", 0x00000001, 0x5C, 0, PutAll },
|
||||
{ "NEG", 0x00000001, 0x42, 0, PutAll },
|
||||
{ "NOP", 0x00000001, 0xea, 0, PutAll }, /* == EOM */
|
||||
{ "ORA", 0x4080A66C, 0x00, 0, Put45GS02 },
|
||||
{ "ORQ", 0x0000140C, 0x00, 13, Put45GS02_Q },
|
||||
{ "PHA", 0x00000001, 0x48, 0, PutAll },
|
||||
{ "PHD", 0x08000008, 0xf4, 1, PutAll }, /* == PHW */
|
||||
{ "PHP", 0x00000001, 0x08, 0, PutAll },
|
||||
{ "PHW", 0x08000008, 0xf4, 1, PutAll },
|
||||
{ "PHX", 0x00000001, 0xda, 0, PutAll },
|
||||
{ "PHY", 0x00000001, 0x5a, 0, PutAll },
|
||||
{ "PHZ", 0x00000001, 0xdb, 0, PutAll },
|
||||
{ "PLA", 0x00000001, 0x68, 0, PutAll },
|
||||
{ "PLP", 0x00000001, 0x28, 0, PutAll },
|
||||
{ "PLX", 0x00000001, 0xfa, 0, PutAll },
|
||||
{ "PLY", 0x00000001, 0x7a, 0, PutAll },
|
||||
{ "PLZ", 0x00000001, 0xfb, 0, PutAll },
|
||||
{ "RMB0", 0x00000004, 0x07, 1, PutAll },
|
||||
{ "RMB1", 0x00000004, 0x17, 1, PutAll },
|
||||
{ "RMB2", 0x00000004, 0x27, 1, PutAll },
|
||||
{ "RMB3", 0x00000004, 0x37, 1, PutAll },
|
||||
{ "RMB4", 0x00000004, 0x47, 1, PutAll },
|
||||
{ "RMB5", 0x00000004, 0x57, 1, PutAll },
|
||||
{ "RMB6", 0x00000004, 0x67, 1, PutAll },
|
||||
{ "RMB7", 0x00000004, 0x77, 1, PutAll },
|
||||
{ "ROL", 0x0000006F, 0x22, 1, PutAll },
|
||||
{ "ROLQ", 0x800000ec, 0x20, 14, Put45GS02_Q },
|
||||
{ "ROR", 0x0000006F, 0x62, 1, PutAll },
|
||||
{ "RORQ", 0x800000ec, 0x60, 14, Put45GS02_Q },
|
||||
{ "ROW", 0x00000008, 0xeb, 6, PutAll },
|
||||
{ "RTI", 0x00000001, 0x40, 0, PutAll },
|
||||
{ "RTN", 0x00800000, 0x62, 1, PutAll },
|
||||
{ "RTS", 0x00000001, 0x60, 0, PutAll },
|
||||
{ "SBC", 0x4080A66C, 0xe0, 0, Put45GS02 },
|
||||
{ "SBCQ", 0x0000140C, 0xe0, 13, Put45GS02_Q },
|
||||
{ "SEC", 0x00000001, 0x38, 0, PutAll },
|
||||
{ "SED", 0x00000001, 0xf8, 0, PutAll },
|
||||
{ "SEE", 0x00000001, 0x03, 0, PutAll },
|
||||
{ "SEI", 0x00000001, 0x78, 0, PutAll },
|
||||
{ "SMB0", 0x00000004, 0x87, 1, PutAll },
|
||||
{ "SMB1", 0x00000004, 0x97, 1, PutAll },
|
||||
{ "SMB2", 0x00000004, 0xA7, 1, PutAll },
|
||||
{ "SMB3", 0x00000004, 0xB7, 1, PutAll },
|
||||
{ "SMB4", 0x00000004, 0xC7, 1, PutAll },
|
||||
{ "SMB5", 0x00000004, 0xD7, 1, PutAll },
|
||||
{ "SMB6", 0x00000004, 0xE7, 1, PutAll },
|
||||
{ "SMB7", 0x00000004, 0xF7, 1, PutAll },
|
||||
{ "STA", 0x4010A66C, 0x80, 0, Put45GS02 },
|
||||
{ "STQ", 0x0000140C, 0x80, 13, Put45GS02_Q },
|
||||
{ "STX", 0x0000030c, 0x82, 1, Put4510 },
|
||||
{ "STY", 0x0000006c, 0x80, 1, Put4510 },
|
||||
{ "STZ", 0x0000006c, 0x04, 5, PutAll },
|
||||
{ "TAB", 0x00000001, 0x5b, 0, PutAll },
|
||||
{ "TAX", 0x00000001, 0xaa, 0, PutAll },
|
||||
{ "TAY", 0x00000001, 0xa8, 0, PutAll },
|
||||
{ "TAZ", 0x00000001, 0x4b, 0, PutAll },
|
||||
{ "TBA", 0x00000001, 0x7b, 0, PutAll },
|
||||
{ "TRB", 0x0000000c, 0x10, 1, PutAll },
|
||||
{ "TSB", 0x0000000c, 0x00, 1, PutAll },
|
||||
{ "TSX", 0x00000001, 0xba, 0, PutAll },
|
||||
{ "TSY", 0x00000001, 0x0b, 0, PutAll },
|
||||
{ "TXA", 0x00000001, 0x8a, 0, PutAll },
|
||||
{ "TXS", 0x00000001, 0x9a, 0, PutAll },
|
||||
{ "TYA", 0x00000001, 0x98, 0, PutAll },
|
||||
{ "TYS", 0x00000001, 0x2b, 0, PutAll },
|
||||
{ "TZA", 0x00000001, 0x6b, 0, PutAll },
|
||||
/* END SORTED.SH */
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
/* Instruction table for the 65816 */
|
||||
static const struct {
|
||||
unsigned Count;
|
||||
@@ -1192,6 +1362,7 @@ static const InsTable* InsTabs[CPU_COUNT] = {
|
||||
(const InsTable*) &InsTabHuC6280,
|
||||
(const InsTable*) &InsTabm740, /* Mitsubishi 740 */
|
||||
(const InsTable*) &InsTab4510,
|
||||
(const InsTable*) &InsTab45GS02,
|
||||
};
|
||||
const InsTable* InsTab = (const InsTable*) &InsTab6502;
|
||||
|
||||
@@ -1199,85 +1370,103 @@ const InsTable* InsTab = (const InsTable*) &InsTab6502;
|
||||
** addressing mode. (The value in the table is ORed with the base opcode)
|
||||
** NOTE: each table has one entry per addressing mode!
|
||||
*/
|
||||
static unsigned char EATab[14][AM65I_COUNT] = {
|
||||
static unsigned char EATab[16][AM65I_COUNT] = {
|
||||
{ /* Table 0 (sec, sed, seo, set, slw, sta, stp, tax, tay, tsx, txa, txs, tya) */
|
||||
0x00, 0x00, 0x05, 0x0D, 0x0F, 0x15, 0x1D, 0x1F,
|
||||
0x00, 0x19, 0x12, 0x00, 0x07, 0x11, 0x17, 0x01,
|
||||
0x00, 0x00, 0x00, 0x03, 0x13, 0x09, 0x00, 0x09,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00
|
||||
},
|
||||
{ /* Table 1 (rol, ror, stx, sty, tst) */
|
||||
0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
|
||||
0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x80, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 2 (bit) */
|
||||
0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 3 (dec, dea) */
|
||||
0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 4 (inc) */
|
||||
0x1A, 0x1A, 0xE6, 0xEE, 0x00, 0xF6, 0xFE, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 5 (stz) */
|
||||
0x00, 0x00, 0x60, 0x98, 0x00, 0x70, 0x9E, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 6 (jmp, rrf) */
|
||||
0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
|
||||
0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x90, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 7 (jsr) */
|
||||
0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
|
||||
0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 8 */
|
||||
0x00, 0x40, 0x01, 0x41, 0x00, 0x09, 0x49, 0x00,
|
||||
0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 9 (dew, inw) */
|
||||
0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x30, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 10 (NOPs, clbX, sebX) */
|
||||
0xea, 0x00, 0x04, 0x0c, 0x00, 0x14, 0x1c, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 11 (LAX) */
|
||||
0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
|
||||
0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
||||
0x00, 0x00, 0x80, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 12 (m740: JMP) */
|
||||
0x00, 0x00, 0x00, 0x4c, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0xb2, 0x6c, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
},
|
||||
{ /* Table 13 (Q) */
|
||||
0x00, 0x00, 0x05, 0x0D, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x12, 0x00, 0x12, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00
|
||||
},
|
||||
{ /* Table 14 (Q) */
|
||||
0x00, 0x00, 0x06, 0x0e, 0x00, 0x16, 0x1e, 0x00,
|
||||
0x00, 0x00, 0x12, 0x00, 0x12, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a
|
||||
},
|
||||
{ /* Table 15 */
|
||||
0x00, 0x00, 0x04, 0x0c, 0x00, 0x14, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03
|
||||
}
|
||||
};
|
||||
|
||||
/* Table to build the effective SWEET16 opcode from a base opcode and an
|
||||
@@ -1325,6 +1514,8 @@ unsigned char ExtBytes[AM65I_COUNT] = {
|
||||
2, /* Immidiate word */
|
||||
2, /* Direct, Relative short */
|
||||
1, /* Special Page */
|
||||
1, /* [Direct],z */
|
||||
0, /* Q */
|
||||
};
|
||||
|
||||
/* Table that encodes the additional bytes for each SWEET16 instruction */
|
||||
@@ -1968,9 +2159,7 @@ static void PutAll (const InsDesc* Ins)
|
||||
|
||||
|
||||
|
||||
static void Put4510 (const InsDesc* Ins)
|
||||
/* Handle all other instructions, with modifications for 4510 */
|
||||
{
|
||||
static void Emit4510 (EffAddr* A) {
|
||||
/* The 4510 uses all 256 possible opcodes, so the last ones were crammed
|
||||
** in where an opcode was still undefined. As a result, some of those
|
||||
** don't follow any rules for encoding the addressmodes. So the EATab
|
||||
@@ -1990,26 +2179,90 @@ static void Put4510 (const InsDesc* Ins)
|
||||
** $d0 -> $c2 : CPZ #$00
|
||||
** $fc -> $23 : JSR ($1234,X)
|
||||
*/
|
||||
EffAddr A;
|
||||
|
||||
/* Evaluate the addressing mode used */
|
||||
if (EvalEA (Ins, &A)) {
|
||||
switch (A.Opcode) {
|
||||
case 0x47: A.Opcode = 0x44; break;
|
||||
case 0x57: A.Opcode = 0x54; break;
|
||||
case 0x93: A.Opcode = 0x82; break;
|
||||
case 0x9C: A.Opcode = 0x8B; break;
|
||||
case 0x9E: A.Opcode = 0x9B; break;
|
||||
case 0xAF: A.Opcode = 0xAB; break;
|
||||
case 0xBF: A.Opcode = 0xBB; break;
|
||||
case 0xB3: A.Opcode = 0xE2; break;
|
||||
case 0xD0: A.Opcode = 0xC2; break;
|
||||
case 0xFC: A.Opcode = 0x23; break;
|
||||
switch (A->Opcode) {
|
||||
case 0x47:
|
||||
A->Opcode = 0x44;
|
||||
break;
|
||||
case 0x57:
|
||||
A->Opcode = 0x54;
|
||||
break;
|
||||
case 0x93:
|
||||
A->Opcode = 0x82;
|
||||
break;
|
||||
case 0x9C:
|
||||
A->Opcode = 0x8B;
|
||||
break;
|
||||
case 0x9E:
|
||||
A->Opcode = 0x9B;
|
||||
break;
|
||||
case 0xAF:
|
||||
A->Opcode = 0xAB;
|
||||
break;
|
||||
case 0xBF:
|
||||
A->Opcode = 0xBB;
|
||||
break;
|
||||
case 0xB3:
|
||||
A->Opcode = 0xE2;
|
||||
break;
|
||||
case 0xD0:
|
||||
A->Opcode = 0xC2;
|
||||
break;
|
||||
case 0xFC:
|
||||
A->Opcode = 0x23;
|
||||
break;
|
||||
default: /* Keep opcode as it is */ break;
|
||||
}
|
||||
|
||||
/* No error, output code */
|
||||
EmitCode (&A);
|
||||
EmitCode(A);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void Put4510 (const InsDesc* Ins)
|
||||
/* Handle all other instructions, with modifications for 4510 */
|
||||
{
|
||||
EffAddr A;
|
||||
|
||||
/* Evaluate the addressing mode used */
|
||||
if (EvalEA (Ins, &A)) {
|
||||
Emit4510(&A);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void Put45GS02 (const InsDesc* Ins)
|
||||
/* Handle all other instructions, with modifications for 45GS02 */
|
||||
{
|
||||
EffAddr A;
|
||||
|
||||
if (EvalEA(Ins, &A)) {
|
||||
if (A.AddrModeSet == AM65_32BIT_BASE_IND_Z) {
|
||||
Emit0(0xEA); /* NOP prefix */
|
||||
}
|
||||
Emit4510(&A);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void Put45GS02_Q (const InsDesc* Ins) {
|
||||
EffAddr A;
|
||||
|
||||
if (EvalEA(Ins, &A)) {
|
||||
Emit0(0x42);
|
||||
Emit0(0x42);
|
||||
if ((A.AddrModeBit == AM65_DIR_IND_LONG) || (A.AddrModeBit == AM65_32BIT_BASE_IND_Z)) {
|
||||
Emit0(0xEA); /* NOP prefix */
|
||||
}
|
||||
if (A.Opcode == 0xea) {
|
||||
A.Opcode = 0x1a;
|
||||
}
|
||||
else if (A.Opcode == 0xca) {
|
||||
A.Opcode = 0x3a;
|
||||
}
|
||||
EmitCode(&A);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -59,35 +59,37 @@
|
||||
** available on these CPUs are removed before doing any checks.
|
||||
*/
|
||||
#define AM65_IMPLICIT 0x00000003UL /* IMP */
|
||||
#define AM65_ACCU 0x00000002UL /* A, BIT, A */
|
||||
#define AM65_DIR 0x00000004UL /* ZP, BIT, ZP */
|
||||
#define AM65_ACCU 0x00000002UL /* A */
|
||||
#define AM65_DIR 0x00000004UL /* ZP */
|
||||
#define AM65_ABS 0x00000008UL /* ABS */
|
||||
#define AM65_ABS_LONG 0x00000010UL /* -- */
|
||||
#define AM65_ABS_LONG 0x00000010UL /* adr */
|
||||
#define AM65_DIR_X 0x00000020UL /* ZP,X */
|
||||
#define AM65_ABS_X 0x00000040UL /* ABS, X */
|
||||
#define AM65_ABS_LONG_X 0x00000080UL /* -- */
|
||||
#define AM65_ABS_LONG_X 0x00000080UL /* adr,x */
|
||||
#define AM65_DIR_Y 0x00000100UL /* ZP, Y */
|
||||
#define AM65_ABS_Y 0x00000200UL /* ABS, Y */
|
||||
#define AM65_DIR_IND 0x00000400UL /* (ZP IND) */
|
||||
#define AM65_ABS_IND 0x00000800UL /* (IND) */
|
||||
#define AM65_DIR_IND_LONG 0x00001000UL /* -- */
|
||||
#define AM65_DIR_IND_Y 0x00002000UL /* IND, Y */
|
||||
#define AM65_DIR_IND_LONG_Y 0x00004000UL /* -- */
|
||||
#define AM65_DIR_X_IND 0x00008000UL /* IND, X */
|
||||
#define AM65_ABS_X_IND 0x00010000UL /* -- */
|
||||
#define AM65_DIR_IND 0x00000400UL /* (ZP) or (ZP),z (4510 / 45GS02) */
|
||||
#define AM65_ABS_IND 0x00000800UL /* (ABS) */
|
||||
#define AM65_DIR_IND_LONG 0x00001000UL /* [ABS] (65816) */
|
||||
#define AM65_DIR_IND_Y 0x00002000UL /* (ZP),y */
|
||||
#define AM65_DIR_IND_LONG_Y 0x00004000UL /* [adr],y (not 45GS02) */
|
||||
#define AM65_DIR_X_IND 0x00008000UL /* (ZP,x) */
|
||||
#define AM65_ABS_X_IND 0x00010000UL /* (ABS,x) */
|
||||
#define AM65_REL 0x00020000UL /* REL */
|
||||
#define AM65_REL_LONG 0x00040000UL /* -- */
|
||||
#define AM65_STACK_REL 0x00080000UL /* SP ? */
|
||||
#define AM65_STACK_REL_IND_Y 0x00100000UL /* ? */
|
||||
#define AM65_REL_LONG 0x00040000UL /* LONGREL */
|
||||
#define AM65_STACK_REL 0x00080000UL /* adr,s */
|
||||
#define AM65_STACK_REL_IND_Y 0x00100000UL /* (rel,s),y */
|
||||
#define AM65_IMM_ACCU 0x00200000UL
|
||||
#define AM65_IMM_INDEX 0x00400000UL
|
||||
#define AM65_IMM_IMPLICIT 0x00800000UL /* IMM */
|
||||
#define AM65_BLOCKMOVE 0x01000000UL /* -- */
|
||||
#define AM65_BLOCKXFER 0x02000000UL /* -- */
|
||||
#define AM65_ABS_IND_LONG 0x04000000UL /* -- */
|
||||
#define AM65_BLOCKMOVE 0x01000000UL
|
||||
#define AM65_BLOCKXFER 0x02000000UL
|
||||
#define AM65_ABS_IND_LONG 0x04000000UL /* (adr) [dir] */
|
||||
#define AM65_IMM_IMPLICIT_WORD 0x08000000UL /* PHW #$1234 (4510 only) */
|
||||
#define AM65_ZP_REL 0x10000000UL /* ZP, REL (m740) */
|
||||
#define AM65_SPECIAL_PAGE 0x20000000UL /* $FFxx (m740) */
|
||||
#define AM65_32BIT_BASE_IND_Z 0x40000000UL /* LDA [$nn],Z (45GS02 only) */
|
||||
#define AM65_Q 0x80000000UL /* Q (45GS02 only) */
|
||||
|
||||
/* Bitmask for all ZP operations that have correspondent ABS ops */
|
||||
#define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
|
||||
@@ -138,7 +140,9 @@
|
||||
#define AM65I_IMM_IMPLICIT_WORD 27
|
||||
#define AM65I_ZP_REL 28
|
||||
#define AM65I_SPECIAL_PAGE 29
|
||||
#define AM65I_COUNT 30
|
||||
#define AM65I_32BIT_BASE_IND_Z 30
|
||||
#define AM65I_Q 31
|
||||
#define AM65I_COUNT 32
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1594,6 +1594,14 @@ static void DoP4510 (void)
|
||||
|
||||
|
||||
|
||||
static void DoP45GS02 (void)
|
||||
/* Switch to 45GS02 CPU */
|
||||
{
|
||||
SetCPU (CPU_45GS02);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void DoPDTV (void)
|
||||
/* Switch to C64DTV CPU */
|
||||
{
|
||||
@@ -2151,6 +2159,7 @@ static CtrlDesc CtrlCmdTab [] = {
|
||||
{ ccKeepToken, DoConditionals }, /* .IFP02 */
|
||||
{ ccKeepToken, DoConditionals }, /* .IFP02X */
|
||||
{ ccKeepToken, DoConditionals }, /* .IFP4510 */
|
||||
{ ccKeepToken, DoConditionals }, /* .IFP45GS02 */
|
||||
{ ccKeepToken, DoConditionals }, /* .IFP816 */
|
||||
{ ccKeepToken, DoConditionals }, /* .IFPC02 */
|
||||
{ ccKeepToken, DoConditionals }, /* .IFPDTV */
|
||||
@@ -2186,6 +2195,7 @@ static CtrlDesc CtrlCmdTab [] = {
|
||||
{ ccNone, DoP02 }, /* .P02 */
|
||||
{ ccNone, DoP02X }, /* .P02X */
|
||||
{ ccNone, DoP4510 }, /* .P4510 */
|
||||
{ ccNone, DoP45GS02 }, /* .P45GS02 */
|
||||
{ ccNone, DoP816 }, /* .P816 */
|
||||
{ ccNone, DoPageLength }, /* .PAGELEN, .PAGELENGTH */
|
||||
{ ccNone, DoUnexpected }, /* .PARAMCOUNT */
|
||||
|
||||
@@ -223,6 +223,7 @@ struct DotKeyword {
|
||||
{ ".IFP02", TOK_IFP02 },
|
||||
{ ".IFP02X", TOK_IFP02X },
|
||||
{ ".IFP4510", TOK_IFP4510 },
|
||||
{ ".IFP45GS02", TOK_IFP45GS02 },
|
||||
{ ".IFP816", TOK_IFP816 },
|
||||
{ ".IFPC02", TOK_IFPC02 },
|
||||
{ ".IFPDTV", TOK_IFPDTV },
|
||||
@@ -263,6 +264,7 @@ struct DotKeyword {
|
||||
{ ".P02", TOK_P02 },
|
||||
{ ".P02X", TOK_P02X },
|
||||
{ ".P4510", TOK_P4510 },
|
||||
{ ".P45GS02", TOK_P45GS02 },
|
||||
{ ".P816", TOK_P816 },
|
||||
{ ".PAGELEN", TOK_PAGELENGTH },
|
||||
{ ".PAGELENGTH", TOK_PAGELENGTH },
|
||||
@@ -1279,12 +1281,19 @@ Again:
|
||||
break;
|
||||
|
||||
case 'S':
|
||||
if ((CPU == CPU_4510) || (CPU == CPU_65816)) {
|
||||
if ((CPU == CPU_4510) || (CPU == CPU_45GS02) || (CPU == CPU_65816)) {
|
||||
CurTok.Tok = TOK_S;
|
||||
return;
|
||||
}
|
||||
break;
|
||||
|
||||
case 'Q':
|
||||
if (CPU == CPU_45GS02) {
|
||||
CurTok.Tok = TOK_Q;
|
||||
return;
|
||||
}
|
||||
break;
|
||||
|
||||
case 'X':
|
||||
CurTok.Tok = TOK_X;
|
||||
return;
|
||||
@@ -1299,7 +1308,7 @@ Again:
|
||||
CurTok.Tok = TOK_OVERRIDE_ZP;
|
||||
return;
|
||||
} else {
|
||||
if (CPU == CPU_4510) {
|
||||
if ((CPU == CPU_4510) || (CPU == CPU_45GS02)) {
|
||||
CurTok.Tok = TOK_Z;
|
||||
return;
|
||||
}
|
||||
@@ -1311,7 +1320,7 @@ Again:
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
if ((CPU == CPU_4510) &&
|
||||
if ((CPU == CPU_4510 || CPU == CPU_45GS02) &&
|
||||
(toupper (SB_AtUnchecked (&CurTok.SVal, 0)) == 'S') &&
|
||||
(toupper (SB_AtUnchecked (&CurTok.SVal, 1)) == 'P')) {
|
||||
|
||||
|
||||
@@ -68,6 +68,7 @@ typedef enum token_t {
|
||||
TOK_Y, /* Y register */
|
||||
TOK_Z, /* Z register */
|
||||
TOK_S, /* S register */
|
||||
TOK_Q, /* Q pseudo register */
|
||||
TOK_REG, /* Sweet16 R.. register (in sweet16 mode) */
|
||||
|
||||
TOK_ASSIGN, /* := */
|
||||
@@ -195,6 +196,7 @@ typedef enum token_t {
|
||||
TOK_IFP02,
|
||||
TOK_IFP02X,
|
||||
TOK_IFP4510,
|
||||
TOK_IFP45GS02,
|
||||
TOK_IFP816,
|
||||
TOK_IFPC02,
|
||||
TOK_IFPDTV,
|
||||
@@ -230,6 +232,7 @@ typedef enum token_t {
|
||||
TOK_P02,
|
||||
TOK_P02X,
|
||||
TOK_P4510,
|
||||
TOK_P45GS02,
|
||||
TOK_P816,
|
||||
TOK_PAGELENGTH,
|
||||
TOK_PARAMCOUNT,
|
||||
|
||||
@@ -63,6 +63,7 @@ const char* CPUNames[CPU_COUNT] = {
|
||||
"huc6280",
|
||||
"m740",
|
||||
"4510",
|
||||
"45GS02"
|
||||
};
|
||||
|
||||
/* Tables with CPU instruction sets */
|
||||
@@ -78,6 +79,7 @@ const unsigned CPUIsets[CPU_COUNT] = {
|
||||
CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02 | CPU_ISET_HUC6280,
|
||||
CPU_ISET_6502 | CPU_ISET_M740,
|
||||
CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02 | CPU_ISET_4510,
|
||||
CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02 | CPU_ISET_4510 | CPU_ISET_45GS02,
|
||||
};
|
||||
|
||||
|
||||
|
||||
@@ -58,6 +58,7 @@ typedef enum {
|
||||
CPU_HUC6280, /* Used in PC engine */
|
||||
CPU_M740, /* Mitsubishi 740 series MCUs */
|
||||
CPU_4510, /* CPU of C65 */
|
||||
CPU_45GS02, /* CPU of MEGA65 */
|
||||
CPU_COUNT /* Number of different CPUs */
|
||||
} cpu_t;
|
||||
|
||||
@@ -74,6 +75,7 @@ enum {
|
||||
CPU_ISET_HUC6280 = 1 << CPU_HUC6280,
|
||||
CPU_ISET_M740 = 1 << CPU_M740,
|
||||
CPU_ISET_4510 = 1 << CPU_4510,
|
||||
CPU_ISET_45GS02 = 1 << CPU_45GS02
|
||||
};
|
||||
|
||||
/* CPU used */
|
||||
|
||||
BIN
test/asm/opcodes/45GS02-opcodes.ref
Normal file
BIN
test/asm/opcodes/45GS02-opcodes.ref
Normal file
Binary file not shown.
377
test/asm/opcodes/45GS02-opcodes.s
Normal file
377
test/asm/opcodes/45GS02-opcodes.s
Normal file
@@ -0,0 +1,377 @@
|
||||
.setcpu "45GS02"
|
||||
|
||||
brk
|
||||
ora ($05,x)
|
||||
cle
|
||||
see
|
||||
tsb $02
|
||||
ora $02
|
||||
asl $02
|
||||
rmb0 $02
|
||||
php
|
||||
ora #$01
|
||||
asl
|
||||
tsy
|
||||
tsb $1234
|
||||
ora $1234
|
||||
asl $1234
|
||||
bbr0 $02,*+$34
|
||||
|
||||
bpl *+$32
|
||||
ora ($06),y
|
||||
ora ($07),z
|
||||
lbpl *+$3133 ; bpl *+$3133
|
||||
trb $02
|
||||
ora $03,x
|
||||
asl $03,x
|
||||
rmb1 $02
|
||||
clc
|
||||
ora $1456,y
|
||||
inc
|
||||
inz
|
||||
trb $1234
|
||||
ora $1345,x
|
||||
asl $1345,x
|
||||
bbr1 $02,*+$34
|
||||
|
||||
jsr $1234
|
||||
and ($05,x)
|
||||
jsr ($2345)
|
||||
jsr ($2456,x)
|
||||
bit $02
|
||||
and $02
|
||||
rol $02
|
||||
rmb2 $02
|
||||
plp
|
||||
and #$01
|
||||
rol
|
||||
tys
|
||||
bit $1234
|
||||
and $1234
|
||||
rol $1234
|
||||
bbr2 $02,*+$34
|
||||
|
||||
bmi *+$32
|
||||
and ($06),y
|
||||
and ($07),z
|
||||
lbmi *+$3133 ; bmi *+$3133
|
||||
bit $03,x
|
||||
and $03,x
|
||||
rol $03,x
|
||||
rmb3 $02
|
||||
sec
|
||||
and $1456,y
|
||||
dec
|
||||
dez
|
||||
bit $1345,x
|
||||
and $1345,x
|
||||
rol $1345,x
|
||||
bbr3 $02,*+$34
|
||||
|
||||
rti
|
||||
eor ($05,x)
|
||||
neg
|
||||
asr
|
||||
asr $02
|
||||
eor $02
|
||||
lsr $02
|
||||
rmb4 $02
|
||||
pha
|
||||
eor #$01
|
||||
lsr
|
||||
taz
|
||||
jmp $1234
|
||||
eor $1234
|
||||
lsr $1234
|
||||
bbr4 $02,*+$34
|
||||
|
||||
bvc *+$32
|
||||
eor ($06),y
|
||||
eor ($07),z
|
||||
lbvc *+$3133 ; bvc *+$3133
|
||||
asr $03,x
|
||||
eor $03,x
|
||||
lsr $03,x
|
||||
rmb5 $02
|
||||
cli
|
||||
eor $1456,y
|
||||
phy
|
||||
tab
|
||||
map
|
||||
eor $1345,x
|
||||
lsr $1345,x
|
||||
bbr5 $02,*+$34
|
||||
|
||||
rts
|
||||
adc ($05,x)
|
||||
rtn #$09
|
||||
bsr *+$3133
|
||||
stz $02
|
||||
adc $02
|
||||
ror $02
|
||||
rmb6 $02
|
||||
pla
|
||||
adc #$01
|
||||
ror
|
||||
tza
|
||||
jmp ($2345)
|
||||
adc $1234
|
||||
ror $1234
|
||||
bbr6 $02,*+$34
|
||||
|
||||
bvs *+$32
|
||||
adc ($06),y
|
||||
adc ($07),z
|
||||
lbvs *+$3133 ; bvs *+$3133
|
||||
stz $03,x
|
||||
adc $03,x
|
||||
ror $03,x
|
||||
rmb7 $02
|
||||
sei
|
||||
adc $1456,y
|
||||
ply
|
||||
tba
|
||||
jmp ($2456,x)
|
||||
adc $1345,x
|
||||
ror $1345,x
|
||||
bbr7 $02,*+$34
|
||||
|
||||
bra *+$32
|
||||
sta ($05,x)
|
||||
sta ($0f,s),y
|
||||
sta ($0f,sp),y
|
||||
lbra *+$3133 ; bra *+$3133
|
||||
sty $02
|
||||
sta $02
|
||||
stx $02
|
||||
smb0 $02
|
||||
dey
|
||||
bit #$01
|
||||
txa
|
||||
sty $1345,x
|
||||
sty $1234
|
||||
sta $1234
|
||||
stx $1234
|
||||
bbs0 $02,*+$34
|
||||
|
||||
bcc *+$32
|
||||
sta ($06),y
|
||||
sta ($07),z
|
||||
lbcc *+$3133 ; bcc *+$3133
|
||||
sty $03,x
|
||||
sta $03,x
|
||||
stx $04,y
|
||||
smb1 $02
|
||||
tya
|
||||
sta $1456,y
|
||||
txs
|
||||
stx $1456,y
|
||||
stz $1234
|
||||
sta $1345,x
|
||||
stz $1345,x
|
||||
bbs1 $02,*+$34
|
||||
|
||||
ldy #$01
|
||||
lda ($05,x)
|
||||
ldx #$01
|
||||
ldz #$01
|
||||
ldy $02
|
||||
lda $02
|
||||
ldx $02
|
||||
smb2 $02
|
||||
tay
|
||||
lda #$01
|
||||
tax
|
||||
ldz $1234
|
||||
ldy $1234
|
||||
lda $1234
|
||||
ldx $1234
|
||||
bbs2 $02,*+$34
|
||||
|
||||
bcs *+$32
|
||||
lda ($06),y
|
||||
lda ($07),z
|
||||
lbcs *+$3133 ; bcs *+$3133
|
||||
ldy $03,x
|
||||
lda $03,x
|
||||
ldx $04,y
|
||||
smb3 $02
|
||||
clv
|
||||
lda $1456,y
|
||||
tsx
|
||||
ldz $1345,x
|
||||
ldy $1345,x
|
||||
lda $1345,x
|
||||
ldx $1456,y
|
||||
bbs3 $02,*+$34
|
||||
|
||||
cpy #$01
|
||||
cmp ($05,x)
|
||||
cpz #$01
|
||||
dew $02
|
||||
cpy $02
|
||||
cmp $02
|
||||
dec $02
|
||||
smb4 $02
|
||||
iny
|
||||
cmp #$01
|
||||
dex
|
||||
asw $1234
|
||||
cpy $1234
|
||||
cmp $1234
|
||||
dec $1234
|
||||
bbs4 $02,*+$34
|
||||
|
||||
bne *+$32
|
||||
cmp ($06),y
|
||||
cmp ($07),z
|
||||
lbne *+$3133 ; bne *+$3133
|
||||
cpz $02
|
||||
cmp $03,x
|
||||
dec $03,x
|
||||
smb5 $02
|
||||
cld
|
||||
cmp $1456,y
|
||||
phx
|
||||
phz
|
||||
cpz $1234
|
||||
cmp $1345,x
|
||||
dec $1345,x
|
||||
bbs5 $02,*+$34
|
||||
|
||||
cpx #$01
|
||||
sbc ($05,x)
|
||||
lda ($0f,s),y
|
||||
lda ($0f,sp),y
|
||||
inw $02
|
||||
cpx $02
|
||||
sbc $02
|
||||
inc $02
|
||||
smb6 $02
|
||||
inx
|
||||
sbc #$01
|
||||
eom
|
||||
nop
|
||||
row $1234
|
||||
cpx $1234
|
||||
sbc $1234
|
||||
inc $1234
|
||||
bbs6 $02,*+$34
|
||||
|
||||
beq *+$32
|
||||
sbc ($06),y
|
||||
sbc ($07),z
|
||||
lbeq *+$3133 ; beq *+$3133
|
||||
phd #$089a
|
||||
phw #$089a
|
||||
sbc $03,x
|
||||
inc $03,x
|
||||
smb7 $02
|
||||
sed
|
||||
sbc $1456,y
|
||||
plx
|
||||
plz
|
||||
phd $1234
|
||||
phw $1234
|
||||
sbc $1345,x
|
||||
inc $1345,x
|
||||
bbs7 $02,*+$34
|
||||
|
||||
adc [$12],z
|
||||
|
||||
adcq $12
|
||||
adcq $3456
|
||||
adcq ($78)
|
||||
adcq [$9a]
|
||||
|
||||
and [$12],z
|
||||
|
||||
andq $12
|
||||
andq $3456
|
||||
andq ($78)
|
||||
andq [$9a]
|
||||
|
||||
aslq $12
|
||||
aslq
|
||||
aslq $3456
|
||||
aslq $78,x
|
||||
aslq $9abc,x
|
||||
|
||||
asrq
|
||||
asrq $12
|
||||
asrq $34,x
|
||||
|
||||
bitq $12
|
||||
bitq $3456
|
||||
|
||||
cmp [$12],z
|
||||
|
||||
cmpq $12
|
||||
cmpq $3456
|
||||
cmpq ($78)
|
||||
cmpq [$9a]
|
||||
|
||||
deq
|
||||
deq $12
|
||||
deq $3456
|
||||
deq $78,x
|
||||
deq $9abc,x
|
||||
|
||||
eor [$12],z
|
||||
|
||||
eorq $12
|
||||
eorq $3456
|
||||
eorq ($78)
|
||||
eorq [$9a]
|
||||
|
||||
inq
|
||||
inq $12
|
||||
inq $3456
|
||||
inq $78,x
|
||||
inq $9abc,x
|
||||
|
||||
lda [$12],z
|
||||
|
||||
ldq $12
|
||||
ldq $3456
|
||||
ldq ($78),z
|
||||
ldq [$9a],z
|
||||
|
||||
lsrq $12
|
||||
lsrq
|
||||
lsrq $3456
|
||||
lsrq $78,x
|
||||
lsrq $9abc,x
|
||||
|
||||
ora [$12],z
|
||||
|
||||
orq $12
|
||||
orq $3456
|
||||
orq ($78)
|
||||
orq [$9a]
|
||||
|
||||
rolq $12
|
||||
rolq
|
||||
rolq $3456
|
||||
rolq $78,x
|
||||
rolq $9abc,x
|
||||
|
||||
rorq $12
|
||||
rorq
|
||||
rorq $3456
|
||||
rorq $78,x
|
||||
rorq $9abc,x
|
||||
|
||||
sbc [$12],z
|
||||
|
||||
sbcq $12
|
||||
sbcq $3456
|
||||
sbcq ($78)
|
||||
sbcq [$9a]
|
||||
|
||||
sta [$12],z ; EA 92 12
|
||||
|
||||
stq $12
|
||||
stq $3456
|
||||
stq ($78)
|
||||
stq [$9a]
|
||||
Reference in New Issue
Block a user