fix instruction bitfields. 65CE02 derivates can not use 65SC02, because of the zp-ind-z clash
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@@ -81,15 +81,14 @@ const unsigned CPUIsets[CPU_COUNT] = {
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/* FIXME: does 65816 have both wai/stp and indirect-zp (without z)? */
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CPU_ISET_65816 | CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02,
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CPU_ISET_SWEET16,
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/* FIXME: HUC6280 does not have wai/stp */
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CPU_ISET_HUC6280 | CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02,
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CPU_ISET_M740 | CPU_ISET_6502,
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/* 4510 does NOT have indirect-zp (without z), so we can not use 65SC02 */
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/* FIXME: 4510 does not have wai/stp */
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CPU_ISET_4510 | CPU_ISET_6502 | CPU_ISET_65C02,
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CPU_ISET_45GS02 | CPU_ISET_6502 | CPU_ISET_65C02 | CPU_ISET_4510,
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CPU_ISET_4510 | CPU_ISET_6502 | CPU_ISET_65C02 | CPU_ISET_65CE02,
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CPU_ISET_45GS02 | CPU_ISET_6502 | CPU_ISET_65C02 | CPU_ISET_65CE02 | CPU_ISET_4510,
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CPU_ISET_W65C02 | CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02,
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CPU_ISET_65CE02 | CPU_ISET_6502 | CPU_ISET_65SC02 | CPU_ISET_65C02,
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CPU_ISET_65CE02 | CPU_ISET_6502 | CPU_ISET_65C02,
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};
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