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Mikey enumeration values for cc65 include files and new bit definitions for ca65

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This commit is contained in:
Alex Thissen
2024-08-09 13:11:02 +02:00
committed by Alex Thissen
parent 394d3b1964
commit eb6003aaf7
2 changed files with 430 additions and 172 deletions
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347
asminc/lynx.inc
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@@ -83,7 +83,7 @@ MATHJ = $FC6F
SPRCTL0 = $FC80
; Sprite bits-per-pixel definitions
BPP_MASK = %11000000 ; Mask for settings bits per pixel
BPP_MASK = %11000000 ; Mask for settings bits per pixel
BPP_1 = %00000000
BPP_2 = %01000000
BPP_3 = %10000000
@@ -94,23 +94,23 @@ VFLIP = %00010000
; Sprite types - redefined to reflect the reality caused by the shadow error
TYPE_SHADOW = %00000111
TYPE_XOR = %00000110
TYPE_NONCOLL = %00000101 ; Non-colliding
TYPE_NONCOLL = %00000101 ; Non-colliding
TYPE_NORMAL = %00000100
TYPE_BOUNDARY = %00000011
TYPE_BSHADOW = %00000010 ; Background shadow
TYPE_BACKNONCOLL = %00000001 ; Background non-colliding
TYPE_BSHADOW = %00000010 ; Background shadow
TYPE_BACKNONCOLL = %00000001 ; Background non-colliding
TYPE_BACKGROUND = %00000000
SPRCTL1 = $FC81
LITERAL = %10000000
PACKED = %00000000
ALGO3 = %01000000 ; Broken, do not set this bit!
ALGO3 = %01000000 ; Broken, do not set this bit!
; Sprite reload mask definitions
RELOAD_MASK = %00110000
RENONE = %00000000 ; Reload nothing
REHV = %00010000 ; Reload hsize, vsize
REHVS = %00100000 ; Reload hsize, vsize, stretch
REHVST = %00110000 ; Reload hsize, vsize, stretch, tilt
RENONE = %00000000 ; Reload nothing
REHV = %00010000 ; Reload hsize, vsize
REHVS = %00100000 ; Reload hsize, vsize, stretch
REHVST = %00110000 ; Reload hsize, vsize, stretch, tilt
; More sprite control 1 bit definitions
REUSEPAL = %00001000
SKIP = %00000100
@@ -138,8 +138,9 @@ HOWIE = $FCC4
; *** Mikey Addresses
; ***
; Mikey Timers
; Mikey timers
; Logical timer names
TIMER0 = $FD00
TIMER1 = $FD04
TIMER2 = $FD08
@@ -148,20 +149,20 @@ TIMER4 = $FD10
TIMER5 = $FD14
TIMER6 = $FD18
TIMER7 = $FD1C
HTIMER = $FD00 ; horizontal line timer (timer 0)
VTIMER = $FD08 ; vertical blank timer (timer 2)
STIMER = $FD1C ; sound timer (timer 7)
HTIMER = TIMER0 ; horizontal line timer (timer 0)
VTIMER = TIMER2 ; vertical blank timer (timer 2)
STIMER = TIMER7 ; sound timer (timer 7)
HTIMBKUP = $FD00 ; horizontal line timer (timer 0)
HTIMBKUP = $FD00 ; horizontal line timer (timer 0)
HTIMCTLA = $FD01
HTIMCNT = $FD02
HTIMCTLB = $FD03
VTIMBKUP = $FD08 ; vertical blank timer (timer 2)
VTIMBKUP = $FD08 ; vertical blank timer (timer 2)
VTIMCTLA = $FD09
VTIMCNT = $FD0A
VTIMCTLB = $FD0B
BAUDBKUP = $FD10 ; serial timer (timer 4)
STIMBKUP = $FD1C ; sound timer (timer 7)
BAUDBKUP = $FD10 ; serial timer (timer 4)
STIMBKUP = $FD1C ; sound timer (timer 7)
STIMCTLA = $FD1D
STIMCNT = $FD1E
STIMCTLB = $FD1F
@@ -199,129 +200,227 @@ TIM7CTLA = $FD1D
TIM7CNT = $FD1E
TIM7CTLB = $FD1F
; Timer offsets
TIM_BACKUP = 0
TIM_CONTROLA = 1
TIM_COUNT = 2
TIM_CONTROLB = 3
; TIM_CONTROLA control bits
ENABLE_INT = %10000000
RESET_DONE = %01000000
ENABLE_RELOAD = %00010000
ENABLE_COUNT = %00001000
AUD_CLOCK_MASK = %00000111
; Clock settings
AUD_LINKING = %00000111
AUD_64 = %00000110
AUD_32 = %00000101
AUD_16 = %00000100
AUD_8 = %00000011
AUD_4 = %00000010
AUD_2 = %00000001
AUD_1 = %00000000
; TIM_CONTROLB control bits
TIMER_DONE = %00001000
LAST_CLOCK = %00000100
BORROW_IN = %00000010
BORROW_OUT = %00000001
; Mikey Audio
AUDIO0 = $FD20 ; audio channel 0
AUDIO1 = $FD28 ; audio channel 1
AUDIO2 = $FD30 ; audio channel 2
AUDIO3 = $FD38 ; audio channel 3
AUDIO0 = $FD20 ; audio channel 0
AUDIO1 = $FD28 ; audio channel 1
AUDIO2 = $FD30 ; audio channel 2
AUDIO3 = $FD38 ; audio channel 3
AUD0VOL = $FD20
AUD0FEED = $FD21
AUD0OUT = $FD22
AUD0SHIFT = $FD23
AUD0BKUP = $FD24
AUD0CTLA = $FD25
AUD0CNT = $FD26
AUD0CTLB = $FD27
AUD1VOL = $FD28
AUD1FEED = $FD29
AUD1OUT = $FD2A
AUD1SHIFT = $FD2B
AUD1BKUP = $FD2C
AUD1CTLA = $FD2D
AUD1CNT = $FD2E
AUD1CTLB = $FD2F
AUD2VOL = $FD30
AUD2FEED = $FD31
AUD2OUT = $FD32
AUD2SHIFT = $FD33
AUD2BKUP = $FD34
AUD2CTLA = $FD35
AUD2CNT = $FD36
AUD2CTLB = $FD37
AUD3VOL = $FD38
AUD3FEED = $FD39
AUD3OUT = $FD3A
AUD3SHIFT = $FD3B
AUD3BKUP = $FD3C
AUD3CTLA = $FD3D
AUD3CNT = $FD3E
AUD3CTLB = $FD3F
AUD0VOL = $FD20
AUD0FEED = $FD21
AUD0OUT = $FD22
AUD0SHIFT = $FD23
AUD0BKUP = $FD24
AUD0CTLA = $FD25
AUD0CNT = $FD26
AUD0CTLB = $FD27
AUD1VOL = $FD28
AUD1FEED = $FD29
AUD1OUT = $FD2A
AUD1SHIFT = $FD2B
AUD1BKUP = $FD2C
AUD1CTLA = $FD2D
AUD1CNT = $FD2E
AUD1CTLB = $FD2F
AUD2VOL = $FD30
AUD2FEED = $FD31
AUD2OUT = $FD32
AUD2SHIFT = $FD33
AUD2BKUP = $FD34
AUD2CTLA = $FD35
AUD2CNT = $FD36
AUD2CTLB = $FD37
AUD3VOL = $FD38
AUD3FEED = $FD39
AUD3OUT = $FD3A
AUD3SHIFT = $FD3B
AUD3BKUP = $FD3C
AUD3CTLA = $FD3D
AUD3CNT = $FD3E
AUD3CTLB = $FD3F
; AUD_CONTROL bits are almost identical to TIM_CONTROLA bits.
; See TIM_CONTROLA above for the other definitions
FEEDBACK_7 = %10000000
ENABLE_INTEGRATE = %00100000
; Stereo control registers follow
; Stereo capability does not exist in all Lynxes
; Left and right may be reversed, and if so will be corrected in a later
; release
ATTENREG0 = $FD40 ; Stereo attenuation registers
ATTENREG1 = $FD41
ATTENREG2 = $FD42
ATTENREG3 = $FD43
LEFT_ATTENMASK = %11110000
RIGHT_ATTENMASK = %00001111
; Bit definitions for MPAN and MSTEREO registers
LEFT3_SELECT = %10000000
LEFT2_SELECT = %01000000
LEFT1_SELECT = %00100000
LEFT0_SELECT = %00010000
RIGHT3_SELECT = %00001000
RIGHT2_SELECT = %00000100
RIGHT1_SELECT = %00000010
RIGHT0_SELECT = %00000001
MPAN = $FD44
MSTEREO = $FD50
; Mikey Misc
; Interrupt bits in INTRST and INTSET
TIMER0_INTERRUPT = $01
TIMER1_INTERRUPT = $02
TIMER2_INTERRUPT = $04
TIMER3_INTERRUPT = $08
TIMER4_INTERRUPT = $10
TIMER5_INTERRUPT = $20
TIMER6_INTERRUPT = $40
TIMER7_INTERRUPT = $80
HBL_INTERRUPT = TIMER0_INTERRUPT
VBL_INTERRUPT = TIMER2_INTERRUPT
SERIAL_INTERRUPT = TIMER4_INTERRUPT
SND_INTERRUPT = TIMER7_INTERRUPT
; Mikey interrupts
INTRST = $FD80
INTSET = $FD81
MAGRDY0 = $FD84
MAGRDY1 = $FD85
AUDIN = $FD86
SYSCTL1 = $FD87
MIKEYHREV = $FD88
MIKEYSREV = $FD89
; Interrupt bits in INTRST and INTSET
TIMER0_INTERRUPT = %00000001
TIMER1_INTERRUPT = %00000010
TIMER2_INTERRUPT = %00000100
TIMER3_INTERRUPT = %00001000
TIMER4_INTERRUPT = %00010000
TIMER5_INTERRUPT = %00100000
TIMER6_INTERRUPT = %01000000
TIMER7_INTERRUPT = %10000000
IODIR = $FD8A
IODAT = $FD8B
HBL_INTERRUPT = TIMER0_INTERRUPT
VBL_INTERRUPT = TIMER2_INTERRUPT
SERIAL_INTERRUPT = TIMER4_INTERRUPT
SND_INTERRUPT = TIMER7_INTERRUPT
MAGRDY0 = $FD84
MAGRDY1 = $FD85
AUDIN = $FD86
SYSCTL1 = $FD87
; SYSCTL1 bit definitions
POWERON = %00000010
CART_ADDR_STROBE = %00000001
MIKEYHREV = $FD88
MIKEYSREV = $FD89
IODIR = $FD8A
IODAT = $FD8B
; IODIR and IODAT bit definitions
AUDIN_BIT = $10 ; Note that there is also the address AUDIN
READ_ENABLE = $10 ; Same bit for AUDIN_BIT
RESTLESS = $08
NOEXP = $04 ; If set, redeye is not connected
CART_ADDR_DATA = $02
CART_POWER_OFF = $02 ; Same bit for CART_ADDR_DATA
EXTERNAL_POWER = $01
AUDIN_BIT = %00010000 ; Note that there is also the address AUDIN
READ_ENABLE = %00010000 ; Same bit for AUDIN_BIT
RESTLESS = %00001000
NOEXP = %00000100 ; If set, redeye is not connected
CART_ADDR_DATA = %00000010
CART_POWER_OFF = %00000010 ; Same bit for CART_ADDR_DATA
EXTERNAL_POWER = %00000001
SERCTL = $FD8C
SERCTL = $FD8C
; SERCTL bit definitions for write operations
TXINTEN = $80
RXINTEN = $40
PAREN = $10
RESETERR = $08
TXOPEN = $04
TXBRK = $02
PAREVEN = $01
TXINTEN = %10000000
RXINTEN = %01000000
PAREN = %00010000
RESETERR = %00001000
TXOPEN = %00000100
TXBRK = %00000010
PAREVEN = %00000001
; SERCTL bit definitions for read operations
TXRDY = $80
RXRDY = $40
TXEMPTY = $20
PARERR = $10
OVERRUN = $08
FRAMERR = $04
RXBRK = $02
PARBIT = $01
TXRDY = %10000000
RXRDY = %01000000
TXEMPTY = %00100000
PARERR = %00010000
OVERRUN = %00001000
FRAMERR = %00000100
RXBRK = %00000010
PARBIT = %00000001
SERDAT = $FD8D
SDONEACK = $FD90
CPUSLEEP = $FD91
DISPCTL = $FD92
PBKUP = $FD93
DISPADRL = $FD94
DISPADRH = $FD95
MTEST0 = $FD9C
MTEST1 = $FD9D
MTEST2 = $FD9E
PALETTE = $FDA0 ; hardware rgb palette
GCOLMAP = $FDA0 ; hardware rgb palette (green)
RBCOLMAP = $FDB0 ; hardware rgb palette (red-blue)
SERDAT = $FD8D
SDONEACK = $FD90
CPUSLEEP = $FD91
DISPCTL = $FD92
; DISPCTL bit definitions
DISP_COLOR = %10000000 ; must be set to 1
DISP_FOURBIT = %01000000 ; must be set to 1
DISP_FLIP = %00100000
DMA_ENABLE = %00010000 ; must be set to 1
PBKUP = $FD93
DISPADRL = $FD94
DISPADRH = $FD95
; ***
; *** Misc Hardware + 6502 vectors
; ***
MTEST0 = $FD9C
; MTEST0 bit definitions
AT_CNT16 = %10000000
AT_TEST = %01000000
XCLKEN = %00100000
UART_TURBO = %00010000
ROM_SEL = %00001000
ROM_TEST = %00000100
M_TEST = %00000010
CPU_TEST = %00000001
MAPCTL = $FFF9
VECTORS = $FFFB
INTVECTL = $FFFE
INTVECTH = $FFFF
RSTVECTL = $FFFC
RSTVECTH = $FFFD
NMIVECTL = $FFFA
NMIVECTH = $FFFB
MTEST1 = $FD9D
; MTEST1 bit definitions
P_CNT16 = %01000000
REF_CNT16 = %00100000
VID_TRIG = %00010000
REF_TRIG = %00001000
VID_DMA_DIS = %00000100
REF_FAST = %00000010
REF_DIS = %00000001
MTEST2 = $FD9E
; MTEST2 bit definitions
V_STROBE = %00010000
V_ZERO = %00001000
H_120 = %00000100
H_ZERO = %00000010
V_BLANKEF = %00000001
PALETTE = $FDA0 ; hardware rgb palette
GCOLMAP = $FDA0 ; hardware rgb palette (green)
RBCOLMAP = $FDB0 ; hardware rgb palette (red-blue)
; Memory mapping control and 6502 vectors
MAPCTL = $FFF9
; MAPCTL bit definitions
TURBO_DISABLE = %10000000
VECTOR_SPACE = %00001000 ; 1 maps RAM into specified space
ROM_SPACE = %00000100
MIKEY_SPACE = %00000010
SUZY_SPACE = %00000001
VECTORS = $FFFB
INTVECTL = $FFFE
INTVECTH = $FFFF
RSTVECTL = $FFFC
RSTVECTH = $FFFD
NMIVECTL = $FFFA
NMIVECTH = $FFFB