5be0b10b62
This PR is the first of two PRs that replaces earlier PRs #2589 and #2590. Due to a git branching mishap it was decided to re-partition the new functionality in two sequential PRs that offer self-contained, new functionality to sim65. The functionality in this first PR extends the sim65 simulator in the following ways: (1) It provides tracing functionality, i.e., the possibility of printing one line of simulator state information per instruction executed. (2) It provides a memory mapped "sim65 control" peripheral that allows control of (a) the tracing functionality, and (b) the cpu mode. (3) It provides command-line options to sim65 to enable the tracing, and to override the CPU mode as specified in the program file header. More detailed information and some discussion can be found in the discussions with the (now retracted) PRs #2589 and #2590. This PR provides the technical infrastructure inside the sim65 simulator program itself. Once this PR is accepted, a follow-up PR will be posted that adds C and assembly-language support for the new tracing and peripheral features so they can be easily accessed from the CC65 compiler and the CA65 assembler; some examples; and the documentation for these features. The lack of the latter, in this pull request, will be addressed then.
126 lines
5.7 KiB
C
126 lines
5.7 KiB
C
/*****************************************************************************/
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/* */
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/* peripherals.h */
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/* */
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/* Memory-mapped peripheral subsystem for the 6502 simulator */
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/* */
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/* */
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/* */
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/* (C) 2024-2025, Sidney Cadot */
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/* */
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/* */
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/* This software is provided 'as-is', without any expressed or implied */
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/* warranty. In no event will the authors be held liable for any damages */
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/* arising from the use of this software. */
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/* */
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/* Permission is granted to anyone to use this software for any purpose, */
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/* including commercial applications, and to alter it and redistribute it */
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/* freely, subject to the following restrictions: */
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/* */
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/* 1. The origin of this software must not be misrepresented; you must not */
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/* claim that you wrote the original software. If you use this software */
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/* in a product, an acknowledgment in the product documentation would be */
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/* appreciated but is not required. */
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/* 2. Altered source versions must be plainly marked as such, and must not */
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/* be misrepresented as being the original software. */
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/* 3. This notice may not be removed or altered from any source */
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/* distribution. */
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/* */
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/*****************************************************************************/
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#ifndef PERIPHERALS_H
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#define PERIPHERALS_H
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#include <stdint.h>
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/* The memory range where the memory-mapped peripherals can be accessed. */
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#define PERIPHERALS_APERTURE_BASE_ADDRESS 0xffc0
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#define PERIPHERALS_APERTURE_LAST_ADDRESS 0xffcb
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/* Declarations for the COUNTER peripheral */
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#define PERIPHERALS_COUNTER_ADDRESS_OFFSET_LATCH 0x00
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#define PERIPHERALS_COUNTER_ADDRESS_OFFSET_SELECT 0x01
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#define PERIPHERALS_COUNTER_ADDRESS_OFFSET_VALUE 0x02
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#define PERIPHERALS_COUNTER_LATCH (PERIPHERALS_APERTURE_BASE_ADDRESS + PERIPHERALS_ADDRESS_OFFSET_COUNTER_LATCH)
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#define PERIPHERALS_COUNTER_SELECT (PERIPHERALS_APERTURE_BASE_ADDRESS + PERIPHERALS_ADDRESS_OFFSET_COUNTER_SELECT)
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#define PERIPHERALS_COUNTER_VALUE (PERIPHERALS_APERTURE_BASE_ADDRESS + PERIPHERALS_ADDRESS_OFFSET_COUNTER)
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#define PERIPHERALS_COUNTER_SELECT_CLOCKCYCLE_COUNTER 0x00
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#define PERIPHERALS_COUNTER_SELECT_INSTRUCTION_COUNTER 0x01
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#define PERIPHERALS_COUNTER_SELECT_IRQ_COUNTER 0x02
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#define PERIPHERALS_COUNTER_SELECT_NMI_COUNTER 0x03
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#define PERIPHERALS_COUNTER_SELECT_WALLCLOCK_TIME 0x80
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#define PERIPHERALS_COUNTER_SELECT_WALLCLOCK_TIME_SPLIT 0x81
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typedef struct {
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/* The invisible counters that keep processor state. */
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uint64_t ClockCycles;
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uint64_t CpuInstructions;
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uint64_t IrqEvents;
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uint64_t NmiEvents;
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/* The 'latched_...' fields below hold values that are sampled upon a write
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* to the PERIPHERALS_COUNTER_LATCH address.
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* One of these will be visible (read only) through an eight-byte aperture.
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* The purpose of these latched registers is to read 64-bit values one byte
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* at a time, without having to worry that their content will change along
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* the way.
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*/
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uint64_t LatchedClockCycles;
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uint64_t LatchedCpuInstructions;
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uint64_t LatchedIrqEvents;
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uint64_t LatchedNmiEvents;
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uint64_t LatchedWallclockTime;
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uint64_t LatchedWallclockTimeSplit;
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/* Select which of the six latched registers will be visible.
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* This is a single byte, read/write register, accessible via address
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* PERIPHERALS_COUNTER_SELECT. If a non-existent latch register is selected,
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* the PERIPHERALS_COUNTER_VALUE will be zero.
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*/
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uint8_t LatchedValueSelected;
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} CounterPeripheral;
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/* Declarations for the SIMCONTROL peripheral. */
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#define PERIPHERALS_SIMCONTROL_ADDRESS_OFFSET_CPUMODE 0x0A
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#define PERIPHERALS_SIMCONTROL_ADDRESS_OFFSET_TRACEMODE 0x0B
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#define PERIPHERALS_SIMCONTROL_CPUMODE (PERIPHERALS_APERTURE_BASE_ADDRESS + PERIPHERALS_SIMCONTROL_ADDRESS_OFFSET_CPUMODE)
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#define PERIPHERALS_SIMCONTROL_TRACEMODE (PERIPHERALS_APERTURE_BASE_ADDRESS + PERIPHERALS_SIMCONTROL_ADDRESS_OFFSET_TRACEMODE)
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/* Declare the 'Sim65Peripherals' type and its single instance 'Peripherals'. */
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typedef struct {
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/* State of the peripherals available in sim65. */
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CounterPeripheral Counter;
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} Sim65Peripherals;
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extern Sim65Peripherals Peripherals;
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/*****************************************************************************/
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/* Code */
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/*****************************************************************************/
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void PeripheralsWriteByte (uint8_t Addr, uint8_t Val);
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/* Write a byte to a memory location in the peripheral address aperture. */
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uint8_t PeripheralsReadByte (uint8_t Addr);
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/* Read a byte from a memory location in the peripheral address aperture. */
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void PeripheralsInit (void);
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/* Initialize the peripherals. */
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/* End of peripherals.h */
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#endif
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