997 lines
22 KiB
Plaintext
997 lines
22 KiB
Plaintext
<!doctype linuxdoc system>
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<article>
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<title>ca65/da65 Users Guide
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<author><url url="mailto:uz@cc65.org" name="Ullrich von Bassewitz">,<newline>
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<url url="mailto:groepaz@gmx.net" name="Groepaz">
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<abstract>
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An Overview on all supported CPUs
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</abstract>
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<!-- Table of contents -->
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<toc>
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<!-- Begin the document -->
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<sect>Overview<p>
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<itemize>
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<item><ref id="6502-mode" name="6502"> - NMOS 6502 (all legal instructions)
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<item><ref id="6502X-mode" name="6502X"> - NMOS 6502 with all undocumented instructions
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<item><ref id="DTV-mode" name="6502DTV"> - the CPU of the C64 DTV device
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<item><ref id="65SC02-mode" name="65SC02"> - original CMOS
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<item><ref id="65C02-mode" name="65C02"> - CMOS with Rockwell extensions
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<item><ref id="65CE02-mode" name="65CE02"> - CMOS with CSG extensions
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<item><ref id="W65C02-mode" name="W65C02"> - CMOS with WDC extensions
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<item><ref id="4510-mode" name="4510"> - the CPU of the Commodore C65
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<item><ref id="45GS02-mode" name="45GS02"> - the CPU of the Commodore MEGA65
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<item><ref id="HUC6280-mode" name="HuC6280"> - the CPU of the PC engine
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<item><ref id="M740-mode" name="M740"> - a Microcontroller by Mitsubishi
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<item><ref id="65816-mode" name="65816"> - the CPU of the SNES, and the SCPU
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<item><ref id="sweet16-mode" name="Sweet16"> - an interpreter for a pseudo 16 bit CPU
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</itemize>
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<sect>NMOS branch<p>
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<sect1>6502<label id="6502-mode"><p>
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The original NMOS 6502 CPU.
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For Example: MOS MCS6502 Rev. D, Rockwell R6502, Synertek SY6502, UMC UM6502
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(56 instructions, 151 opcodes)
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<tscreen><verb>
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$00 brk
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$01 ora (zp,x)
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$05 ora zp
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$06 asl zp
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$08 php
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$09 ora #imm
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$0a asl a
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$0d ora addr
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$0e asl addr
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$10 bpl rel80
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$11 ora (zp),y
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$15 ora zp,x
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$16 asl zp,x
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$18 clc
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$19 ora addr,y
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$1d ora addr,x
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$1e asl addr,x
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$20 jsr addr
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$21 and (zp,x)
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$24 bit zp
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$25 and zp
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$26 rol zp
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$28 plp
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$29 and #imm
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$2a rol a
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$2c bit addr
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$2d and addr
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$2e rol addr
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$30 bmi rel8
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$31 and (zp),y
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$35 and zp,x
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$36 rol zp,x
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$38 sec
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$39 and addr,y
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$3d and addr,x
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$3e rol addr,x
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$40 rti
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$41 eor (zp,x)
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$45 eor zp
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$46 lsr zp
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$48 pha
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$49 eor #imm
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$4a lsr a
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$4c jmp addr
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$4d eor addr
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$4e lsr addr
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$50 bvc rel8
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$51 eor (zp),y
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$55 eor zp,x
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$56 lsr zp,x
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$58 cli
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$59 eor addr,y
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$5d eor addr,x
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$5e lsr addr,x
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$60 rts
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$61 adc (zp,x)
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$65 adc zp
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$66 ror zp
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$68 pla
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$69 adc #imm
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$6a ror a
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$6c jmp (addr)
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$6d adc addr
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$6e ror addr
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$70 bvs rel8
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$71 adc (zp),y
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$75 adc zp,x
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$76 ror zp,x
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$78 sei
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$79 adc addr,y
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$7d adc addr,x
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$7e ror addr,x
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$81 sta (zp,x)
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$84 sty zp
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$85 sta zp
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$86 stx zp
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$88 dey
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$8a txa
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$8c sty addr
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$8d sta addr
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$8e stx addr
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$90 bcc rel8
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$91 sta (zp),y
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$94 sty zp,x
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$95 sta zp,x
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$96 stx zp,y
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$98 tya
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$99 sta addr,y
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$9a txs
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$9d sta addr,x
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$a0 ldy #imm
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$a1 lda (zp,x)
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$a2 ldx #imm
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$a4 ldy zp
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$a5 lda zp
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$a6 ldx zp
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$a8 tay
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$a9 lda #imm
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$aa tax
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$ac ldy addr
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$ad lda addr
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$ae ldx addr
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$b0 bcs rel8
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$b1 lda (zp),y
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$b4 ldy zp,x
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$b5 lda zp,x
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$b6 ldx zp,y
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$b8 clv
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$b9 lda addr,y
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$ba tsx
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$bc ldy addr,x
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$bd lda addr,x
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$be ldx addr,y
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$c0 cpy #imm
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$c1 cmp (zp,x)
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$c4 cpy zp
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$c5 cmp zp
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$c6 dec zp
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$c8 iny
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$c9 cmp #imm
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$ca dex
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$cc cpy addr
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$cd cmp addr
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$ce dec addr
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$d0 bne rel8
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$d1 cmp (zp),y
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$d5 cmp zp,x
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$d6 dec zp,x
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$d8 cld
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$d9 cmp addr,y
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$dd cmp addr,x
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$de dec addr,x
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$e0 cpx #imm
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$e1 sbc (zp,x)
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$e4 cpx zp
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$e5 sbc zp
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$e6 inc zp
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$e8 inx
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$e9 sbc #imm
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$ea nop
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$ec cpx addr
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$ed sbc addr
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$ee inc addr
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$f0 beq rel81
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$f1 sbc (zp),y
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$f5 sbc zp,x
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$f6 inc zp,x
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$f8 sed
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$f9 sbc addr,y
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$fd sbc addr,x
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$fe inc addr,x
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</verb></tscreen>
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<sect1>6502X<label id="6502X-mode"><p>
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6502X mode is an extension to the normal 6502 mode. In this mode, several
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mnemonics for undocumented instructions of the NMOS 6502 CPUs are accepted.
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Note: Since these instructions are undocumented, there are no official mnemonics
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for them.
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(20 new instructions, 105 new opcodes, 76 instructions/256 opcodes total)
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<itemize>
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<item><tt>ALR: A:=(A and #imm)/2;</tt>
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<item><tt>ANC: A:= A and #imm;</tt> Generates opcode $0B.
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<item><tt>ANE: A:= (A or CONST) and X and #imm;</tt>
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<item><tt>ARR: A:=(A and #imm)/2;</tt>
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<item><tt>AXS: X:=A and X-#imm;</tt>
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<item><tt>DCP: addr:=addr-1; A-addr;</tt>
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<item><tt>ISC: addr:=addr+1; A:=A-addr;</tt>
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<item><tt>JAM:</tt>
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<item><tt>LAS: A,X,S:=addr and S;</tt>
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<item><tt>LAX: A,X:=addr;</tt>
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<item><tt>NOP: #imm; zp; zp,x; abs; abs,x</tt>
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<item><tt>RLA: addr:=addrrol; A:=A and addr;</tt>
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<item><tt>RRA: addr:=addrror; A:=A adc addr;</tt>
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<item><tt>SAX: addr:=A and X;</tt>
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<item><tt>SHA: addr:=A and X and {addr hi +1};</tt>
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<item><tt>SHX: addr:=X and {addr hi +1};</tt>
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<item><tt>SHY: addr:=Y and {addr hi +1};</tt>
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<item><tt>SLO: addr:=addr*2; A:=A or addr;</tt>
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<item><tt>SRE: addr:=addr/2; A:=A xor addr;</tt>
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<item><tt>TAS: addr:=A and X and {addr hi +1}; SP:=A and X;</tt>
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</itemize>
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<tscreen><verb>
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$02 jam
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$03 slo (zp,x)
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$04 nop zp
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$07 slo zp
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$0b anc #imm
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$0c nop addr
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$0f slo addr
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$12 jam
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$13 slo (zp),y
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$14 nop zp,x
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$17 slo zp,y
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$1a nop
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$1b slo addr,y
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$1c nop addr,x
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$1f slo addr,x
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$22 jam
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$23 rla (zp,x)
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$27 rla zp
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$2b anc #imm
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$2f rla addr
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$32 jam
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$33 rla (zp),y
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$34 nop zp,x
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$37 rla zp,y
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$3a nop
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$3b rla addr,y
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$3c nop addr,x
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$3f rla addr,x
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$42 jam
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$43 sre (zp,x)
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$44 nop zp
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$47 sre zp
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$4b alr #imm
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$4f sre addr
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$52 jam
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$53 sre (zp),y
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$54 nop zp,x
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$57 sre zp,y
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$5a nop
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$5b sre addr,y
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$5c nop addr,x
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$5f sre addr,x
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$62 jam
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$63 rra (zp,x)
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$64 nop zp
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$67 rra zp
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$6b arr #imm
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$6f rra addr
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$72 jam
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$73 rra (zp),y
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$74 nop zp,x
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$77 rra zp,y
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$7a nop
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$7b rra addr,y
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$7c nop addr,x
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$7f rra addr,x
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$80 nop #imm
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$82 nop #imm
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$83 sax (zp,x)
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$87 sax zp
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$89 nop #imm
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$8b ane #imm
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$8f sax addr
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$92 jam
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$93 sha (zp),y
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$97 sax zp,y
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$9b tas addr,y
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$9c shy addr,x
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$9e shx addr,y
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$9f sha addr,y
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$a3 lax (zp,x)
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$a7 lax zp
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$ab lax #imm
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$af lax addr
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$b2 jam
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$b3 lax (zp),y
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$b7 lax zp,y
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$bb las addr,y
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$bf lax addr,y
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$c2 nop #imm
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$c3 dcp (zp,x)
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$c7 dcp zp
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$cb axs #imm
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$cf dcp addr
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$d2 jam
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$d3 dcp (zp),y
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$d4 nop zp,x
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$d7 dcp zp,y
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$da nop
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$db dcp addr,y
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$dc nop addr,x
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$df dcp addr,x
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$e2 nop #imm
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$e3 isc (zp,x)
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$e7 isc zp
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$eb sbc #imm
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$ef isc addr
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$f2 jam
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$f3 isc (zp),y
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$f4 nop zp,x
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$f7 isc zp,y
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$fa nop
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$fb isc addr,y
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$fc nop addr,x
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$ff isc addr,x
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</verb></tscreen>
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<sect1>6502DTV<label id="DTV-mode"><p>
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The CPU of the C64 DTV is based on the 6510. It adds some instructions, and does
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not support all undocumented 6510 instructions.
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(3+10 new instructions, 3+56 new opcodes, 69 instructions/210 opcodes total)
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Opcodes added over 6502 (these are JAM on 6502):
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<tscreen><verb>
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$12 bra rel8
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$32 sac #imm
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$42 sir #imm
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</verb></tscreen>
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Supported undocumented 6510 instructions (nop, anc, rla, lax, las, alr, arr,
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rra, shy, shx, axs, sbc):
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<tscreen><verb>
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$04 nop zp
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$0b anc #imm
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$0c nop addr
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$14 nop zp,x
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$1a nop
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$1c nop addr,x
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$23 rla (zp,x)
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$27 rla zp
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$2b anc #imm
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$2f rla addr
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$33 rla (zp),y
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$34 nop zp,x
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$37 rla zp,y
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$3a nop
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$3b rla addr,y
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$3c nop addr,x
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$3f rla addr,x
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$44 nop zp
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$4b alr #imm
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$54 nop zp,x
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$5a nop
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$5c nop addr,x
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$63 rra (zp,x)
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$64 nop zp
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$67 rra zp
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$6b arr #imm
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$6f rra addr
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$73 rra (zp),y
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$74 nop zp,x
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$77 rra zp,y
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$7a nop
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$7b rra addr,y
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$7c nop addr,x
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$7f rra addr,x
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$80 nop #imm
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$82 nop #imm
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$89 nop #imm
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$9c shy addr,x
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$9e shx addr,y
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$a3 lax (zp,x)
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$a7 lax zp
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$ab lax #imm
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$af lax addr
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$b3 lax (zp),y
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$b7 lax zp,y
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$bb las addr,y
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$bf lax addr,y
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$c2 nop #imm
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$cb axs #imm
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$d4 nop zp,x
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$da nop
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$dc nop addr,x
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$e2 nop #imm
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$eb sbc #imm
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$f4 nop zp,x
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$fa nop
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$fc nop addr,x
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</verb></tscreen>
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<sect>CMOS branch<p>
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The original CMOS version was apparently developed already back in the Commodore
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days, but never saw the light of day. It was then licensed by (now) WDC to
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different other vendors. Unfortunately some of those named their chips "65C02"
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(not SC), which causes a lot of confusion now. So keep that in mind: some chips
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that are named "65C02" will only support the original 65SC02 instruction set.
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<sect1>65SC02 (Original CMOS)<label id="65SC02-mode"><p>
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The first CMOS instruction set, without bit manipulation, nor wai/stp. It adds
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8 new instructions (phx, phy, plx, ply, bra, stz, tsb, trb) and two new address
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modes (zeropage-indirect, absolute-x-indexed-indirect) to the original (legal)
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6502 instructions.
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For example: Synertek SY65C02, GTE G65SC02, CMD G65SC02, NCR 65C02
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(8 new instructions, 27 new opcodes, 64 instructions/178 opcodes total)
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<tscreen><verb>
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$04 tsb zp
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$0c tsb abs16
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$12 ora (zp)
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$14 trb zp
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$1a inc
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$1c trb abs16
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$32 and (zp)
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$34 bit zp, x
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$3a dec
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$3c bit abs16, x
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$52 eor (zp)
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$5a phy
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$64 stz zp
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$72 adc (zp)
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$74 stz zp, x
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$7a ply
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$7c jmp (abs16, x)
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$80 bra rel8
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$89 bit #imm8
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$92 sta (zp)
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$9c stz abs16
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$9e stz abs16, x
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$b2 lda (zp)
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$d2 cmp (zp)
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$da phx
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$f2 sbc (zp)
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$fa plx
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</verb></tscreen>
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<sect1>65C02 (CMOS with Rockwell extensions)<label id="65C02-mode"><p>
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The Rockwell extensions add additional bit manipulation and bit test-and-branch
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commands to the original 65SC02 instruction set.
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For Example: Rockwell R65C02, Ricoh RP65C02, NCR 65CX02
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(4 new instructions, 32 new opcodes, 68 instructions/210 opcodes total)
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<tscreen><verb>
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$07 rmb0 zp clear bit in zp location
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$0f bbr0 zp, rel8 branch if bit is not set in zp location
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$17 rmb1 zp
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$1f bbr1 zp, rel8
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$27 rmb2 zp
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$2f bbr2 zp, rel8
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$37 rmb3 zp
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$3f bbr3 zp, rel8
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$47 rmb4 zp
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$4f bbr4 zp, rel8
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$57 rmb5 zp
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$5f bbr5 zp, rel8
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$67 rmb6 zp
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$6f bbr6 zp, rel8
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$77 rmb7 zp
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$7f bbr7 zp, rel8
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$87 smb0 zp set bit in zp location
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$8f bbs0 zp, rel8 branch if bit is set in zp location
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$97 smb1 zp
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$9f bbs1 zp, rel8
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$a7 smb2 zp
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$af bbs2 zp, rel8
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$b7 smb3 zp
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$bf bbs3 zp, rel8
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$c7 smb4 zp
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$cf bbs4 zp, rel8
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$d7 smb5 zp
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$df bbs5 zp, rel8
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$e7 smb6 zp
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$ef bbs6 zp, rel8
|
|
$f7 smb7 zp
|
|
$ff bbs7 zp, rel8
|
|
</verb></tscreen>
|
|
|
|
All "illegal" opcodes perform NOP on this CPU.
|
|
|
|
|
|
|
|
<sect1>W65C02 (CMOS with WDC extensions)<label id="W65C02-mode"><p>
|
|
|
|
For their W65C02S WDC took the Rockwell extensions, and added two extra
|
|
instructions (which they also added to the 65C816/65C802)
|
|
|
|
(2 new instructions, 2 new opcodes, 70 instructions/212 opcodes total)
|
|
|
|
<tscreen><verb>
|
|
$cb wai wait for interrupt
|
|
$db stp wait for reset
|
|
</verb></tscreen>
|
|
|
|
All "illegal" opcodes perform NOP on this CPU.
|
|
|
|
|
|
|
|
<sect1>65CE02 (CMOS with CSG extensions)<label id="65CE02-mode"><p>
|
|
|
|
CSG took the Rockwell extensions and developed them further. Notable additions
|
|
are long relative branches/jumps, and finally a real z register. Note that the
|
|
two opcodes used by the WDC extensions have been repurposed for something else,
|
|
so the 65CE02 is not 100% compatible with the W65C02.
|
|
|
|
For Example: CSG 65CE02 (used on the Amiga A2232 Serial Card)
|
|
|
|
(34 new instructions, 46 new opcodes, 102 instructions/256 opcodes total)
|
|
|
|
<tscreen><verb>
|
|
$02 cle clear stack extend disable
|
|
$03 see set stack extend disable
|
|
$0b tsy transfer stack_ptr_high to Y
|
|
$12 ora (zp), z
|
|
$13 lbpl rel16
|
|
$1b inz increment Z
|
|
$22 jsr (abs16)
|
|
$23 jsr (abs16, x)
|
|
$2b tys transfer Y to stack_ptr_high
|
|
$32 and (zp), z
|
|
$33 lbmi rel16
|
|
$3b dez decrement Z
|
|
$42 neg negate A
|
|
$43 asr
|
|
$44 asr zp
|
|
$4b taz transfer A to Z
|
|
$52 eor (zp), z
|
|
$53 lbvc rel16
|
|
$54 asr zp, x
|
|
$5b tab
|
|
$5c aug "4-byte NOP reserved for future expansion"
|
|
$62 rtn #imm8
|
|
$63 lbsr rel16 relative jsr, "branch to subroutine"
|
|
$64 stz zp store Z
|
|
$6b tza transfer Z to A
|
|
$72 adc (zp), z
|
|
$73 lbvs rel16
|
|
$74 stz zp, x store Z
|
|
$7b tba
|
|
$82 sta (off8, s), y
|
|
$83 lbra rel16 relative jmp
|
|
$8b sty abs16, x
|
|
$92 sta (zp), z
|
|
$93 lbcc rel16
|
|
$9b stx abs16, y
|
|
$9c stz abs16 store Z
|
|
$9e stz abs16, x store Z
|
|
$a3 ldz #imm8
|
|
$ab ldz abs16
|
|
$b2 lda (zp), z
|
|
$b3 lbcs rel16
|
|
$bb ldz abs16, x
|
|
$c2 cpz #imm8
|
|
$c3 dew zp
|
|
$cb asw abs16
|
|
$d2 cmp (zp), z
|
|
$d3 lbne rel16
|
|
$d4 cpz zp
|
|
$db phz push Z
|
|
$dc cpz abs16
|
|
$e2 lda (off8, s), y
|
|
$e3 inw zp
|
|
$eb row abs16
|
|
$f2 sbc (zp), z
|
|
$f3 lbeq rel16
|
|
$f4 phw #imm16
|
|
$fb plz pull Z
|
|
$fc phw abs16
|
|
</verb></tscreen>
|
|
|
|
One notable change is that some instructions of the original CMOS instruction set
|
|
were changed from "zeropage indirect" addressing to "zeropage indirect, z indexed".
|
|
This could be done, because the z register is initially guaranteed to be zero,
|
|
making the CPU binary compatible with older CMOS variants.
|
|
|
|
<tscreen><verb>
|
|
$12 ora (zp) -> ora (zp), z
|
|
$32 and (zp) -> and (zp), z
|
|
$52 eor (zp) -> eor (zp), z
|
|
$72 adc (zp) -> adc (zp), z
|
|
$92 sta (zp) -> sta (zp), z
|
|
$b2 lda (zp) -> cmp (zp), z
|
|
$d2 cmp (zp) -> lda (zp), z
|
|
$f2 sbc (zp) -> sbc (zp), z
|
|
</verb></tscreen>
|
|
|
|
Additional to that, the meaning of the following instruction changes from "store
|
|
zero" to "store z register". Again, this makes the CPU binary compatible with
|
|
older CMOS variants
|
|
|
|
<tscreen><verb>
|
|
$64 stz zp
|
|
$74 stz zp, x
|
|
$9c stz abs16
|
|
$9e stz abs16, x
|
|
</verb></tscreen>
|
|
|
|
The other 65SC02 instructions (phx, phy, plx, ply, tsb, trb, bra) are unchanged.
|
|
|
|
|
|
|
|
<sect1>4510<label id="4510-mode"><p>
|
|
|
|
The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX.
|
|
It contains among other functions a slightly modified 65CE02/4502 CPU, to allow
|
|
address mapping for 20 bits of address space (1 megabyte addressable area).
|
|
|
|
The 4510 supports the complete 65CE02 instruction set, but changes
|
|
the 4-Byte NOP into the "map" instruction:
|
|
|
|
<tscreen><verb>
|
|
$5c map
|
|
</verb></tscreen>
|
|
|
|
For more information about the Commodore C65/C64DX and the 4510 CPU, see
|
|
<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/"> and
|
|
<url url="https://en.wikipedia.org/wiki/Commodore_65" name="Wikipedia">.
|
|
|
|
|
|
|
|
<sect1>45GS02<label id="45GS02-mode"><p>
|
|
|
|
The 45GS02 is a microcontroller that is the core of the MEGA65.
|
|
It is an extension of the 4510 CPU and adds 32-bit addressing and a 32-bit
|
|
pseudo register Q that is comprised of the four registers A, X, Y, and Z.
|
|
|
|
<tscreen><verb>
|
|
$42 $42 $05 orq zp
|
|
$42 $42 $06 aslq zp
|
|
$42 $42 $0a aslq
|
|
$42 $42 $0d orq addr
|
|
$42 $42 $0e aslq addr
|
|
$42 $42 $12 orq (zp)
|
|
$42 $42 $16 aslq zp,x
|
|
$42 $42 $1a inq
|
|
$42 $42 $1e aslq addr,x
|
|
$42 $42 $24 bitq zp
|
|
$42 $42 $25 andq zp
|
|
$42 $42 $26 rolq zp
|
|
$42 $42 $2a rolq
|
|
$42 $42 $2c bitq addr
|
|
$42 $42 $2d andq addr
|
|
$42 $42 $2e rolq addr
|
|
$42 $42 $32 andq (zp)
|
|
$42 $42 $36 rolq zp, x
|
|
$42 $42 $3a deq
|
|
$42 $42 $3e rolq addr, x
|
|
$42 $42 $43 asrq
|
|
$42 $42 $44 asrq zp
|
|
$42 $42 $45 eorq zp
|
|
$42 $42 $46 lsrq zp
|
|
$42 $42 $4a lsrq
|
|
$42 $42 $4d eorq addr
|
|
$42 $42 $4e lsrq addr
|
|
$42 $42 $52 eorq (zp)
|
|
$42 $42 $54 asrq zp, x
|
|
$42 $42 $56 lsrq zp, x
|
|
$42 $42 $5e lsrq addr, x
|
|
$42 $42 $65 adcq zp
|
|
$42 $42 $66 rorq zp
|
|
$42 $42 $6a rorq
|
|
$42 $42 $6d adcq addr
|
|
$42 $42 $6e rorq addr
|
|
$42 $42 $72 adcq (zp)
|
|
$42 $42 $76 rorq zp, x
|
|
$42 $42 $7e rorq addr, x
|
|
$42 $42 $85 stq zp
|
|
$42 $42 $8d stq addr
|
|
$42 $42 $92 stq (zp)
|
|
$42 $42 $a5 ldq zp
|
|
$42 $42 $ad ldq addr
|
|
$42 $42 $b2 ldq (zp), z
|
|
$42 $42 $c5 cmpq zp
|
|
$42 $42 $c6 deq zp
|
|
$42 $42 $cd cmpq addr
|
|
$42 $42 $ce deq addr
|
|
$42 $42 $d2 cmpq (zp)
|
|
$42 $42 $d6 deq zp, x
|
|
$42 $42 $de deq addr, x
|
|
$42 $42 $e5 sbcq zp
|
|
$42 $42 $e6 inq zp
|
|
$42 $42 $ed sbcq addr
|
|
$42 $42 $ee inq addr
|
|
$42 $42 $f2 sbcq (zp)
|
|
$42 $42 $f6 inq zp, x
|
|
$42 $42 $fe inq addr, x
|
|
|
|
$ea $12 ora [zp], z
|
|
$ea $32 and [zp], z
|
|
$ea $52 eor [zp], z
|
|
$ea $72 adc [zp], z
|
|
$ea $92 sta [zp], z
|
|
$ea $b2 lda [zp], z
|
|
$ea $d2 cmp [zp], z
|
|
$ea $f2 sbc [zp], z
|
|
|
|
$42 $42 $ea $12 orq [zp]
|
|
$42 $42 $ea $32 andq [zp]
|
|
$42 $42 $ea $52 eorq [zp]
|
|
$42 $42 $ea $72 adcq [zp]
|
|
$42 $42 $ea $92 stq [zp]
|
|
$42 $42 $ea $b2 ldq [zp], z
|
|
$42 $42 $ea $d2 cmpq [zp]
|
|
$42 $42 $ea $f2 sbcq [zp]
|
|
</verb></tscreen>
|
|
|
|
|
|
<sect1>HUC6280<label id="HUC6280-mode"><p>
|
|
|
|
The HUC6280 is a superset of 65C02. It implements the original CMOS instructions
|
|
with Rockwell extensions, plus some other instructions:
|
|
|
|
<tscreen><verb>
|
|
$02 sxy
|
|
$03 st0 #imm
|
|
$13 st1 #imm
|
|
$22 sax
|
|
$23 st2 #imm
|
|
$42 say
|
|
$43 tma #imm
|
|
$44 bsr rel8
|
|
$53 tam #imm
|
|
$54 csl
|
|
$62 cla
|
|
$73 tii addr, addr, addr
|
|
$82 clx
|
|
$83 tst #imm, zp
|
|
$82 clx
|
|
$83 tst #imm, zp
|
|
$93 tst #imm, addr
|
|
$a3 tst #imm, zp, x
|
|
$b3 tst #imm, addr, x
|
|
$c2 cly
|
|
$c3 tdd addr, addr, addr
|
|
$d3 tin addr, addr, addr
|
|
$d4 csh
|
|
$e3 tia addr, addr, addr
|
|
$f3 tai addr, addr, addr
|
|
$f4 set
|
|
</verb></tscreen>
|
|
|
|
|
|
<sect1>M740<label id="M740-mode"><p>
|
|
|
|
The M740 is a microcontroller by Mitsubishi, which was marketed for embedded
|
|
devices in the mid 80s. It is a superset of 6502, the added CMOS instructions
|
|
seem to be completely custom however:
|
|
|
|
<tscreen><verb>
|
|
$02 jsr (zp)
|
|
$03 bbs0 a, rel8
|
|
$07 bbs0 zp, rel8
|
|
$0b seb0 a
|
|
$0f seb0 zp
|
|
$12 clt
|
|
$13 bbc0 a, rel8
|
|
$17 bbc0 zp, rel8
|
|
$1a inc a
|
|
$1b clb0 a
|
|
$1f clb0 zp
|
|
$22 jsr $ff12
|
|
$23 bbs1 a, rel8
|
|
$27 bbs1 zp, rel8
|
|
$2b seb1 a
|
|
$2f seb1 zp
|
|
$32 set
|
|
$33 bbc1 a, rel8
|
|
$37 bbc1 zp, rel8
|
|
$3a dec a
|
|
$3b clb1 a
|
|
$3c ldm zp, #imm
|
|
$3f clb1 zp
|
|
$42 stp
|
|
$43 bbs2 a, rel8
|
|
$44 com zp
|
|
$47 bbs2 zp, rel8
|
|
$4b seb2 a
|
|
$4f seb2 zp
|
|
$53 bbc2 a, rel8
|
|
$57 bbc2 zp, rel8
|
|
$5b clb2 a
|
|
$5f clb2 zp
|
|
$63 bbs3 a, rel8
|
|
$64 tst zp
|
|
$67 bbs3 zp, rel8
|
|
$6b seb3 a
|
|
$6f seb3 zp
|
|
$73 bbc3 a, rel8
|
|
$77 bbc3 zp, rel8
|
|
$7b clb3 a
|
|
$7f clb3 zp
|
|
$80 bra rel8
|
|
$82 rrf zp
|
|
$83 bbs4 a, rel8
|
|
$87 bbs4 zp, rel8
|
|
$8b seb4 a
|
|
$8f seb4 zp
|
|
$93 bbc4 a, rel8
|
|
$97 bbc4 zp, rel8
|
|
$9b clb4 a
|
|
$9f clb4 zp
|
|
$a3 bbs5 a, rel8
|
|
$a7 bbs5 zp, rel8
|
|
$ab seb5 a
|
|
$af seb5 zp
|
|
$b2 lda (zp)
|
|
$b3 bbc5 a, rel8
|
|
$b7 bbc5 zp, rel8
|
|
$bb clb5 a
|
|
$bf clb5 zp
|
|
$c2 slw
|
|
$c3 bbs6 a, rel8
|
|
$c7 bbs6 zp, rel8
|
|
$cb seb6 a
|
|
$cf seb6 zp
|
|
$d3 bbc6 a, rel8
|
|
$d7 bbc6 zp, rel8
|
|
$db clb6 a
|
|
$df clb6 zp
|
|
$e2 fst
|
|
$e3 bbs7 a, rel8
|
|
$e7 bbs7 zp, rel8
|
|
$eb seb7 a
|
|
$ef seb7 zp
|
|
$f3 bbc7 a, rel8
|
|
$f7 bbc7 zp, rel8
|
|
$fb clb7 a
|
|
$ff clb7 zp
|
|
</verb></tscreen>
|
|
|
|
Four instructions are the same on 65SC02:
|
|
|
|
<tscreen><verb>
|
|
$1a inc a
|
|
$3a dec a
|
|
$80 bra rel8
|
|
$b2 lda (zp)
|
|
</verb></tscreen>
|
|
|
|
These four instructions are different from 65SC02:
|
|
|
|
<tscreen><verb>
|
|
$12 ora (zp) -> clt
|
|
$32 and (zp) -> set
|
|
$3c bit addr,x -> ldm zp, #imm
|
|
$64 stz zp -> tst zp
|
|
</verb></tscreen>
|
|
|
|
The following 65SC02 instructions are not implemented:
|
|
|
|
<tscreen><verb>
|
|
$04 tsb zp
|
|
$0c tsb addr
|
|
$14 trb zp
|
|
$1c trb addr
|
|
$34 bit zp,y
|
|
$52 eor (zp)
|
|
$5a phy
|
|
$72 adc (zp)
|
|
$74 stz zp,y
|
|
$7a ply
|
|
$7c jmp (addr)
|
|
$89 bit #imm8
|
|
$92 sta (zp)
|
|
$9c stz addr
|
|
$9e stz addr,x
|
|
$d2 cmp (zp)
|
|
$da phx
|
|
$f2 sbc (zp)
|
|
$fa plx
|
|
</verb></tscreen>
|
|
|
|
|
|
|
|
For more information about the M740 Controllers, see
|
|
<url url="https://en.wikipedia.org/wiki/Mitsubishi_740" name="Wikipedia">.
|
|
|
|
|
|
|
|
<sect1>65816<label id="65816-mode"><p><p>
|
|
|
|
The 65816 is a 16bit CPU developed by WDC.
|
|
|
|
<sect>other<p>
|
|
|
|
<sect1>Sweet16<label id="sweet16-mode"><p><p>
|
|
|
|
SWEET 16 is an interpreter for a pseudo 16 bit CPU written by Steve Wozniak
|
|
for the Apple ][ machines. It is available in the Apple ][ ROM.
|
|
|
|
It implements the following opcodes:
|
|
|
|
<tscreen><verb>
|
|
00 1 RTN (Return to 6502 mode)
|
|
01 2 BR ea (Branch always)
|
|
02 2 BNC ea (Branch if No Carry)
|
|
03 2 BC ea (Branch if Carry)
|
|
04 2 BP ea (Branch if Plus)
|
|
05 2 BM ea (Branch if Minus)
|
|
06 2 BZ ea (Branch if Zero)
|
|
07 2 BNZ ea (Branch if NonZero)
|
|
08 2 BM1 ea (Branch if Minus 1)
|
|
09 2 BNM1 ea (Branch if Not Minus 1)
|
|
0A 1 BK (Break to Monitor)
|
|
0B 1 RS (Return from Subroutine)
|
|
0C 1 BS ea (Branch to Subroutine)
|
|
1n 3 SET Rn R<-2 byte constant (Set Constant) (load register immediate)
|
|
2n 1 LD Rn ACC<-R (Load)
|
|
3n 1 ST Rn ACC->R (Store)
|
|
4n 1 LD @Rn ACC<-@R, R<-R+1 (Load Indirect)
|
|
5n 1 ST @Rn ACC->@R, R<-R+1 (Store Indirect)
|
|
6n 1 LDD @Rn ACC<-@R double (Load Double Indirect)
|
|
7n 1 STD @Rn ACC->@R double (Store Double Indirect)
|
|
8n 1 POP @Rn R<-R-1, ACC<-@R (pop) (Pop Indirect)
|
|
9n 1 STP @Rn R<-R-1, ACC->@R (Store POP Indirect)
|
|
An 1 ADD Rn ACC<-@R (pop) double (Add)
|
|
Bn 1 SUB Rn compare ACC to R (Sub)
|
|
Cn 1 POPD @Rn ACC<-ACC+R (Pop Double Indirect)
|
|
Dn 1 CPR Rn ACC<-ACC-R (Compare)
|
|
En 1 INR Rn R<-R+1 (Increment)
|
|
Fn 1 DCR Rn R<-R-1 (Decrement)
|
|
</verb></tscreen>
|
|
|
|
For more information about SWEET 16, see
|
|
<url url="http://www.6502.org/source/interpreters/sweet16.htm">.
|
|
|
|
|
|
|
|
<sect>Copyright<p>
|
|
|
|
ca65 (and all cc65 binutils) are (C) Copyright 1998-2003 Ullrich von
|
|
Bassewitz. For usage of the binaries and/or sources the following
|
|
conditions do apply:
|
|
|
|
This software is provided 'as-is', without any expressed or implied
|
|
warranty. In no event will the authors be held liable for any damages
|
|
arising from the use of this software.
|
|
|
|
Permission is granted to anyone to use this software for any purpose,
|
|
including commercial applications, and to alter it and redistribute it
|
|
freely, subject to the following restrictions:
|
|
|
|
<enum>
|
|
<item> The origin of this software must not be misrepresented; you must not
|
|
claim that you wrote the original software. If you use this software
|
|
in a product, an acknowledgment in the product documentation would be
|
|
appreciated but is not required.
|
|
<item> Altered source versions must be plainly marked as such, and must not
|
|
be misrepresented as being the original software.
|
|
<item> This notice may not be removed or altered from any source
|
|
distribution.
|
|
</enum>
|
|
|
|
|
|
|
|
</article>
|