190 lines
4.8 KiB
ArmAsm
190 lines
4.8 KiB
ArmAsm
;
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; Colin Leroy-Mira <colin@colino.net>, 2025
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;
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; unsigned char __fastcall__ get_tv(void)
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;
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.export _get_tv
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.import _set_iigs_speed, _get_iigs_speed
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.import ostype
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.constructor calibrate_tv, 8 ; After ostype
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.include "accelerator.inc"
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.include "apple2.inc"
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.include "get_tv.inc"
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.segment "ONCE"
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; Cycle wasters
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waste_72:
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jsr waste_36
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waste_36:
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jsr waste_12
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waste_24:
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jsr waste_12
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waste_12:
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rts
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.proc calibrate_tv
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lda ostype
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bmi iigs
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cmp #$20
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bcc iip
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cmp #$40
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bcc iie
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iic: jmp calibrate_iic
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iigs: jmp calibrate_iigs
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iie: jmp calibrate_iie
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iip: rts ; Keep TV::OTHER.
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.endproc
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; Magic numbers
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WASTE_LOOP_CYCLES = 92 ; The wait loop total cycles
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NTSC_LOOP_COUNT = 17030/WASTE_LOOP_CYCLES ; How many loops expected on NTSC
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PAL_LOOP_COUNT = 20280/WASTE_LOOP_CYCLES ; How many loops expected on PAL
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STOP_PTRIG = 16500/WASTE_LOOP_CYCLES ; Stop PTRIG at 16.5ms
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; Carry set at enter: wait for VBL +
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; Carry clear at enter: wait for VBL -
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; Increments X every 92 cycles.
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.proc count_until_vbl_bit
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lda #$10 ; BPL
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bcc :+
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lda #$30 ; BMI
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: sta sign
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; Wait for VBLsign change with 92 cycles loops.
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; Hit PTRIG repeatedly so that accelerators will slow down.
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; But stop hitting PTRIG after 16.5ms cycles, so that on the //c,
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; the VBLINT will not be reset right before we get it. 16.5ms
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; is a good value because it's far enough from 17ms for NTSC
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; models, and close enough to 20.2ms for PAL models that accelerators
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; will stay slow until there. (5ms usually).
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: cpx #STOP_PTRIG ; 2 - see if we spent 16.5ms already
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bcs notrig ; 4 / 5 - if so, stop hitting PTRIG
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sta PTRIG ; 8 - otherwise hit it
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bcc count ; 11
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notrig:
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nop ; 7 - keep cycle count constant when not
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nop ; 9 - hitting PTRIG
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nop ; 11
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count:
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inx ; 13
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jsr waste_72 ; 85
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bit RDVBLBAR ; 89 - Wait for VBL change
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sign:
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bpl :- ; 92 - patched with bpl/bmi
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rts
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.endproc
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.proc calibrate_iic
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php
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sei
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sta IOUDISOFF
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lda RDVBLMSK
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pha ; Back up for cleanup
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bit ENVBL
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bit PTRIG ; Reset VBL interrupt flag
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: bit RDVBLBAR ; Wait for one VBL
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bpl :-
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bit PTRIG ; Reset VBL interrupt flag again
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ldx #$00
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clc
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jsr count_until_vbl_bit
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pla ; Cleanup
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asl
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bcs :+ ; VBL interrupts were already enabled
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bit DISVBL
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: sta IOUDISON ; IIc Tech Ref Man: The firmware normally leaves IOUDIS on.
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plp
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jmp calibrate_done
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.endproc
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.proc calibrate_iie
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: bit RDVBLBAR ; Wait for bit 7 to be off (VBL start)
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bmi :-
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: bit RDVBLBAR ; Wait for bit 7 to be on (VBL end)
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bpl :-
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; Wait and count during a full cycle
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ldx #$00
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sec
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jsr count_until_vbl_bit
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clc
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jsr count_until_vbl_bit
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jmp calibrate_done
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.endproc
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.proc calibrate_iigs
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; Backup speed and slow down
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jsr _get_iigs_speed
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pha
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lda #SPEED_SLOW
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jsr _set_iigs_speed
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; The same as IIe, but reverted, because... something?
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: bit RDVBLBAR ; Wait for bit 7 to be on (VBL start)
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bpl :-
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: bit RDVBLBAR ; Wait for bit 7 to be off (VBL end)
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bmi :-
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; Wait and count during a full cycle
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ldx #$00
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clc
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jsr count_until_vbl_bit
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sec
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jsr count_until_vbl_bit
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jsr calibrate_done
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; Restore user speed
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pla
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jmp _set_iigs_speed
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.endproc
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.proc calibrate_done
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; Consider X +/- 3 to be valid,
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; anything else is unknown.
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lda #TV::NTSC
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cpx #NTSC_LOOP_COUNT-3
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bcc unexpected
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cpx #NTSC_LOOP_COUNT+3
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bcc matched
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lda #TV::PAL
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cpx #PAL_LOOP_COUNT-3
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bcc unexpected
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cpx #PAL_LOOP_COUNT+3
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bcs unexpected
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matched:
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sta tv
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unexpected:
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rts
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.endproc
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.code
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; The only thing remaining from that code after init
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.proc _get_tv
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lda tv
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ldx #>$0000
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rts
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.endproc
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.segment "INIT"
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tv: .byte TV::OTHER
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