423 lines
12 KiB
Plaintext
423 lines
12 KiB
Plaintext
<!doctype linuxdoc system>
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<article>
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<title>ca65/da65 Users Guide
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<author><url url="mailto:uz@cc65.org" name="Ullrich von Bassewitz">,<newline>
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<url url="mailto:groepaz@gmx.net" name="Groepaz">
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<abstract>
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An Overview on all supported CPUs
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</abstract>
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<!-- Table of contents -->
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<toc>
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<!-- Begin the document -->
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<sect>Overview<p>
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<sect1>Supported CPUs<p>
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<itemize>
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<item><ref id="6502-mode" name="6502"> - NMOS 6502 (all legal instructions)
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<item><ref id="6502X-mode" name="6502X"> - NMOS 6502 with all undocumented instructions
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<item><ref id="DTV-mode" name="6502DTV"> - the emulated CPU of the C64DTV device
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<item><ref id="65SC02-mode" name="65SC02"> - first CMOS instruction set (no bit manipulation)
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<item><ref id="65C02-mode" name="65C02"> - full CMOS instruction set (has bit manipulation)
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<item><ref id="W65C02-mode" name="W65C02"> - CMOS with WDC extensions
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<item><ref id="65CE02-mode" name="65CE02"> - CMOS with GTE extensions
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<item><ref id="65816-mode" name="65816"> - the CPU of the SNES, and the SCPU
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<item><ref id="HUC6280-mode" name="HuC6280"> - the CPU of the PC engine
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<item><ref id="4510-mode" name="4510"> - the CPU of the Commodore C65
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<item><ref id="45GS02-mode" name="45GS02"> - the CPU of the Commodore MEGA65
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<item><ref id="M740-mode" name="M740"> - a Microcontroller by Mitsubishi
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<item><ref id="sweet16-mode" name="Sweet16"> - an interpreter for a pseudo 16 bit CPU
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</itemize>
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<sect2>6502 mode<label id="6502-mode"><p>
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The default (no CPU given on the command line or in the <tt/GLOBAL/ section of
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the info file) is the 6502 CPU. The disassembler knows all "official" opcodes
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for this CPU. Invalid opcodes are translated into <tt/.byte/ commands.
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<sect2>6502X mode<label id="6502X-mode"><p>
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6502X mode is an extension to the normal 6502 mode. In this mode, several
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mnemonics for undocumented instructions of the NMOS 6502 CPUs are accepted.
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Note: Since these instructions are undocumented, there are no official mnemonics
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for them.
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<itemize>
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<item><tt>ALR: A:=(A and #{imm})/2;</tt>
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<item><tt>ANC: A:= A and #{imm};</tt> Generates opcode $0B.
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<item><tt>ANE: A:= (A or CONST) and X and #{imm};</tt>
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<item><tt>ARR: A:=(A and #{imm})/2;</tt>
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<item><tt>AXS: X:=A and X-#{imm};</tt>
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<item><tt>DCP: {addr}:={addr}-1; A-{addr};</tt>
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<item><tt>ISC: {addr}:={addr}+1; A:=A-{addr};</tt>
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<item><tt>JAM:</tt>
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<item><tt>LAS: A,X,S:={addr} and S;</tt>
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<item><tt>LAX: A,X:={addr};</tt>
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<item><tt>NOP: #{imm}; zp; zp,x; abs; abs,x</tt>
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<item><tt>RLA: {addr}:={addr}rol; A:=A and {addr};</tt>
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<item><tt>RRA: {addr}:={addr}ror; A:=A adc {addr};</tt>
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<item><tt>SAX: {addr}:=A and X;</tt>
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<item><tt>SHA: {addr}:=A and X and {addr hi +1};</tt>
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<item><tt>SHX: {addr}:=X and {addr hi +1};</tt>
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<item><tt>SHY: {addr}:=Y and {addr hi +1};</tt>
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<item><tt>SLO: {addr}:={addr}*2; A:=A or {addr};</tt>
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<item><tt>SRE: {addr}:={addr}/2; A:=A xor {addr};</tt>
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<item><tt>TAS: {addr}:=A and X and {addr hi +1}; SP:=A and X;</tt>
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</itemize>
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<sect2>DTV mode<label id="DTV-mode"><p>
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The C64DTV CPU is based on the 6510, but adds some instructions, and does not
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support all undocumented instructions.
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<itemize>
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<item><tt>bra {rel}</tt> Generates opcode $12.
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<item><tt>sac #{imm}</tt> Generates opcode $32.
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<item><tt>sir #{imm}</tt> Generates opcode $42.
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</itemize>
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Supported undocumented instructions:
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<itemize>
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<item><tt>ALR: A:=(A and #{imm})/2;</tt>
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<item><tt>ANC: A:=A and #{imm};</tt> Generates opcode $0B.
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<item><tt>ARR: A:=(A and #{imm})/2;</tt>
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<item><tt>AXS: X:=A and X-#{imm};</tt>
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<item><tt>LAS: A,X,S:={addr} and S;</tt>
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<item><tt>LAX: A,X:={addr};</tt>
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<item><tt>NOP: #{imm}; zp; zp,x; abs; abs,x</tt>
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<item><tt>RLA: {addr}:={addr}rol; A:=A and {addr};</tt>
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<item><tt>RRA: {addr}:={addr}ror; A:=A adc {addr};</tt>
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<item><tt>SHX: {addr}:=X and {addr hi +1};</tt>
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<item><tt>SHY: {addr}:=y and {addr hi +1};</tt>
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</itemize>
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<sect2>65SC02 (Original CMOS)<label id="65SC02-mode"><p>
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The first CMOS instruction set, without bit manipulation or wai/stp.
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<tscreen><verb>
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$04 tsb zp
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$0c tsb abs16
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$12 ora (zp)
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$14 trb zp
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$1a inc
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$1c trb abs16
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$32 and (zp)
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$34 bit zp, x
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$3a dec
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$3c bit abs16, x
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$52 eor (zp)
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$5a phy
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$64 stz zp
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$72 adc (zp)
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$74 stz zp, x
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$7a ply
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$7c jmp (abs16, x)
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$80 bra rel8
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$89 bit #imm8
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$92 sta (zp)
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$9c stz abs16
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$9e stz abs16, x
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$b2 lda (zp)
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$d2 cmp (zp)
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$da phx
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$f2 sbc (zp)
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$fa plx
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</verb></tscreen>
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<sect2>65C02 (CMOS with Rockwell extensions)<label id="65C02-mode"><p>
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The 65C02 understands the same opcodes as the 65SC02, plus 16 additional bit
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manipulation and bit test-and-branch commands.
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The R65C02 adds bit manipulation instructions:
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<tscreen><verb>
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smbB zp set bit in zp location
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rmbB zp reset bit in zp location
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bbsB zp, rel8 branch if bit is set in zp location
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bbrB zp, rel8 branch if bit is reset in zp location
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</verb></tscreen>
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<sect2>W65C02 (CMOS with WDC extensions)<label id="W65C02-mode"><p>
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This mode also supports wai/stp.
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<tscreen><verb>
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$cb wai wait for interrupt
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$db stp wait for reset
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</verb></tscreen>
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<sect2>65CE02 (CMOS with GTE extensions)<label id="65CE02-mode"><p>
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<tscreen><verb>
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$02 cle clear stack extend disable
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$03 see set stack extend disable
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$0b tsy transfer stack_ptr_high to Y
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$12 ora (zp), z
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$13 lbpl rel16
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$1b inz increment Z
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$22 jsr (abs16)
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$23 jsr (abs16, x)
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$2b tys transfer Y to stack_ptr_high
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$32 and (zp), z
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$33 lbmi rel16
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$3b dez decrement Z
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$42 neg negate A
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$43 asr
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$44 asr zp
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$4b taz transfer A to Z
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$52 eor (zp), z
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$53 lbvc rel16
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$54 asr zp, x
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$5b tab
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$5c aug "4-byte NOP reserved for future expansion"
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$62 rtn #imm8
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$63 lbsr rel16 relative jsr, "branch to subroutine"
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$64 stz zp store Z
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$6b tza transfer Z to A
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$72 adc (zp), z
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$73 lbvs rel16
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$74 stz zp, x store Z
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$7b tba
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$82 sta (off8, s), y
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$83 lbra rel16 relative jmp
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$8b sty abs16, x
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$92 sta (zp), z
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$93 lbcc rel16
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$9b stx abs16, y
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$9c stz abs16 store Z
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$9e stz abs16, x store Z
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$a3 ldz #imm8
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$ab ldz abs16
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$b2 lda (zp), z
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$b3 lbcs rel16
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$bb ldz abs16, x
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$c2 cpz #imm8
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$c3 dew zp
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$cb asw abs16
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$d2 cmp (zp), z
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$d3 lbne rel16
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$d4 cpz zp
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$db phz push Z
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$dc cpz abs16
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$e2 lda (off8, s), y
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$e3 inw zp
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$eb row abs16
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$f2 sbc (zp), z
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$f3 lbeq rel16
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$f4 phw #imm16
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$fb plz pull Z
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$fc phw abs16
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</verb></tscreen>
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<sect2>4510 mode<label id="4510-mode"><p>
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The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX.
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It contains among other functions a slightly modified 65CE02/4502 CPU, to allow
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address mapping for 20 bits of address space (1 megabyte addressable area).
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The 4510 mode supports the complete (legal) 65CE02 instruction set, but changes
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the 4-Byte NOP into the "map" instruction:
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<tscreen><verb>
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$5c map "4-byte NOP reserved for future expansion" on 65CE02
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</verb></tscreen>
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For more information about the Commodore C65/C64DX and the 4510 CPU, see
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<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/"> and
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<url url="https://en.wikipedia.org/wiki/Commodore_65" name="Wikipedia">.
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<sect2>45GS02 mode<label id="45GS02-mode"><p>
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The 45GS02 is a microcontroller that is the core of the MEGA65.
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It is an extension of the 4510 CPU and adds 32-bit addressing and a 32-bit
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pseudo register Q that is comprised of the four registers A, X, Y, and Z.
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<tscreen><verb>
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$42 $42 $05 orq $12
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$42 $42 $06 aslq $12
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$42 $42 $0a aslq
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$42 $42 $0d orq $1234
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$42 $42 $0e aslq $1234
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$42 $42 $12 orq ($12)
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$42 $42 $16 aslq $12,x
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$42 $42 $1a inq
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$42 $42 $1e aslq $1234,x
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$42 $42 $24 bitq $12
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$42 $42 $25 andq $12
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$42 $42 $26 rolq $12
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$42 $42 $2a rolq
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$42 $42 $2c bitq $1234
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$42 $42 $2d andq $1234
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$42 $42 $2e rolq $1234
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$42 $42 $32 andq ($12)
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$42 $42 $36 rolq $12, x
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$42 $42 $3a deq
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$42 $42 $3e rolq $1234, x
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$42 $42 $43 asrq
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$42 $42 $44 asrq $12
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$42 $42 $45 eorq $12
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$42 $42 $46 lsrq $12
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$42 $42 $4a lsrq
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$42 $42 $4d eorq $1234
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$42 $42 $4e lsrq $1234
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$42 $42 $52 eorq ($12)
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$42 $42 $54 asrq $12, x
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$42 $42 $56 lsrq $12, x
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$42 $42 $5e lsrq $1234, x
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$42 $42 $65 adcq $12
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$42 $42 $66 rorq $12
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$42 $42 $6a rorq
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$42 $42 $6d adcq $1234
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$42 $42 $6e rorq $1234
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$42 $42 $72 adcq ($12)
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$42 $42 $76 rorq $12, x
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$42 $42 $7e rorq $1234, x
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$42 $42 $85 stq $12
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$42 $42 $8d stq $1234
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$42 $42 $92 stq ($12)
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$42 $42 $a5 ldq $12
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$42 $42 $ad ldq $1234
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$42 $42 $b2 ldq ($12), z
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$42 $42 $c5 cmpq $12
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$42 $42 $c6 deq $12
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$42 $42 $cd cmpq $1234
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$42 $42 $ce deq $1234
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$42 $42 $d2 cmpq ($12)
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$42 $42 $d6 deq $12, x
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$42 $42 $de deq $1234, x
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$42 $42 $e5 sbcq $12
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$42 $42 $e6 inq $12
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$42 $42 $ed sbcq $1234
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$42 $42 $ee inq $1234
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$42 $42 $f2 sbcq ($12)
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$42 $42 $f6 inq $12, x
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$42 $42 $fe inq $1234, x
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$ea $12 ora [$12], z
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$ea $32 and [$12], z
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$ea $52 eor [$12], z
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$ea $72 adc [$12], z
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$ea $92 sta [$12], z
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$ea $b2 lda [$12], z
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$ea $d2 cmp [$12], z
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$ea $f2 sbc [$12], z
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$42 $42 $ea $12 orq [$12]
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$42 $42 $ea $32 andq [$12]
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$42 $42 $ea $52 eorq [$12]
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$42 $42 $ea $72 adcq [$12]
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$42 $42 $ea $92 stq [$12]
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$42 $42 $ea $b2 ldq [$12], z
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$42 $42 $ea $d2 cmpq [$12]
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$42 $42 $ea $f2 sbcq [$12]
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</verb></tscreen>
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<sect2>HUC6280 mode<label id="HUC6280-mode"><p>
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The HUC6280 is a superset of 65C02. It adds some other instructions:
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<tscreen><verb>
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$02 sxy
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$03 st0 #{imm}
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$13 st1 #{imm}
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$22 sax
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$23 st2 #{imm}
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$42 say
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$43 tma #{imm}
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$44 bsr {rel}
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$53 tam #{imm}
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$54 csl
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$62 cla
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$73 tii {addr}, {addr}, {addr}
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$82 clx
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$83 tst #{imm}, {zp}
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$82 clx
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$83 tst #{imm}, {zp}
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$93 tst #{imm}, {addr}
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$a3 tst #{imm}, {zp}, x
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$b3 tst #{imm}, {addr}, x
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$c2 cly
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$c3 tdd {addr}, {addr}, {addr}
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$d3 tin {addr}, {addr}, {addr}
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$d4 csh
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$e3 tia {addr}, {addr}, {addr}
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$f3 tai {addr}, {addr}, {addr}
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$f4 set
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</verb></tscreen>
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<sect2>M740 mode<label id="M740-mode"><p>
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The M740 is a microcontroller by Mitsubishi, which was marketed for embedded
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devices in the mid 80s. It is a superset of 6502, and a subset of 65SC02, plus
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some new instructions.
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For more information about the M740 Controllers, see
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<url url="https://en.wikipedia.org/wiki/Mitsubishi_740" name="Wikipedia">.
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<sect2>65816 mode<label id="65816-mode"><p><p>
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The 65816 support requires annotating ranges with the M and X flag states.
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This can be recorded with an emulator that supports Code and Data Logging,
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for example. Disassemble one bank at a time.
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<sect2>Sweet16<label id="sweet16-mode"><p><p>
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SWEET 16 is an interpreter for a pseudo 16 bit CPU written by Steve Wozniak
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for the Apple ][ machines. It is available in the Apple ][ ROM.
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For more information about SWEET 16, see
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<url url="http://www.6502.org/source/interpreters/sweet16.htm">.
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<sect>Copyright<p>
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ca65 (and all cc65 binutils) are (C) Copyright 1998-2003 Ullrich von
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Bassewitz. For usage of the binaries and/or sources the following
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conditions do apply:
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This software is provided 'as-is', without any expressed or implied
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warranty. In no event will the authors be held liable for any damages
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arising from the use of this software.
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Permission is granted to anyone to use this software for any purpose,
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including commercial applications, and to alter it and redistribute it
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freely, subject to the following restrictions:
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<enum>
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<item> The origin of this software must not be misrepresented; you must not
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claim that you wrote the original software. If you use this software
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in a product, an acknowledgment in the product documentation would be
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appreciated but is not required.
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<item> Altered source versions must be plainly marked as such, and must not
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be misrepresented as being the original software.
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<item> This notice may not be removed or altered from any source
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distribution.
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</enum>
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</article>
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