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use sect2 for cpu subsections

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mrdudz
2025-06-21 22:12:53 +02:00
parent 12e40f4aff
commit 4820b716c7
2 changed files with 21 additions and 21 deletions
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22
doc/ca65.sgml
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@@ -468,12 +468,12 @@ byte. If omitted, the assembler will only produce only 1 byte.
brk #$34 ; 2-bytes: $00 $34
</verb></tscreen>
<sect1>6502 mode<label id="6502-mode"><p>
<sect2>6502 mode<label id="6502-mode"><p>
In 6502 mode (which is the default) the assembler accepts all regular "legal"
6502 mnemonics and addressing modes.
<sect1>6502X mode<label id="6502X-mode"><p>
<sect2>6502X mode<label id="6502X-mode"><p>
6502X mode is an extension to the normal 6502 mode. In this mode, several
mnemonics for undocumented instructions of the NMOS 6502 CPUs are accepted.
@@ -505,7 +505,7 @@ for them.
</itemize>
<sect1>DTV mode<label id="DTV-mode"><p>
<sect2>DTV mode<label id="DTV-mode"><p>
The C64DTV CPU is based on the 6510, but adds some instructions, and does not
support all undocumented instructions.
@@ -533,7 +533,7 @@ Supported undocumented instructions:
</itemize>
<sect1>65SC02 mode<label id="65SC02-mode"><p>
<sect2>65SC02 mode<label id="65SC02-mode"><p>
65SC02 mode supports all regular 6502 instructions, plus the following:
@@ -568,7 +568,7 @@ $fa plx
</verb></tscreen>
<sect1>65C02 mode<label id="65C02-mode"><p>
<sect2>65C02 mode<label id="65C02-mode"><p>
65C02 mode supports all "official" W65C02 opcodes.
@@ -589,7 +589,7 @@ $db stp wait for reset
</verb></tscreen>
<sect1>4510 mode<label id="4510-mode"><p>
<sect2>4510 mode<label id="4510-mode"><p>
The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX.
It contains among other functions a slightly modified 65CE02/4502 CPU, to allow
@@ -620,13 +620,13 @@ For more information about the Commodore C65/C64DX and the 4510 CPU, see
<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/"> and
<url url="https://en.wikipedia.org/wiki/Commodore_65" name="Wikipedia">.
<sect1>45GS02 mode<label id="45GS02-mode"><p>
<sect2>45GS02 mode<label id="45GS02-mode"><p>
The 45GS02 is a microcontroller that is the core of the MEGA65.
It is an extension of the 4510 CPU and adds 32-bit addressing and a 32-bit
pseudo register Q that is comprised of the four registers A, X, Y, and Z.
<sect1>HUC6280 mode<label id="HUC6280-mode"><p>
<sect2>HUC6280 mode<label id="HUC6280-mode"><p>
The HUC6280 is a superset of the R65C02. It adds some other instructions:
@@ -662,7 +662,7 @@ $f4 set
Note that this CPU does not implement <tt>wai</tt> and <tt>stp</tt>.
<sect1>M740 mode<label id="M740-mode"><p>
<sect2>M740 mode<label id="M740-mode"><p>
The M740 is a microcontroller by Mitsubishi, which was marketed for embedded
devices in the mid 80s. It is a superset of 6502, and a subset of 65SC02, plus
@@ -672,7 +672,7 @@ For more information about the M740 Controllers, see
<url url="https://en.wikipedia.org/wiki/Mitsubishi_740" name="Wikipedia">.
<sect1>65816 mode<label id="65816-mode"><p><p>
<sect2>65816 mode<label id="65816-mode"><p><p>
In 65816 mode, several aliases are accepted, in addition to the official
mnemonics:
@@ -700,7 +700,7 @@ or two far addresses whose high byte will be used.
</verb></tscreen>
<sect1>sweet16 mode<label id="sweet16-mode"><p>
<sect2>sweet16 mode<label id="sweet16-mode"><p>
SWEET 16 is an interpreter for a pseudo 16 bit CPU written by Steve Wozniak
for the Apple ][ machines. It is available in the Apple ][ ROM. ca65 can

20
doc/da65.sgml
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@@ -263,28 +263,28 @@ disassembler may be told which CPU to support:
for more details on the various CPUs, see <tt><htmlurl url="ca65.html#6502-mode" name="here"></tt>.
<sect1>6502 mode<label id="6502-mode"><p>
<sect2>6502 mode<label id="6502-mode"><p>
The default (no CPU given on the command line or in the <tt/GLOBAL/ section of
the info file) is the 6502 CPU. The disassembler knows all "official" opcodes
for this CPU. Invalid opcodes are translated into <tt/.byte/ commands.
<sect1>6502X mode<label id="6502X-mode"><p>
<sect2>6502X mode<label id="6502X-mode"><p>
Using 6502X as CPU the illegal opcodes of 6502 CPU are detected and displayed.
<sect1>DTV mode<label id="DTV-mode"><p>
<sect2>DTV mode<label id="DTV-mode"><p>
6502DTV setting recognizes the emulated CPU instructions of the C64DTV device.
<sect1>65SC02 mode<label id="65SC02-mode"><p>
<sect2>65SC02 mode<label id="65SC02-mode"><p>
The first CMOS instruction set, without bit manipulation or wai/stp.
<sect1>65C02 mode<label id="65C02-mode"><p>
<sect2>65C02 mode<label id="65C02-mode"><p>
The 65C02 understands the same opcodes as the 65SC02, plus 16 additional bit
manipulation and bit test-and-branch commands.
@@ -292,7 +292,7 @@ manipulation and bit test-and-branch commands.
This mode also supports wai/stp.
<sect1>4510 mode<label id="4510-mode"><p>
<sect2>4510 mode<label id="4510-mode"><p>
When disassembling 4510 code, due to handling of 16-bit wide branches, da65
can produce output that can not be re-assembled, when one or more of those
@@ -300,22 +300,22 @@ branches point outside of the disassembled memory. This can happen when text
or binary data is processed.
<sect1>45GS02 mode<label id="45GS02-mode"><p>
<sect2>45GS02 mode<label id="45GS02-mode"><p>
All compound instructions are supported.
<sect1>HUC6280 mode<label id="HUC6280-mode"><p>
<sect2>HUC6280 mode<label id="HUC6280-mode"><p>
All special opcodes are supported.
<sect1>M740 mode<label id="M740-mode"><p>
<sect2>M740 mode<label id="M740-mode"><p>
All special opcodes are supported.
<sect1>65816 mode<label id="65816-mode"><p><p>
<sect2>65816 mode<label id="65816-mode"><p><p>
The 65816 support requires annotating ranges with the M and X flag states.
This can be recorded with an emulator that supports Code and Data Logging,