Merge branch 'master' into quietagain

test/asm/cpudetect/allinst.inc

@@ -357,11 +357,10 @@ LABEL:
     .endscope
 .endif
 
-
 ;------------------------------------------------------------------------------
-; The 65c02 is the CMOS re-design of the 6502. It has a few improvements:
+; The 65sc02 is the original CMOS re-design of the 6502.
 ;
-;      65C02            65ce02
+;      65SC02           65ce02
 ;
 ; $04  tsb zp
 ; $0c  tsb abs16
@@ -391,69 +390,42 @@ LABEL:
 ; $f2  sbc (zp)         (-> sbc (zp), z)
 ; $fa  plx
 
-; FIXME: currently CPU_ISET_65SC02 and CPU_65SC02 really means "65C02"
-
-; FIXME: should really check for 65C02
-
 .if (.cpu .bitand CPU_ISET_65SC02)
     .scope
     ; 65c02 instruction set adds some extra legal instructions to 6502
     tsb $12         ; $04
     tsb $1234       ; $0c
-    ;ora ($12)       ; $12  FIXME: not working with 4510:ora (zp), z
+    ora ($12)       ; $12  FIXME: not working with 4510:ora (zp), z
     trb $12         ; $14
     inc a           ; $1a
     trb $1234       ; $1c
-    ;and ($12)       ; $32  FIXME: not working with 4510:and (zp), z
+    and ($12)       ; $32  FIXME: not working with 4510:and (zp), z
     bit $12,x       ; $34
     dec a           ; $3a
     bit $1234,x     ; $3c
-    ;eor ($12)       ; $52  FIXME: not working with 4510:eor (zp), z
+    eor ($12)       ; $52  FIXME: not working with 4510:eor (zp), z
     phy             ; $5a
     stz $12         ; $64
-    ;adc ($12)       ; $72  FIXME: not working with 4510:adc (zp), z
+    adc ($12)       ; $72  FIXME: not working with 4510:adc (zp), z
     stz $12,x       ; $74
     ply             ; $7a
     jmp ($1234)     ; $7c
 LABEL:
     bra LABEL       ; $80
     bit #$12        ; $89
-    ;sta ($12)       ; $92  FIXME: not working with 4510:sta (zp), z
+    sta ($12)       ; $92  FIXME: not working with 4510:sta (zp), z
     stz $1234       ; $9c
     stz $1234,x     ; $9e
-    ;lda ($12)       ; $b2  FIXME: not working with 4510:lda (zp), z
-    ;cmp ($12)       ; $d2  FIXME: not working with 4510:cmp (zp), z
+    lda ($12)       ; $b2  FIXME: not working with 4510:lda (zp), z
+    cmp ($12)       ; $d2  FIXME: not working with 4510:cmp (zp), z
     phx             ; $da
-    ;sbc ($12)       ; $f2  FIXME: not working with 4510:sbc (zp), z
+    sbc ($12)       ; $f2  FIXME: not working with 4510:sbc (zp), z
     plx             ; $fa
     .endscope
 .endif
 
-; FIXME: hack so these opcodes get tested anyway, while 4510 is still quirky
-.if (.cpu .bitand CPU_ISET_65SC02)
-.if (.not .cpu = CPU_4510)
-    ora ($12)       ; $12
-    and ($12)       ; $32
-    eor ($12)       ; $52
-    adc ($12)       ; $72
-    sta ($12)       ; $92
-    lda ($12)       ; $b2
-    cmp ($12)       ; $d2
-    sbc ($12)       ; $f2
-.endif
-.endif
 
-; TODO: R65C02
 ; The R65C02 is a superset of the 65C02. It adds bit manipulation instructions:
-;   smbB zp         set bit in zp location
-;   rmbB zp         reset bit in zp location
-;   bbsB zp, rel8   branch if bit is set in zp location
-;   bbrB zp, rel8   branch if bit is reset in zp location
-
-; FIXME: currently CPU_ISET_65C02 and CPU_65C02 really means "W65C02"
-
-; FIXME: should really check for R65C02
-
 .if (.cpu .bitand CPU_ISET_65C02)
 
     ; R65C02 instruction set adds some extra legal instructions to 65C02
@@ -494,88 +466,17 @@ LABEL3:
 .endif
 
 
-; TODO: W65C02
 ; The W65C02 is a superset of the R65C02. It only adds two instructions:
-;
-; $cb  wai             wait for interrupt
-; $db  stp             wait for reset
-
-; FIXME: currently CPU_ISET_65C02 and CPU_65C02 really means "W65C02"
-
-; FIXME: should really check for W65C02
-
-.if (.cpu = CPU_65C02)
+.if (.cpu .bitand CPU_ISET_W65C02)
     wai             ; $cb
     stp             ; $db
 .endif
 
 
-; TODO: 65CE02
 ; The 65CE02 is another superset of the R65C02. It has several improvements:
-;
-; $02  cle              clear stack extend disable
-; $03  see              set stack extend disable
-; $0b  tsy              transfer stack_ptr_high to Y
-; $12  ora (zp), z
-; $13  lbpl rel16
-; $1b  inz              increment Z
-; $22  jsr (abs16)
-; $23  jsr (abs16, x)
-; $2b  tys              transfer Y to stack_ptr_high
-; $32  and (zp), z
-; $33  lbmi rel16
-; $3b  dez              decrement Z
-; $42  neg              negate A
-; $43  asr
-; $44  asr zp
-; $4b  taz              transfer A to Z
-; $52  eor (zp), z
-; $53  lbvc rel16
-; $54  asr zp, x
-; $5b  tab
-; $5c  aug              "4-byte NOP reserved for future expansion"
-; $62  rtn #imm8
-; $63  lbsr rel16       relative jsr, "branch to subroutine"
-; $64  stz zp           store Z
-; $6b  tza              transfer Z to A
-; $72  adc (zp), z
-; $73  lbvs rel16
-; $74  stz zp, x        store Z
-; $7b  tba
-; $82  sta (off8, s), y
-; $83  lbra rel16       relative jmp
-; $8b  sty abs16, x
-; $92  sta (zp), z
-; $93  lbcc rel16
-; $9b  stx abs16, y
-; $9c  stz abs16        store Z
-; $9e  stz abs16, x     store Z
-; $a3  ldz #imm8
-; $ab  ldz abs16
-; $b2  lda (zp), z
-; $b3  lbcs rel16
-; $bb  ldz abs16, x
-; $c2  cpz #imm8
-; $c3  dew zp
-; $cb  asw abs16
-; $d2  cmp (zp), z
-; $d3  lbne rel16
-; $d4  cpz zp
-; $db  phz              push Z
-; $dc  cpz abs16
-; $e2  lda (off8, s), y
-; $e3  inw zp
-; $eb  row abs16
-; $f2  sbc (zp), z
-; $f3  lbeq rel16
-; $f4  phw #imm16
-; $fb  plz              pull Z
-; $fc  phw abs16
-
-; FIXME: should really check for 65CE02
-
-.if (.cpu .bitand CPU_ISET_4510)
+.if (.cpu .bitand CPU_ISET_65CE02)
     .scope
+
     ; 65CE02 adds the following:
     cle                         ; $02
     see                         ; $03
@@ -649,8 +550,6 @@ LABEL3:
 
     ; added to 65CE02
     map                         ; $5c   ("4-byte NOP reserved for future expansion" on 65CE02)
-    asw $1234                   ; $cb   (wai on W65C02)
-    phz                         ; $db   (stp on W65C02)
     eom                         ; $ea   "end of mapping" - but really just a NOP
 
     .endscope
@@ -896,3 +795,215 @@ LABEL:
     .endscope
 .endif
 
+.if (.cpu .bitand CPU_ISET_65816)
+
+    .smart  -                       ; Stop being smart
+
+    .A8 ; akku 8 bit
+    .I8 ; index registers 8 bit
+
+    .scope
+    cop $12             ; $02  coprocessor operation
+    ora $12, s          ; $03
+    ora [$12]           ; $07
+    phd                 ; $0b  push direct page register
+    ora $123456         ; $0f
+    ora ($12, s), y     ; $13
+    ora [$12], y        ; $17
+    tcs                 ; $1b  transfer C to stack pointer
+    ora $123456, x      ; $1f
+    jsl $123456         ; $22
+    and $12, s          ; $23
+    and [$12]           ; $27
+    pld                 ; $2b  pull direct page register
+    and $123456         ; $2f
+    and ($12, s), y     ; $33
+    and [$12], y        ; $37
+    tsc                 ; $3b  transfer stack pointer to C
+    and $123456, x      ; $3f
+    wdm $12             ; $42  (reserved for future expansion)
+    eor $12, s          ; $43
+    mvp $1234, $5678    ; $44
+    eor [$12]           ; $47
+    phk                 ; $4b  push program bank register
+    eor $123456         ; $4f
+    eor ($12, s), y     ; $53
+    mvn $1234, $5678    ; $54
+    eor [$12], y        ; $57
+    tcd                 ; $5b  transfer C to direct page register
+    jml $123456         ; $5c
+    eor $123456, x      ; $5f
+    per LABEL           ; $62  push effective relative address
+    adc $12, s          ; $63
+    adc [$12]           ; $67
+    rtl                 ; $6b  return long (fetches 24-bit address from stack)
+    adc $123456         ; $6f
+    adc ($12, s), y     ; $73
+    adc [$12], y        ; $77
+    tdc                 ; $7b  transfer direct page register to C
+    adc $123456, x      ; $7f
+LABEL:
+    brl LABEL           ; $82  branch long (16-bit offset)
+    sta $12, s          ; $83
+    sta [$12]           ; $87
+    phb                 ; $8b  push data bank register
+    sta $123456         ; $8f
+    sta ($12, s), y     ; $93
+    sta [$12], y        ; $97
+    txy                 ; $9b  transfer X to Y
+    sta $123456, x      ; $9f
+    lda $12, s          ; $a3
+    lda [$12]           ; $a7
+    plb                 ; $ab  pull data bank register
+    lda $123456         ; $af
+    lda ($12, s), y     ; $b3
+    lda [$12], y        ; $b7
+    tyx                 ; $bb  transfer Y to X
+    lda $123456, x      ; $bf
+    rep #$12            ; $c2  clear bits in status register
+    cmp $12, s          ; $c3
+    cmp [$12]           ; $c7
+    wai                 ; $cb  wait for interrupt
+    cmp $123456         ; $cf
+    cmp ($12, s), y     ; $d3
+    pei ($12)           ; $d4  push effective indirect address
+    cmp [$12], y        ; $d7
+    stp                 ; $db  wait for reset
+    jmp [$1234]         ; $dc
+    cmp $123456, x      ; $df
+    sep #$12            ; $e2  set bits in status register
+    sbc $12, s          ; $e3
+    sbc [$12]           ; $e7
+    xba                 ; $eb  exchange high and low bytes of accumulator
+    sbc $123456         ; $ef
+    sbc ($12, s), y     ; $f3
+    pea $1234           ; $f4  push effective absolute address
+    sbc [$12], y        ; $f7
+    xce                 ; $fb  exchange Carry and Emulation bits
+    jsr ($1234, x)      ; $fc
+    sbc $123456, x      ; $ff
+    .endscope
+
+    .A16 ; akku 16 bit
+    .I16 ; index registers 16 bit
+
+    .scope
+    cop $12             ; $02  coprocessor operation
+    ora $12, s          ; $03
+    ora [$12]           ; $07
+    phd                 ; $0b  push direct page register
+    ora $123456         ; $0f
+    ora ($12, s), y     ; $13
+    ora [$12], y        ; $17
+    tcs                 ; $1b  transfer C to stack pointer
+    ora $123456, x      ; $1f
+    jsl $123456         ; $22
+    and $12, s          ; $23
+    and [$12]           ; $27
+    pld                 ; $2b  pull direct page register
+    and $123456         ; $2f
+    and ($12, s), y     ; $33
+    and [$12], y        ; $37
+    tsc                 ; $3b  transfer stack pointer to C
+    and $123456, x      ; $3f
+    wdm $12             ; $42  (reserved for future expansion)
+    eor $12, s          ; $43
+    mvp $1234, $5678    ; $44
+    eor [$12]           ; $47
+    phk                 ; $4b  push program bank register
+    eor $123456         ; $4f
+    eor ($12, s), y     ; $53
+    mvn $1234, $5678    ; $54
+    eor [$12], y        ; $57
+    tcd                 ; $5b  transfer C to direct page register
+    jml $123456         ; $5c
+    eor $123456, x      ; $5f
+    per LABEL           ; $62  push effective relative address
+    adc $12, s          ; $63
+    adc [$12]           ; $67
+    rtl                 ; $6b  return long (fetches 24-bit address from stack)
+    adc $123456         ; $6f
+    adc ($12, s), y     ; $73
+    adc [$12], y        ; $77
+    tdc                 ; $7b  transfer direct page register to C
+    adc $123456, x      ; $7f
+LABEL:
+    brl LABEL           ; $82  branch long (16-bit offset)
+    sta $12, s          ; $83
+    sta [$12]           ; $87
+    phb                 ; $8b  push data bank register
+    sta $123456         ; $8f
+    sta ($12, s), y     ; $93
+    sta [$12], y        ; $97
+    txy                 ; $9b  transfer X to Y
+    sta $123456, x      ; $9f
+    lda $12, s          ; $a3
+    lda [$12]           ; $a7
+    plb                 ; $ab  pull data bank register
+    lda $123456         ; $af
+    lda ($12, s), y     ; $b3
+    lda [$12], y        ; $b7
+    tyx                 ; $bb  transfer Y to X
+    lda $123456, x      ; $bf
+    rep #$12            ; $c2  clear bits in status register
+    cmp $12, s          ; $c3
+    cmp [$12]           ; $c7
+    wai                 ; $cb  wait for interrupt
+    cmp $123456         ; $cf
+    cmp ($12, s), y     ; $d3
+    pei ($12)           ; $d4  push effective indirect address
+    cmp [$12], y        ; $d7
+    stp                 ; $db  wait for reset
+    jmp [$1234]         ; $dc
+    cmp $123456, x      ; $df
+    sep #$12            ; $e2  set bits in status register
+    sbc $12, s          ; $e3
+    sbc [$12]           ; $e7
+    xba                 ; $eb  exchange high and low bytes of accumulator
+    sbc $123456         ; $ef
+    sbc ($12, s), y     ; $f3
+    pea $1234           ; $f4  push effective absolute address
+    sbc [$12], y        ; $f7
+    xce                 ; $fb  exchange Carry and Emulation bits
+    jsr ($1234, x)      ; $fc
+    sbc $123456, x      ; $ff
+    .endscope
+
+.endif
+
+.if (.cpu .bitand CPU_ISET_SWEET16)
+
+    RTN                 ; $00      Return to 6502 code.
+    BR   LABEL          ; $01 ea   Unconditional Branch.
+    BNC  LABEL          ; $02 ea   Branch if Carry=0.
+    BC   LABEL          ; $03 ea   Branch if Carry=1.
+    BP   LABEL          ; $04 ea   Branch if last result positive.
+    BM   LABEL          ; $0S ea   Branch if last result negative.
+    BZ   LABEL          ; $06 ea   Branch if last result zero.
+    BNZ  LABEL          ; $07 ea   Branch if last result non-zero.
+    BM1  LABEL          ; $08 ea   Branch if last result = -1.
+    BNM1 LABEL          ; $09 ea   Branch if last result not -1.
+    BK                  ; $0A      Execute 6502 BRK instruction.
+    RS                  ; $0B      Return from SWEET-16 subroutine.
+    BS   LABEL          ; $0C ea   Call SWEET-16 subroutine.
+LABEL:
+
+.repeat 16, count
+    SET  count,$1234    ; $1n lo hi  Rn <-- value.
+    LD   count          ; $2n        R0 <-- (Rn).
+    ST   count          ; $3n        Rn <-- (R0).
+    LD   @count         ; $4n        MA = (Rn), ROL <-- (MA), Rn <-- MA+1, R0H <-- 0.
+    ST   @count         ; $5n        MA = (Rn), MA <-- (R0L), Rn <-- MA+1.
+    LDD  @count         ; $6n        MA = (Rn), R0 <-- (MA, MA+1), Rn <-- MA+2.
+    STD  @count         ; $7n        MA = (Rn), MA,MA+l <-- (R0), Rn <-- MA+2.
+    POP  @count         ; $8n        MA = (Rn)-1, R0L <-- (MA), R0H <-- 0, Rn <-- MA.
+    STP  @count         ; $9n        MA <-- (Rn)-1, (MA) <-- R0L, Rn <-- MA.
+    ADD  count          ; $An        R0 <-- (R0) + (Rn).
+    SUB  count          ; $Bn        R0 <-- (R0) - (Rn).
+    POPD @count         ; $Cn        MA = (Rn)-2, MA,MA+l <-- R0, Rn <-- MA.
+    CPR  count          ; $Dn        R13 <-- (R0) - (Rn), R14 <-- status flags.
+    INR  count          ; $En        Rn <-- (Rn) + 1.
+    DCR  count          ; $Fn        Rn <-- (Rn) - 1.
+.endrepeat
+
+.endif

test/asm/cpudetect/cpudetect.s

@@ -12,6 +12,11 @@
    lax #$ea
 .endif
 
+.ifp6280
+   sax
+   cla
+.endif
+
 .ifpsc02
    jmp ($1234,x)
 .endif
@@ -20,8 +25,13 @@
    rmb0 $12
 .endif
 
-.ifp816
-   xba
+.ifpwc02
+   wai
+   stp
+.endif
+
+.ifpce02
+   ldz #$12
 .endif
 
 .ifp4510
@@ -40,6 +50,14 @@
    jsr $ff12
 .endif
 
+.ifp816
+   xba
+.endif
+
+.ifpsweet16
+   bk
+.endif
+
 
 ; step 2: check for bitwise compatibility of instructions sets
 ;         (made verbose for better reading with hexdump/hd(1))
@@ -56,6 +74,10 @@
    .byte 0,"CPU_ISET_6502X"
 .endif
 
+.if (.cpu .bitand CPU_ISET_6502DTV)
+   .byte 0,"CPU_ISET_6502DTV"
+.endif
+
 .if (.cpu .bitand CPU_ISET_65SC02)
    .byte 0,"CPU_ISET_65SC02"
 .endif
@@ -64,16 +86,12 @@
    .byte 0,"CPU_ISET_65C02"
 .endif
 
-.if (.cpu .bitand CPU_ISET_65816)
-   .byte 0,"CPU_ISET_65816"
+.if (.cpu .bitand CPU_ISET_W65C02)
+   .byte 0,"CPU_ISET_W65C02"
 .endif
 
-.if (.cpu .bitand CPU_ISET_SWEET16)
-   .byte 0,"CPU_ISET_SWEET16"
-.endif
-
-.if (.cpu .bitand CPU_ISET_HUC6280)
-   .byte 0,"CPU_ISET_HUC6280"
+.if (.cpu .bitand CPU_ISET_65CE02)
+   .byte 0,"CPU_ISET_65CE02"
 .endif
 
 .if (.cpu .bitand CPU_ISET_4510)
@@ -84,19 +102,25 @@
    .byte 0,"CPU_ISET_45GS02"
 .endif
 
-.if (.cpu .bitand CPU_ISET_6502DTV)
-   .byte 0,"CPU_ISET_6502DTV"
+.if (.cpu .bitand CPU_ISET_HUC6280)
+   .byte 0,"CPU_ISET_HUC6280"
 .endif
 
 .if (.cpu .bitand CPU_ISET_M740)
    .byte 0,"CPU_ISET_M740"
 .endif
 
-; FIXME: something with 65816 is quirky
-.if (.not .cpu .bitand CPU_ISET_65816)
-    .include "allinst.inc"
+.if (.cpu .bitand CPU_ISET_65816)
+   .byte 0,"CPU_ISET_65816"
 .endif
 
+.if (.cpu .bitand CPU_ISET_SWEET16)
+   .byte 0,"CPU_ISET_SWEET16"
+.endif
+
+
+.include "allinst.inc"
+
 
 ; step 3: switch through all supported cpus to verify the pseudo-op is there
 
@@ -104,8 +128,12 @@
 .p02X
 .psc02
 .pc02
-.p816
+.pwc02
+.pce02
 .p4510
 .p45GS02
 .pdtv
+.p6280
 .pm740
+.p816
+.psweet16

test/asm/opcodes/65ce02-opcodes.s

@@ -0,0 +1,278 @@
+.setcpu "65CE02"
+
+   brk
+   ora ($05,x)
+   cle
+   see
+   tsb $02
+   ora $02
+   asl $02
+   rmb0 $02
+   php
+   ora #$01
+   asl
+   tsy
+   tsb $1234
+   ora $1234
+   asl $1234
+   bbr0 $02,*+$34
+
+   bpl *+$32
+   ora ($06),y
+   ora ($07),z
+   lbpl *+$3133 ; bpl *+$3133
+   trb $02
+   ora $03,x
+   asl $03,x
+   rmb1 $02
+   clc
+   ora $1456,y
+   inc
+   inz
+   trb $1234
+   ora $1345,x
+   asl $1345,x
+   bbr1 $02,*+$34
+
+   jsr $1234
+   and ($05,x)
+   jsr ($2345)
+   jsr ($2456,x)
+   bit $02
+   and $02
+   rol $02
+   rmb2 $02
+   plp
+   and #$01
+   rol
+   tys
+   bit $1234
+   and $1234
+   rol $1234
+   bbr2 $02,*+$34
+
+   bmi *+$32
+   and ($06),y
+   and ($07),z
+   lbmi *+$3133 ; bmi *+$3133
+   bit $03,x
+   and $03,x
+   rol $03,x
+   rmb3 $02
+   sec
+   and $1456,y
+   dec
+   dez
+   bit $1345,x
+   and $1345,x
+   rol $1345,x
+   bbr3 $02,*+$34
+
+   rti
+   eor ($05,x)
+   neg
+   asr
+   asr $02
+   eor $02
+   lsr $02
+   rmb4 $02
+   pha
+   eor #$01
+   lsr
+   taz
+   jmp $1234
+   eor $1234
+   lsr $1234
+   bbr4 $02,*+$34
+
+   bvc *+$32
+   eor ($06),y
+   eor ($07),z
+   lbvc *+$3133 ; bvc *+$3133
+   asr $03,x
+   eor $03,x
+   lsr $03,x
+   rmb5 $02
+   cli
+   eor $1456,y
+   phy
+   tab
+   aug
+   eor $1345,x
+   lsr $1345,x
+   bbr5 $02,*+$34
+
+   rts
+   adc ($05,x)
+   rtn #$09
+   bsr *+$3133
+   stz $02
+   adc $02
+   ror $02
+   rmb6 $02
+   pla
+   adc #$01
+   ror
+   tza
+   jmp ($2345)
+   adc $1234
+   ror $1234
+   bbr6 $02,*+$34
+
+   bvs *+$32
+   adc ($06),y
+   adc ($07),z
+   lbvs *+$3133 ; bvs *+$3133
+   stz $03,x
+   adc $03,x
+   ror $03,x
+   rmb7 $02
+   sei
+   adc $1456,y
+   ply
+   tba
+   jmp ($2456,x)
+   adc $1345,x
+   ror $1345,x
+   bbr7 $02,*+$34
+
+   bra *+$32
+   sta ($05,x)
+   sta ($0f,s),y
+   sta ($0f,sp),y
+   lbra *+$3133 ; bra *+$3133
+   sty $02
+   sta $02
+   stx $02
+   smb0 $02
+   dey
+   bit #$01
+   txa
+   sty $1345,x
+   sty $1234
+   sta $1234
+   stx $1234
+   bbs0 $02,*+$34
+
+   bcc *+$32
+   sta ($06),y
+   sta ($07),z
+   lbcc *+$3133 ; bcc *+$3133
+   sty $03,x
+   sta $03,x
+   stx $04,y
+   smb1 $02
+   tya
+   sta $1456,y
+   txs
+   stx $1456,y
+   stz $1234
+   sta $1345,x
+   stz $1345,x
+   bbs1 $02,*+$34
+
+   ldy #$01
+   lda ($05,x)
+   ldx #$01
+   ldz #$01
+   ldy $02
+   lda $02
+   ldx $02
+   smb2 $02
+   tay
+   lda #$01
+   tax
+   ldz $1234
+   ldy $1234
+   lda $1234
+   ldx $1234
+   bbs2 $02,*+$34
+
+   bcs *+$32
+   lda ($06),y
+   lda ($07),z
+   lbcs *+$3133 ; bcs *+$3133
+   ldy $03,x
+   lda $03,x
+   ldx $04,y
+   smb3 $02
+   clv
+   lda $1456,y
+   tsx
+   ldz $1345,x
+   ldy $1345,x
+   lda $1345,x
+   ldx $1456,y
+   bbs3 $02,*+$34
+
+   cpy #$01
+   cmp ($05,x)
+   cpz #$01
+   dew $02
+   cpy $02
+   cmp $02
+   dec $02
+   smb4 $02
+   iny
+   cmp #$01
+   dex
+   asw $1234
+   cpy $1234
+   cmp $1234
+   dec $1234
+   bbs4 $02,*+$34
+
+   bne *+$32
+   cmp ($06),y
+   cmp ($07),z
+   lbne *+$3133 ; bne *+$3133
+   cpz $02
+   cmp $03,x
+   dec $03,x
+   smb5 $02
+   cld
+   cmp $1456,y
+   phx
+   phz
+   cpz $1234
+   cmp $1345,x
+   dec $1345,x
+   bbs5 $02,*+$34
+
+   cpx #$01
+   sbc ($05,x)
+   lda ($0f,s),y
+   lda ($0f,sp),y
+   inw $02
+   cpx $02
+   sbc $02
+   inc $02
+   smb6 $02
+   inx
+   sbc #$01
+   eom
+   nop
+   row $1234
+   cpx $1234
+   sbc $1234
+   inc $1234
+   bbs6 $02,*+$34
+
+   beq *+$32
+   sbc ($06),y
+   sbc ($07),z
+   lbeq *+$3133 ; beq *+$3133
+   phd #$089a
+   phw #$089a
+   sbc $03,x
+   inc $03,x
+   smb7 $02
+   sed
+   sbc $1456,y
+   plx
+   plz
+   phd $1234
+   phw $1234
+   sbc $1345,x
+   inc $1345,x
+   bbs7 $02,*+$34

test/asm/opcodes/sweet16-opcodes.s

@@ -0,0 +1,34 @@
+.setcpu "SWEET16"
+
+    RTN                 ; $00      Return to 6502 code.
+    BR   LABEL          ; $01 ea   Unconditional Branch.
+    BNC  LABEL          ; $02 ea   Branch if Carry=0.
+    BC   LABEL          ; $03 ea   Branch if Carry=1.
+    BP   LABEL          ; $04 ea   Branch if last result positive.
+    BM   LABEL          ; $0S ea   Branch if last result negative.
+    BZ   LABEL          ; $06 ea   Branch if last result zero.
+    BNZ  LABEL          ; $07 ea   Branch if last result non-zero.
+    BM1  LABEL          ; $08 ea   Branch if last result = -1.
+    BNM1 LABEL          ; $09 ea   Branch if last result not -1.
+    BK                  ; $0A      Execute 6502 BRK instruction.
+    RS                  ; $0B      Return from SWEET-16 subroutine.
+    BS   LABEL          ; $0C ea   Call SWEET-16 subroutine.
+LABEL:
+
+.repeat 16, count
+    SET  count,$1234    ; $1n lo hi  Rn <-- value.
+    LD   count          ; $2n        R0 <-- (Rn).
+    ST   count          ; $3n        Rn <-- (R0).
+    LD   @count         ; $4n        MA = (Rn), ROL <-- (MA), Rn <-- MA+1, R0H <-- 0.
+    ST   @count         ; $5n        MA = (Rn), MA <-- (R0L), Rn <-- MA+1.
+    LDD  @count         ; $6n        MA = (Rn), R0 <-- (MA, MA+1), Rn <-- MA+2.
+    STD  @count         ; $7n        MA = (Rn), MA,MA+l <-- (R0), Rn <-- MA+2.
+    POP  @count         ; $8n        MA = (Rn)-1, R0L <-- (MA), R0H <-- 0, Rn <-- MA.
+    STP  @count         ; $9n        MA <-- (Rn)-1, (MA) <-- R0L, Rn <-- MA.
+    ADD  count          ; $An        R0 <-- (R0) + (Rn).
+    SUB  count          ; $Bn        R0 <-- (R0) - (Rn).
+    POPD @count         ; $Cn        MA = (Rn)-2, MA,MA+l <-- R0, Rn <-- MA.
+    CPR  count          ; $Dn        R13 <-- (R0) - (Rn), R14 <-- status flags.
+    INR  count          ; $En        Rn <-- (Rn) + 1.
+    DCR  count          ; $Fn        Rn <-- (Rn) - 1.
+.endrepeat

test/asm/opcodes/w65c02-opcodes.s

@@ -0,0 +1,258 @@
+.setcpu "W65C02"
+
+   brk
+   ora     ($12,x)
+   .byte   $02
+   .byte   $03
+   tsb     $12
+   ora     $12
+   asl     $12
+   rmb0    $12
+   php
+   ora     #$12
+   asl     a
+   .byte   $0B
+   tsb     $3456
+   ora     $3456
+   asl     $3456
+   bbr0    $12,*+122
+   bpl     *+122
+   ora     ($12),y
+   ora     ($12)
+   .byte   $13
+   trb     $12
+   ora     $12,x
+   asl     $12,x
+   rmb1    $12
+   clc
+   ora     $3456,y
+   inc     a
+   .byte   $1B
+   trb     $3456
+   ora     $3456,x
+   asl     $3456,x
+   bbr1    $12,*+122
+   jsr     $3456
+   and     ($12,x)
+   .byte   $22
+   .byte   $23
+   bit     $12
+   and     $12
+   rol     $12
+   rmb2    $12
+   plp
+   and     #$12
+   rol     a
+   .byte   $2B
+   bit     $3456
+   and     $3456
+   rol     $3456
+   bbr2    $12,*+122
+   bmi     *+122
+   and     ($12),y
+   and     ($12)
+   .byte   $33
+   bit     $12,x
+   and     $12,x
+   rol     $12,x
+   rmb3    $12
+   sec
+   and     $3456,y
+   dec     a
+   .byte   $3B
+   bit     $3456,x
+   and     $3456,x
+   rol     $3456,x
+   bbr3    $12,*+122
+   rti
+   eor     ($12,x)
+   .byte   $42
+   .byte   $43
+   .byte   $44
+   eor     $12
+   lsr     $12
+   rmb4    $12
+   pha
+   eor     #$12
+   lsr     a
+   .byte   $4B
+   jmp     $3456
+   eor     $3456
+   lsr     $3456
+   bbr4    $12,*+122
+   bvc     *+122
+   eor     ($12),y
+   eor     ($12)
+   .byte   $53
+   .byte   $54
+   eor     $12,x
+   lsr     $12,x
+   rmb5    $12
+   cli
+   eor     $3456,y
+   phy
+   .byte   $5B
+   .byte   $5C
+   eor     $3456,x
+   lsr     $3456,x
+   bbr5    $12,*+122
+   rts
+   adc     ($12,x)
+   .byte   $62
+   .byte   $63
+   stz     $12
+   adc     $12
+   ror     $12
+   rmb6    $12
+   pla
+   adc     #$12
+   ror     a
+   .byte   $6B
+   jmp     ($3456)
+   adc     $3456
+   ror     $3456
+   bbr6    $12,*+122
+   bvs     *+122
+   adc     ($12),y
+   adc     ($12)
+   .byte   $73
+   stz     $12,x
+   adc     $12,x
+   ror     $12,x
+   rmb7    $12
+   sei
+   adc     $3456,y
+   ply
+   .byte   $7B
+   jmp     ($3456,x)
+   adc     $3456,x
+   ror     $3456,x
+   bbr7    $12,*+122
+   bra     *+122
+   sta     ($12,x)
+   .byte   $82
+   .byte   $83
+   sty     $12
+   sta     $12
+   stx     $12
+   smb0    $12
+   dey
+   bit     #$12
+   txa
+   .byte   $8B
+   sty     $3456
+   sta     $3456
+   stx     $3456
+   bbs0    $12,*+122
+   bcc     *+122
+   sta     ($12),y
+   sta     ($12)
+   .byte   $93
+   sty     $12,x
+   sta     $12,x
+   stx     $12,y
+   smb1    $12
+   tya
+   sta     $3456,y
+   txs
+   .byte   $9B
+   stz     $3456
+   sta     $3456,x
+   stz     $3456,x
+   bbs1    $12,*+122
+   ldy     #$12
+   lda     ($12,x)
+   ldx     #$12
+   .byte   $A3
+   ldy     $12
+   lda     $12
+   ldx     $12
+   smb2    $12
+   tay
+   lda     #$12
+   tax
+   .byte   $AB
+   ldy     $3456
+   lda     $3456
+   ldx     $3456
+   bbs2    $12,*+122
+   bcs     *+122
+   lda     ($12),y
+   lda     ($12)
+   .byte   $B3
+   ldy     $12,x
+   lda     $12,x
+   ldx     $12,y
+   smb3    $12
+   clv
+   lda     $3456,y
+   tsx
+   .byte   $BB
+   ldy     $3456,x
+   lda     $3456,x
+   ldx     $3456,y
+   bbs3    $12,*+122
+   cpy     #$12
+   cmp     ($12,x)
+   .byte   $C2
+   .byte   $C3
+   cpy     $12
+   cmp     $12
+   dec     $12
+   smb4    $12
+   iny
+   cmp     #$12
+   dex
+   wai
+   cpy     $3456
+   cmp     $3456
+   dec     $3456
+   bbs4    $12,*+122
+   bne     *+122
+   cmp     ($12),y
+   cmp     ($12)
+   .byte   $D3
+   .byte   $D4
+   cmp     $12,x
+   dec     $12,x
+   smb5    $12
+   cld
+   cmp     $3456,y
+   phx
+   stp
+   .byte   $DC
+   cmp     $3456,x
+   dec     $3456,x
+   bbs5    $12,*+122
+   cpx     #$12
+   sbc     ($12,x)
+   .byte   $E2
+   .byte   $E3
+   cpx     $12
+   sbc     $12
+   inc     $12
+   smb6    $12
+   inx
+   sbc     #$12
+   nop
+   .byte   $EB
+   cpx     $3456
+   sbc     $3456
+   inc     $3456
+   bbs6    $12,*+122
+   beq     *+122
+   sbc     ($12),y
+   sbc     ($12)
+   .byte   $F3
+   .byte   $F4
+   sbc     $12,x
+   inc     $12,x
+   smb7    $12
+   sed
+   sbc     $3456,y
+   plx
+   .byte   $FB
+   .byte   $FC
+   sbc     $3456,x
+   inc     $3456,x
+   bbs7    $12,*+122

test/asm/val/ismnemonic.s

@@ -8,7 +8,10 @@
 ;    "6502DTV"
 ;    "65SC02"
 ;    "65C02"
+;    "65CE02"
+;    "W65C02"
 ;    "4510"
+;    "45GS02"
 ;    "huc6280"
 ;    "65816"
 ;    "sweet16"
@@ -415,6 +418,107 @@ test_Ismnemonic smb5
 test_Ismnemonic smb6
 test_Ismnemonic smb7
 test_Ismnemonic sta
+test_Ismnemonic stx
+test_Ismnemonic sty
+test_Ismnemonic stz
+test_Ismnemonic tax
+test_Ismnemonic tay
+test_Ismnemonic trb
+test_Ismnemonic tsb
+test_Ismnemonic tsx
+test_Ismnemonic txa
+test_Ismnemonic txs
+test_Ismnemonic tya
+
+
+.setcpu "W65C02"
+test_Ismnemonic adc
+test_Ismnemonic and
+test_Ismnemonic asl
+test_Ismnemonic bbr0
+test_Ismnemonic bbr1
+test_Ismnemonic bbr2
+test_Ismnemonic bbr3
+test_Ismnemonic bbr4
+test_Ismnemonic bbr5
+test_Ismnemonic bbr6
+test_Ismnemonic bbr7
+test_Ismnemonic bbs0
+test_Ismnemonic bbs1
+test_Ismnemonic bbs2
+test_Ismnemonic bbs3
+test_Ismnemonic bbs4
+test_Ismnemonic bbs5
+test_Ismnemonic bbs6
+test_Ismnemonic bbs7
+test_Ismnemonic bcc
+test_Ismnemonic bcs
+test_Ismnemonic beq
+test_Ismnemonic bit
+test_Ismnemonic bmi
+test_Ismnemonic bne
+test_Ismnemonic bpl
+test_Ismnemonic bra
+test_Ismnemonic brk
+test_Ismnemonic bvc
+test_Ismnemonic bvs
+test_Ismnemonic clc
+test_Ismnemonic cld
+test_Ismnemonic cli
+test_Ismnemonic clv
+test_Ismnemonic cmp
+test_Ismnemonic cpx
+test_Ismnemonic cpy
+test_Ismnemonic dea
+test_Ismnemonic dec
+test_Ismnemonic dex
+test_Ismnemonic dey
+test_Ismnemonic eor
+test_Ismnemonic ina
+test_Ismnemonic inc
+test_Ismnemonic inx
+test_Ismnemonic iny
+test_Ismnemonic jmp
+test_Ismnemonic jsr
+test_Ismnemonic lda
+test_Ismnemonic ldx
+test_Ismnemonic ldy
+test_Ismnemonic lsr
+test_Ismnemonic nop
+test_Ismnemonic ora
+test_Ismnemonic pha
+test_Ismnemonic php
+test_Ismnemonic phx
+test_Ismnemonic phy
+test_Ismnemonic pla
+test_Ismnemonic plp
+test_Ismnemonic plx
+test_Ismnemonic ply
+test_Ismnemonic rmb0
+test_Ismnemonic rmb1
+test_Ismnemonic rmb2
+test_Ismnemonic rmb3
+test_Ismnemonic rmb4
+test_Ismnemonic rmb5
+test_Ismnemonic rmb6
+test_Ismnemonic rmb7
+test_Ismnemonic rol
+test_Ismnemonic ror
+test_Ismnemonic rti
+test_Ismnemonic rts
+test_Ismnemonic sbc
+test_Ismnemonic sec
+test_Ismnemonic sed
+test_Ismnemonic sei
+test_Ismnemonic smb0
+test_Ismnemonic smb1
+test_Ismnemonic smb2
+test_Ismnemonic smb3
+test_Ismnemonic smb4
+test_Ismnemonic smb5
+test_Ismnemonic smb6
+test_Ismnemonic smb7
+test_Ismnemonic sta
 test_Ismnemonic stp
 test_Ismnemonic stx
 test_Ismnemonic sty
@@ -429,6 +533,141 @@ test_Ismnemonic txs
 test_Ismnemonic tya
 test_Ismnemonic wai
 
+.setcpu "65CE02"
+test_Ismnemonic adc
+test_Ismnemonic and
+test_Ismnemonic asl
+test_Ismnemonic asr
+test_Ismnemonic asw
+test_Ismnemonic aug
+test_Ismnemonic bbr0
+test_Ismnemonic bbr1
+test_Ismnemonic bbr2
+test_Ismnemonic bbr3
+test_Ismnemonic bbr4
+test_Ismnemonic bbr5
+test_Ismnemonic bbr6
+test_Ismnemonic bbr7
+test_Ismnemonic bbs0
+test_Ismnemonic bbs1
+test_Ismnemonic bbs2
+test_Ismnemonic bbs3
+test_Ismnemonic bbs4
+test_Ismnemonic bbs5
+test_Ismnemonic bbs6
+test_Ismnemonic bbs7
+test_Ismnemonic bcc
+test_Ismnemonic bcs
+test_Ismnemonic beq
+test_Ismnemonic bit
+test_Ismnemonic bmi
+test_Ismnemonic bne
+test_Ismnemonic bpl
+test_Ismnemonic bra
+test_Ismnemonic brk
+test_Ismnemonic bsr
+test_Ismnemonic bvc
+test_Ismnemonic bvs
+test_Ismnemonic clc
+test_Ismnemonic cld
+test_Ismnemonic cle
+test_Ismnemonic cli
+test_Ismnemonic clv
+test_Ismnemonic cmp
+test_Ismnemonic cpx
+test_Ismnemonic cpy
+test_Ismnemonic cpz
+test_Ismnemonic dea
+test_Ismnemonic dec
+test_Ismnemonic dew
+test_Ismnemonic dex
+test_Ismnemonic dey
+test_Ismnemonic dez
+test_Ismnemonic eom
+test_Ismnemonic eor
+test_Ismnemonic ina
+test_Ismnemonic inc
+test_Ismnemonic inw
+test_Ismnemonic inx
+test_Ismnemonic iny
+test_Ismnemonic inz
+test_Ismnemonic jmp
+test_Ismnemonic jsr
+test_Ismnemonic lbcc
+test_Ismnemonic lbcs
+test_Ismnemonic lbeq
+test_Ismnemonic lbmi
+test_Ismnemonic lbne
+test_Ismnemonic lbpl
+test_Ismnemonic lbra
+test_Ismnemonic lbvc
+test_Ismnemonic lbvs
+test_Ismnemonic lda
+test_Ismnemonic ldx
+test_Ismnemonic ldy
+test_Ismnemonic ldz
+test_Ismnemonic lsr
+test_Ismnemonic neg
+test_Ismnemonic nop
+test_Ismnemonic ora
+test_Ismnemonic pha
+test_Ismnemonic phd
+test_Ismnemonic php
+test_Ismnemonic phw
+test_Ismnemonic phx
+test_Ismnemonic phy
+test_Ismnemonic phz
+test_Ismnemonic pla
+test_Ismnemonic plp
+test_Ismnemonic plx
+test_Ismnemonic ply
+test_Ismnemonic plz
+test_Ismnemonic rmb0
+test_Ismnemonic rmb1
+test_Ismnemonic rmb2
+test_Ismnemonic rmb3
+test_Ismnemonic rmb4
+test_Ismnemonic rmb5
+test_Ismnemonic rmb6
+test_Ismnemonic rmb7
+test_Ismnemonic rol
+test_Ismnemonic ror
+test_Ismnemonic row
+test_Ismnemonic rti
+test_Ismnemonic rtn
+test_Ismnemonic rts
+test_Ismnemonic sbc
+test_Ismnemonic sec
+test_Ismnemonic sed
+test_Ismnemonic see
+test_Ismnemonic sei
+test_Ismnemonic smb0
+test_Ismnemonic smb1
+test_Ismnemonic smb2
+test_Ismnemonic smb3
+test_Ismnemonic smb4
+test_Ismnemonic smb5
+test_Ismnemonic smb6
+test_Ismnemonic smb7
+test_Ismnemonic sta
+test_Ismnemonic stx
+test_Ismnemonic sty
+test_Ismnemonic stz
+test_Ismnemonic tab
+test_Ismnemonic tax
+test_Ismnemonic tay
+test_Ismnemonic taz
+test_Ismnemonic tba
+test_Ismnemonic trb
+test_Ismnemonic tsb
+test_Ismnemonic tsx
+test_Ismnemonic tsy
+test_Ismnemonic txa
+test_Ismnemonic txs
+test_Ismnemonic tya
+test_Ismnemonic tys
+test_Ismnemonic tza
+
 .setcpu "4510"
 test_Ismnemonic adc
 test_Ismnemonic and
@@ -564,6 +803,159 @@ test_Ismnemonic tya
 test_Ismnemonic tys
 test_Ismnemonic tza
 
+.setcpu "45GS02"
+test_Ismnemonic adc
+test_Ismnemonic and
+test_Ismnemonic asl
+test_Ismnemonic asr
+test_Ismnemonic asw
+test_Ismnemonic bbr0
+test_Ismnemonic bbr1
+test_Ismnemonic bbr2
+test_Ismnemonic bbr3
+test_Ismnemonic bbr4
+test_Ismnemonic bbr5
+test_Ismnemonic bbr6
+test_Ismnemonic bbr7
+test_Ismnemonic bbs0
+test_Ismnemonic bbs1
+test_Ismnemonic bbs2
+test_Ismnemonic bbs3
+test_Ismnemonic bbs4
+test_Ismnemonic bbs5
+test_Ismnemonic bbs6
+test_Ismnemonic bbs7
+test_Ismnemonic bcc
+test_Ismnemonic bcs
+test_Ismnemonic beq
+test_Ismnemonic bit
+test_Ismnemonic bmi
+test_Ismnemonic bne
+test_Ismnemonic bpl
+test_Ismnemonic bra
+test_Ismnemonic brk
+test_Ismnemonic bsr
+test_Ismnemonic bvc
+test_Ismnemonic bvs
+test_Ismnemonic clc
+test_Ismnemonic cld
+test_Ismnemonic cle
+test_Ismnemonic cli
+test_Ismnemonic clv
+test_Ismnemonic cmp
+test_Ismnemonic cpx
+test_Ismnemonic cpy
+test_Ismnemonic cpz
+test_Ismnemonic dea
+test_Ismnemonic dec
+test_Ismnemonic dew
+test_Ismnemonic dex
+test_Ismnemonic dey
+test_Ismnemonic dez
+test_Ismnemonic eom
+test_Ismnemonic eor
+test_Ismnemonic ina
+test_Ismnemonic inc
+test_Ismnemonic inw
+test_Ismnemonic inx
+test_Ismnemonic iny
+test_Ismnemonic inz
+test_Ismnemonic jmp
+test_Ismnemonic jsr
+test_Ismnemonic lbcc
+test_Ismnemonic lbcs
+test_Ismnemonic lbeq
+test_Ismnemonic lbmi
+test_Ismnemonic lbne
+test_Ismnemonic lbpl
+test_Ismnemonic lbra
+test_Ismnemonic lbvc
+test_Ismnemonic lbvs
+test_Ismnemonic lda
+test_Ismnemonic ldx
+test_Ismnemonic ldy
+test_Ismnemonic ldz
+test_Ismnemonic lsr
+test_Ismnemonic map
+test_Ismnemonic neg
+test_Ismnemonic nop
+test_Ismnemonic ora
+test_Ismnemonic pha
+test_Ismnemonic phd
+test_Ismnemonic php
+test_Ismnemonic phw
+test_Ismnemonic phx
+test_Ismnemonic phy
+test_Ismnemonic phz
+test_Ismnemonic pla
+test_Ismnemonic plp
+test_Ismnemonic plx
+test_Ismnemonic ply
+test_Ismnemonic plz
+test_Ismnemonic rmb0
+test_Ismnemonic rmb1
+test_Ismnemonic rmb2
+test_Ismnemonic rmb3
+test_Ismnemonic rmb4
+test_Ismnemonic rmb5
+test_Ismnemonic rmb6
+test_Ismnemonic rmb7
+test_Ismnemonic rol
+test_Ismnemonic ror
+test_Ismnemonic row
+test_Ismnemonic rti
+test_Ismnemonic rtn
+test_Ismnemonic rts
+test_Ismnemonic sbc
+test_Ismnemonic sec
+test_Ismnemonic sed
+test_Ismnemonic see
+test_Ismnemonic sei
+test_Ismnemonic smb0
+test_Ismnemonic smb1
+test_Ismnemonic smb2
+test_Ismnemonic smb3
+test_Ismnemonic smb4
+test_Ismnemonic smb5
+test_Ismnemonic smb6
+test_Ismnemonic smb7
+test_Ismnemonic sta
+test_Ismnemonic stx
+test_Ismnemonic sty
+test_Ismnemonic stz
+test_Ismnemonic tab
+test_Ismnemonic tax
+test_Ismnemonic tay
+test_Ismnemonic taz
+test_Ismnemonic tba
+test_Ismnemonic trb
+test_Ismnemonic tsb
+test_Ismnemonic tsx
+test_Ismnemonic tsy
+test_Ismnemonic txa
+test_Ismnemonic txs
+test_Ismnemonic tya
+test_Ismnemonic tys
+test_Ismnemonic tza
+
+test_Ismnemonic adcq
+test_Ismnemonic andq
+test_Ismnemonic aslq
+test_Ismnemonic asrq
+test_Ismnemonic bitq
+test_Ismnemonic cmpq
+test_Ismnemonic deq
+test_Ismnemonic eorq
+test_Ismnemonic inq
+test_Ismnemonic ldq
+test_Ismnemonic lsrq
+test_Ismnemonic orq
+test_Ismnemonic sbcq
+test_Ismnemonic stq
+test_Ismnemonic rolq
+test_Ismnemonic rorq
+
+
 .setcpu "HuC6280"
 test_Ismnemonic adc
 test_Ismnemonic and