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Merge branch 'master' into c_sp

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Gorilla Sapiens
2025-06-22 19:02:24 +00:00
parent 5a4b11e7ff 7573272836
commit a7af49a763
93 changed files with 5626 additions and 554 deletions
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6
test/Makefile
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@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# top-level Makefile for the regression tests
ifneq ($(shell echo),)

6
test/asm/Makefile
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@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# top-level Makefile for the regression tests
ifneq ($(shell echo),)

BIN
test/asm/cpudetect/45GS02-cpudetect.ref Normal file
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Binary file not shown.

6
test/asm/cpudetect/Makefile
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@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the assembler regression tests
ifneq ($(shell echo),)

898
test/asm/cpudetect/allinst.inc Normal file
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@@ -0,0 +1,898 @@
; just emit to bss for now, this way the output wont get checked, which is
; fine - we only want to see if the assembler accepts all the opcodes it
; should accept for the current CPU mode
.bss
.if (.cpu .bitand CPU_ISET_6502)
.scope
; regular basic 6502 (legal) instruction set
LABEL0:
brk ; $00
ora ($12,x) ; $01
ora $12 ; $05
asl $12 ; $06
php ; $08
ora #$12 ; $09
asl a ; $0a
ora $1234 ; $0d
asl $1234 ; $0e
bpl LABEL0 ; $10
ora ($12),y ; $11
ora $12,x ; $15
asl $12,x ; $16
clc ; $18
ora $1234,y ; $19
ora $1234,x ; $1d
asl $1234,x ; $1e
jsr $1234 ; $20
and ($12,x) ; $21
bit $12 ; $24
and $12 ; $25
rol $12 ; $26
plp ; $28
and #$12 ; $29
rol a ; $2a
bit $1234 ; $2c
and $1234 ; $2d
rol $1234 ; $2e
bmi LABEL ; $30
and ($12),y ; $31
and $12,x ; $35
rol $12,x ; $36
sec ; $38
and $1234,y ; $39
and $1234,x ; $3d
rol $1234,x ; $3e
rti ; $40
eor ($12,x) ; $41
eor $12 ; $45
lsr $12 ; $46
pha ; $48
eor #$12 ; $49
lsr a ; $4a
jmp $1234 ; $4c
eor $1234 ; $4d
lsr $1234 ; $4e
bvc LABEL ; $50
eor ($12),y ; $51
eor $12,x ; $55
lsr $12,x ; $56
cli ; $58
eor $1234,y ; $59
eor $1234,x ; $5d
lsr $1234,x ; $5e
rts ; $60
adc ($12,x) ; $61
adc $12 ; $65
ror $12 ; $66
pla ; $68
adc #$12 ; $69
ror a ; $6a
jmp ($1234) ; $6c
adc $1234 ; $6d
ror $1234 ; $6e
bvs LABEL ; $70
adc ($12),y ; $71
adc $12,x ; $75
ror $12,x ; $76
sei ; $78
adc $1234,y ; $79
adc $1234,x ; $7d
ror $1234,x ; $7e
LABEL:
sta ($12,x) ; $81
sty $12 ; $84
sta $12 ; $85
stx $12 ; $86
dey ; $88
txa ; $8a
sty $1234 ; $8c
sta $1234 ; $8d
stx $1234 ; $8e
bcc LABEL ; $90
sta ($12),y ; $91
sty $12,x ; $94
sta $12,x ; $95
stx $12,y ; $96
tya ; $98
sta $1234,y ; $99
txs ; $9a
sta $1234,x ; $9d
ldy #$12 ; $a0
lda ($12,x) ; $a1
ldx #$12 ; $a2
ldy $12 ; $a4
lda $12 ; $a5
ldx $12 ; $a6
tay ; $a8
lda #$12 ; $a9
tax ; $aa
ldy $1234 ; $ac
lda $1234 ; $ad
ldx $1234 ; $ae
bcs LABEL ; $b0
lda ($12),y ; $b1
ldy $12,x ; $b4
lda $12,x ; $b5
ldx $12,y ; $b6
clv ; $b8
lda $1234,y ; $b9
tsx ; $ba
ldy $1234,x ; $bc
lda $1234,x ; $bd
ldx $1234,y ; $be
cpy #$12 ; $c0
cmp ($12,x) ; $c1
cpy $12 ; $c4
cmp $12 ; $c5
dec $12 ; $c6
iny ; $c8
cmp #$12 ; $c9
dex ; $ca
cpy $1234 ; $cc
cmp $1234 ; $cd
dec $1234 ; $ce
bne LABEL ; $d0
cmp ($12),y ; $d1
cmp $12,x ; $d5
dec $12,x ; $d6
cld ; $d8
cmp $1234,y ; $d9
cmp $1234,x ; $dd
dec $1234,x ; $de
cpx #$12 ; $e0
sbc ($12,x) ; $e1
cpx $12 ; $e4
sbc $12 ; $e5
inc $12 ; $e6
inx ; $e8
sbc #$12 ; $e9
nop ; $ea
cpx $1234 ; $ec
sbc $1234 ; $ed
inc $1234 ; $ee
beq LABEL1 ; $f0
sbc ($12),y ; $f1
sbc $12,x ; $f5
inc $12,x ; $f6
sed ; $f8
sbc $1234,y ; $f9
sbc $1234,x ; $fd
inc $1234,x ; $fe
LABEL1:
.endscope
.endif
.if (.cpu .bitand CPU_ISET_6502X)
.scope
; all "undocumented" 6502 instructions (aka "unintended opcodes")
jam ; $02
slo ($12,x) ; $03
nop $12 ; $04
slo $12 ; $07
anc #$12 ; $0b
nop $1234 ; $0c
slo $1234 ; $0f
jam ; $12
slo ($12),y ; $13
nop $12,x ; $14
slo $12,y ; $17
nop ; $1a
slo $1234,y ; $1b
nop $1234,x ; $1c
slo $1234,x ; $1f
jam ; $22
rla ($12,x) ; $23
rla $12 ; $27
anc #$12 ; $2b
rla $1234 ; $2f
jam ; $32
rla ($12),y ; $33
nop $12,x ; $34
rla $12,y ; $37
nop ; $3a
rla $1234,y ; $3b
nop $1234,x ; $3c
rla $1234,x ; $3f
jam ; $42
sre ($12,x) ; $43
nop $12 ; $44
sre $12 ; $47
alr #$12 ; $4b
sre $1234 ; $4f
jam ; $52
sre ($12),y ; $53
nop $12,x ; $54
sre $12,y ; $57
nop ; $5a
sre $1234,y ; $5b
nop $1234,x ; $5c
sre $1234,x ; $5f
jam ; $62
rra ($12,x) ; $63
nop $12 ; $64
rra $12 ; $67
arr #$12 ; $6b
rra $1234 ; $6f
jam ; $72
rra ($12),y ; $73
nop $12,x ; $74
rra $12,y ; $77
nop ; $7a
rra $1234,y ; $7b
nop $1234,x ; $7c
rra $1234,x ; $7f
nop #$12 ; $80
nop #$12 ; $82
sax ($12,x) ; $83
sax $12 ; $87
nop #$12 ; $89
ane #$12 ; $8b
sax $1234 ; $8f
jam ; $92
sha ($12),y ; $93
sax $12,y ; $97
tas $1234,y ; $9b
shy $1234,x ; $9c
shx $1234,y ; $9e
sha $1234,y ; $9f
lax ($12,x) ; $a3
lax $12 ; $a7
lax #$12 ; $ab
lax $1234 ; $af
jam ; $b2
lax ($12),y ; $b3
lax $12,y ; $b7
las $1234,y ; $bb
lax $1234,y ; $bf
nop #$12 ; $c2
dcp ($12,x) ; $c3
dcp $12 ; $c7
axs #$12 ; $cb
dcp $1234 ; $cf
jam ; $d2
dcp ($12),y ; $d3
nop $12,x ; $d4
dcp $12,y ; $d7
nop ; $da
dcp $1234,y ; $db
nop $1234,x ; $dc
dcp $1234,x ; $df
nop #$12 ; $e2
isc ($12,x) ; $e3
isc $12 ; $e7
sbc #$12 ; $eb
isc $1234 ; $ef
jam ; $f2
isc ($12),y ; $f3
nop $12,x ; $f4
isc $12,y ; $f7
nop ; $fa
isc $1234,y ; $fb
nop $1234,x ; $fc
isc $1234,x ; $ff
.endscope
.endif
.if (.cpu .bitand CPU_ISET_6502DTV)
.scope
LABEL:
; opcodes added over 6502 (these are JAM on 6502)
bra LABEL ; $12
sac #$12 ; $32
sir #$12 ; $42
; opcodes added over 6502, which work the same as the "illegal" opcodes on 6502
nop $12 ; $04
nop $1234 ; $0c
nop $12,x ; $14
nop ; $1a
nop $1234,x ; $1c
nop $12,x ; $34
nop ; $3a
nop $1234,x ; $3c
nop $12 ; $44
nop $12,x ; $54
nop ; $5a
nop $1234,x ; $5c
nop $12 ; $64
nop $12,x ; $74
nop ; $7a
nop $1234,x ; $7c
nop #$12 ; $80
nop #$12 ; $82
nop #$12 ; $89
nop #$12 ; $c2
nop $12,x ; $d4
nop ; $da
nop $1234,x ; $dc
nop #$12 ; $e2
nop $12,x ; $f4
nop ; $fa
nop $1234,x ; $fc
anc #$12 ; $0b
anc #$12 ; $2b
rla ($12,x) ; $23
rla $12 ; $27
rla $1234 ; $2f
rla ($12),y ; $33
rla $12,y ; $37
rla $1234,y ; $3b
rla $1234,x ; $3f
lax ($12,x) ; $a3
lax $12 ; $a7
lax #$12 ; $ab
lax $1234 ; $af
lax ($12),y ; $b3
lax $12,y ; $b7
lax $1234,y ; $bf
las $1234,y ; $bb
alr #$12 ; $4b
arr #$12 ; $6b
rra ($12,x) ; $63
rra $12 ; $67
rra $1234 ; $6f
rra ($12),y ; $73
rra $12,y ; $77
rra $1234,y ; $7b
rra $1234,x ; $7f
shy $1234,x ; $9c
shx $1234,y ; $9e
axs #$12 ; $cb
sbc #$12 ; $eb
.endscope
.endif
;------------------------------------------------------------------------------
; The 65c02 is the CMOS re-design of the 6502. It has a few improvements:
;
; 65C02 65ce02
;
; $04 tsb zp
; $0c tsb abs16
; $12 ora (zp) (-> ora (zp), z)
; $14 trb zp
; $1a inc
; $1c trb abs16
; $32 and (zp) (-> and (zp), z)
; $34 bit zp, x
; $3a dec
; $3c bit abs16, x
; $52 eor (zp) (-> eor (zp), z)
; $5a phy
; $64 stz zp (store z, not 0)
; $72 adc (zp) (-> adc (zp), z)
; $74 stz zp, x (store z, not 0)
; $7a ply
; $7c jmp (abs16, x)
; $80 bra rel8
; $89 bit #imm8
; $92 sta (zp) (-> sta (zp), z)
; $9c stz abs16 (store z, not 0)
; $9e stz abs16, x (store z, not 0)
; $b2 lda (zp) (-> lda (zp), z)
; $d2 cmp (zp) (-> cmp (zp), z)
; $da phx
; $f2 sbc (zp) (-> sbc (zp), z)
; $fa plx
; FIXME: currently CPU_ISET_65SC02 and CPU_65SC02 really means "65C02"
; FIXME: should really check for 65C02
.if (.cpu .bitand CPU_ISET_65SC02)
.scope
; 65c02 instruction set adds some extra legal instructions to 6502
tsb $12 ; $04
tsb $1234 ; $0c
;ora ($12) ; $12 FIXME: not working with 4510:ora (zp), z
trb $12 ; $14
inc a ; $1a
trb $1234 ; $1c
;and ($12) ; $32 FIXME: not working with 4510:and (zp), z
bit $12,x ; $34
dec a ; $3a
bit $1234,x ; $3c
;eor ($12) ; $52 FIXME: not working with 4510:eor (zp), z
phy ; $5a
stz $12 ; $64
;adc ($12) ; $72 FIXME: not working with 4510:adc (zp), z
stz $12,x ; $74
ply ; $7a
jmp ($1234) ; $7c
LABEL:
bra LABEL ; $80
bit #$12 ; $89
;sta ($12) ; $92 FIXME: not working with 4510:sta (zp), z
stz $1234 ; $9c
stz $1234,x ; $9e
;lda ($12) ; $b2 FIXME: not working with 4510:lda (zp), z
;cmp ($12) ; $d2 FIXME: not working with 4510:cmp (zp), z
phx ; $da
;sbc ($12) ; $f2 FIXME: not working with 4510:sbc (zp), z
plx ; $fa
.endscope
.endif
; FIXME: hack so these opcodes get tested anyway, while 4510 is still quirky
.if (.cpu .bitand CPU_ISET_65SC02)
.if (.not .cpu = CPU_4510)
ora ($12) ; $12
and ($12) ; $32
eor ($12) ; $52
adc ($12) ; $72
sta ($12) ; $92
lda ($12) ; $b2
cmp ($12) ; $d2
sbc ($12) ; $f2
.endif
.endif
; TODO: R65C02
; The R65C02 is a superset of the 65C02. It adds bit manipulation instructions:
; smbB zp set bit in zp location
; rmbB zp reset bit in zp location
; bbsB zp, rel8 branch if bit is set in zp location
; bbrB zp, rel8 branch if bit is reset in zp location
; FIXME: currently CPU_ISET_65C02 and CPU_65C02 really means "W65C02"
; FIXME: should really check for R65C02
.if (.cpu .bitand CPU_ISET_65C02)
; R65C02 instruction set adds some extra legal instructions to 65C02
rmb0 $12 ; $07
bbr0 $12, LABEL3 ; $0f
rmb1 $12 ; $17
bbr1 $12, LABEL3 ; $1f
rmb2 $12 ; $27
bbr2 $12, LABEL3 ; $2f
rmb3 $12 ; $37
bbr3 $12, LABEL3 ; $3f
rmb4 $12 ; $47
bbr4 $12, LABEL3 ; $4f
rmb5 $12 ; $57
bbr5 $12, LABEL3 ; $5f
rmb6 $12 ; $67
bbr6 $12, LABEL3 ; $6f
rmb7 $12 ; $77
bbr7 $12, LABEL3 ; $7f
LABEL3:
smb0 $12 ; $87
bbs0 $12, LABEL3 ; $8f
smb1 $12 ; $97
bbs1 $12, LABEL3 ; $9f
smb2 $12 ; $a7
bbs2 $12, LABEL3 ; $af
smb3 $12 ; $b7
bbs3 $12, LABEL3 ; $bf
smb4 $12 ; $c7
bbs4 $12, LABEL3 ; $cf
smb5 $12 ; $d7
bbs5 $12, LABEL3 ; $df
smb6 $12 ; $e7
bbs6 $12, LABEL3 ; $ef
smb7 $12 ; $f7
bbs7 $12, LABEL3 ; $ff
.endif
; TODO: W65C02
; The W65C02 is a superset of the R65C02. It only adds two instructions:
;
; $cb wai wait for interrupt
; $db stp wait for reset
; FIXME: currently CPU_ISET_65C02 and CPU_65C02 really means "W65C02"
; FIXME: should really check for W65C02
.if (.cpu = CPU_65C02)
wai ; $cb
stp ; $db
.endif
; TODO: 65CE02
; The 65CE02 is another superset of the R65C02. It has several improvements:
;
; $02 cle clear stack extend disable
; $03 see set stack extend disable
; $0b tsy transfer stack_ptr_high to Y
; $12 ora (zp), z
; $13 lbpl rel16
; $1b inz increment Z
; $22 jsr (abs16)
; $23 jsr (abs16, x)
; $2b tys transfer Y to stack_ptr_high
; $32 and (zp), z
; $33 lbmi rel16
; $3b dez decrement Z
; $42 neg negate A
; $43 asr
; $44 asr zp
; $4b taz transfer A to Z
; $52 eor (zp), z
; $53 lbvc rel16
; $54 asr zp, x
; $5b tab
; $5c aug "4-byte NOP reserved for future expansion"
; $62 rtn #imm8
; $63 lbsr rel16 relative jsr, "branch to subroutine"
; $64 stz zp store Z
; $6b tza transfer Z to A
; $72 adc (zp), z
; $73 lbvs rel16
; $74 stz zp, x store Z
; $7b tba
; $82 sta (off8, s), y
; $83 lbra rel16 relative jmp
; $8b sty abs16, x
; $92 sta (zp), z
; $93 lbcc rel16
; $9b stx abs16, y
; $9c stz abs16 store Z
; $9e stz abs16, x store Z
; $a3 ldz #imm8
; $ab ldz abs16
; $b2 lda (zp), z
; $b3 lbcs rel16
; $bb ldz abs16, x
; $c2 cpz #imm8
; $c3 dew zp
; $cb asw abs16
; $d2 cmp (zp), z
; $d3 lbne rel16
; $d4 cpz zp
; $db phz push Z
; $dc cpz abs16
; $e2 lda (off8, s), y
; $e3 inw zp
; $eb row abs16
; $f2 sbc (zp), z
; $f3 lbeq rel16
; $f4 phw #imm16
; $fb plz pull Z
; $fc phw abs16
; FIXME: should really check for 65CE02
.if (.cpu .bitand CPU_ISET_4510)
.scope
; 65CE02 adds the following:
cle ; $02
see ; $03
tsy ; $0b
ora ($12), z ; $12 (ora (zp) on 65C02)
lbpl $1234 ; $13
inz ; $1b
jsr ($1234) ; $22
jsr ($1234,x) ; $23
tys ; $2b
and ($12), z ; $32 (and (zp) on 65C02)
lbmi $1234 ; $33
dez ; $3b
neg ; $42
asr a ; $43
asr $12 ; $44
taz ; $4b
lbvc $1234 ; $53
asr $12,x ; $54
tab ; $5b
;aug ; $5c FIXME: implement in assembler
rtn #$12 ; $62
bsr $1234 ; $63
stz $12 ; $64 (stores 0 on 65C02)
tza ; $6b
adc ($12), z ; $72 (adc (zp) on 65C02)
lbvs $1234 ; $73
stz $12, x ; $74 (stores 0 on 65C02)
tba ; $7b
sta ($12,s),y ; $82
lbra $1234 ; $83
sty $1234,x ; $8b
lbcc $1234 ; $93
sta ($12), z ; $92 (sta (zp) on 65C02)
stx $1234,y ; $9b
stz $1234 ; $9c (stores 0 on 65C02)
ldz #$12 ; $a3
ldz $1234 ; $ab
lda ($12), z ; $b2 (lda (zp) on 65C02)
lbcs $1234 ; $b3
ldz $1234,x ; $bb
cpz #$12 ; $c2
dew $12 ; $c3
cmp ($12), z ; $d2 (cmp ($12) on 65C02)
lbne $1234 ; $d3
cpz $12 ; $d4
cpz $1234 ; $dc
lda ($12,s),y ; $e2
inw $12 ; $e3
row $1234 ; $eb
sbc ($12), z ; $f2 (sbc (zp) on 65C02)
lbeq $1234 ; $f3
phw #$1234 ; $f4
plz ; $fb
phw $1234 ; $fc
.endscope
.endif
; The 4510 is a superset of the 65CE02. Opcode 5c (originally a "4-byte NOP
; reserved for future expansion") has been changed to the "map" instruction,
; now using implied addressing.
;
; $5c map
; $cb asw abs
; $db phz
.if (.cpu .bitand CPU_ISET_4510)
.scope
; added to 65CE02
map ; $5c ("4-byte NOP reserved for future expansion" on 65CE02)
asw $1234 ; $cb (wai on W65C02)
phz ; $db (stp on W65C02)
eom ; $ea "end of mapping" - but really just a NOP
.endscope
.endif
; The 45GS02 instruction set extends the 4510 instruction set using prefix bytes.
; Therefore, the "normal" opcode table is the same as for the 4510 cpu
.if (.cpu .bitand CPU_ISET_45GS02)
.scope
orq $12 ; $42 $42 $05
aslq $12 ; $42 $42 $06
aslq ; $42 $42 $0a
orq $1234 ; $42 $42 $0d
aslq $1234 ; $42 $42 $0e
orq ($12) ; $42 $42 $12
aslq $12,x ; $42 $42 $16
inq ; $42 $42 $1a
aslq $1234,x ; $42 $42 $1e
bitq $12 ; $42 $42 $24
andq $12 ; $42 $42 $25
rolq $12 ; $42 $42 $26
rolq ; $42 $42 $2a
bitq $1234 ; $42 $42 $2c
andq $1234 ; $42 $42 $2d
rolq $1234 ; $42 $42 $2e
andq ($12) ; $42 $42 $32
rolq $12, x ; $42 $42 $36
deq ; $42 $42 $3a
rolq $1234, x ; $42 $42 $3e
asrq ; $42 $42 $43
asrq $12 ; $42 $42 $44
eorq $12 ; $42 $42 $45
lsrq $12 ; $42 $42 $46
lsrq ; $42 $42 $4a
eorq $1234 ; $42 $42 $4d
lsrq $1234 ; $42 $42 $4e
eorq ($12) ; $42 $42 $52
asrq $12, x ; $42 $42 $54
lsrq $12, x ; $42 $42 $56
lsrq $1234, x ; $42 $42 $5e
adcq $12 ; $42 $42 $65
rorq $12 ; $42 $42 $66
rorq ; $42 $42 $6a
adcq $1234 ; $42 $42 $6d
rorq $1234 ; $42 $42 $6e
adcq ($12) ; $42 $42 $72
rorq $12, x ; $42 $42 $76
rorq $1234, x ; $42 $42 $7e
stq $12 ; $42 $42 $85
stq $1234 ; $42 $42 $8d
stq ($12) ; $42 $42 $92
ldq $12 ; $42 $42 $a5
ldq $1234 ; $42 $42 $ad
ldq ($12), z ; $42 $42 $b2
cmpq $12 ; $42 $42 $c5
deq $12 ; $42 $42 $c6
cmpq $1234 ; $42 $42 $cd
deq $1234 ; $42 $42 $ce
cmpq ($12) ; $42 $42 $d2
deq $12, x ; $42 $42 $d6
deq $1234, x ; $42 $42 $de
sbcq $12 ; $42 $42 $e5
inq $12 ; $42 $42 $e6
sbcq $1234 ; $42 $42 $ed
inq $1234 ; $42 $42 $ee
sbcq ($12) ; $42 $42 $f2
inq $12, x ; $42 $42 $f6
inq $1234, x ; $42 $42 $fe
ora [$12], z ; $ea $12
and [$12], z ; $ea $32
eor [$12], z ; $ea $52
adc [$12], z ; $ea $72
sta [$12], z ; $ea $92
lda [$12], z ; $ea $b2
cmp [$12], z ; $ea $d2
sbc [$12], z ; $ea $f2
orq [$12] ; $42 $42 $ea $12
andq [$12] ; $42 $42 $ea $32
eorq [$12] ; $42 $42 $ea $52
adcq [$12] ; $42 $42 $ea $72
stq [$12] ; $42 $42 $ea $92
ldq [$12], z ; $42 $42 $ea $b2
cmpq [$12] ; $42 $42 $ea $d2
sbcq [$12] ; $42 $42 $ea $f2
.endscope
.endif
; The HUC6280 is a superset of the R65C02. It adds some other instructions:
.if (.cpu .bitand CPU_ISET_HUC6280)
.scope
; added to R65C02
sxy ; $02
st0 #$12 ; $03
st1 #$12 ; $13
sax ; $22
st2 #$12 ; $23
say ; $42
tma #$10 ; $43
bsr LABEL ; $44
tam #$12 ; $53
csl ; $54
cla ; $62
tii $1234, $5678, $9abc ; $73
LABEL:
clx ; $82
tst #$12, $34 ; $83
clx ; $82
tst #$12, $34 ; $83
tst #$12, $3456 ; $93
tst #$12, $34, x ; $a3
tst #$12, $3456, x ; $b3
cly ; $c2
tdd $1234, $5678, $9abc ; $c3
tin $1234, $5678, $9abc ; $d3
csh ; $d4
tia $1234, $5678, $9abc ; $e3
tai $1234, $5678, $9abc ; $f3
set ; $f4
.endscope
.endif
.if (.cpu .bitand CPU_ISET_M740)
.scope
; Mitsubishi M740 - adds new instructions to 65SC02 (but also removes some)
jsr ($12) ; $02
bbs0 a, LABEL ; $03
bbs0 $12, LABEL ; $07
seb0 a ; $0b
seb0 $12 ; $0f
bbc0 a, LABEL ; $13
bbc0 $12, LABEL ; $17
clb0 a ; $1b
clb0 $12 ; $1f
jsr $ff12 ; $22
bbs1 a, LABEL ; $23
bbs1 $12, LABEL ; $27
seb1 a ; $2b
seb1 $12 ; $2f
bbc1 a, LABEL ; $33
bbc1 $12, LABEL ; $37
clb1 a ; $3b
clb1 $12 ; $3f
stp ; $42
bbs2 a, LABEL ; $43
com $12 ; $44
bbs2 $12, LABEL ; $47
seb2 a ; $4b
seb2 $12 ; $4f
bbc2 a, LABEL ; $53
bbc2 $12, LABEL ; $57
clb2 a ; $5b
clb2 $12 ; $5f
bbs3 a, LABEL ; $63
bbs3 $12, LABEL ; $67
seb3 a ; $6b
seb3 $12 ; $6f
bbc3 a, LABEL ; $73
bbc3 $12, LABEL ; $77
clb3 a ; $7b
clb3 $12 ; $7f
LABEL:
rrf $12 ; $82
bbs4 a, LABEL ; $83
bbs4 $12, LABEL ; $87
seb4 a ; $8b
seb4 $12 ; $8f
bbc4 a, LABEL ; $93
bbc4 $12, LABEL ; $97
clb4 a ; $9b
clb4 $12 ; $9f
bbs5 a, LABEL ; $a3
bbs5 $12, LABEL ; $a7
seb5 a ; $ab
seb5 $12 ; $af
bbc5 a, LABEL ; $b3
bbc5 $12, LABEL ; $b7
clb5 a ; $bb
clb5 $12 ; $bf
slw ; $c2
bbs6 a, LABEL ; $c3
bbs6 $12, LABEL ; $c7
seb6 a ; $cb
seb6 $12 ; $cf
bbc6 a, LABEL ; $d3
bbc6 $12, LABEL ; $d7
clb6 a ; $db
clb6 $12 ; $df
fst ; $e2
bbs7 a, LABEL ; $e3
bbs7 $12, LABEL ; $e7
seb7 a ; $eb
seb7 $12 ; $ef
bbc7 a, LABEL ; $f3
bbc7 $12, LABEL ; $f7
clb7 a ; $fb
clb7 $12 ; $ff
; replaced from 65SC02
clt ; $12
set ; $32
ldm $12, #$34 ; $3c
tst $12 ; $64
; removed from 65SC02 (replaced by new)
; ora ($12) ; $12
; and ($12) ; $32
; bit $1234,x ; $3c
; stz $12 ; $64
; removed from 65SC02
; tsb $12 ; $04
; tsb $1234 ; $0c
; trb $12 ; $14
; trb $1234 ; $1c
; bit $12,y ; $34
; eor ($12) ; $52
; phy ; $5a
; adc ($12) ; $72
; stz $12,y ; $74
; ply ; $7a
; jmp ($1234) ; $7c
; bit #$12 ; $89
; sta ($12) ; $92
; stz $1234 ; $9c
; stz $1234,x ; $9e
; cmp ($12) ; $d2
; phx ; $da
; sbc ($12) ; $f2
; plx ; $fa
.endscope
.endif

23
test/asm/cpudetect/cpudetect.s
View File

@@ -28,10 +28,18 @@
taz
.endif
.ifp45GS02
orq $1234
.endif
.ifpdtv
sac #$00
.endif
.ifpm740
jsr $ff12
.endif
; step 2: check for bitwise compatibility of instructions sets
; (made verbose for better reading with hexdump/hd(1))
@@ -72,10 +80,23 @@
.byte 0,"CPU_ISET_4510"
.endif
.if (.cpu .bitand CPU_ISET_45GS02)
.byte 0,"CPU_ISET_45GS02"
.endif
.if (.cpu .bitand CPU_ISET_6502DTV)
.byte 0,"CPU_ISET_6502DTV"
.endif
.if (.cpu .bitand CPU_ISET_M740)
.byte 0,"CPU_ISET_M740"
.endif
; FIXME: something with 65816 is quirky
.if (.not .cpu .bitand CPU_ISET_65816)
.include "allinst.inc"
.endif
; step 3: switch through all supported cpus to verify the pseudo-op is there
@@ -85,4 +106,6 @@
.pc02
.p816
.p4510
.p45GS02
.pdtv
.pm740

BIN
test/asm/cpudetect/m740-cpudetect.ref Normal file
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6
test/asm/err/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the tests that MUST NOT compile
ifneq ($(shell echo),)

28
test/asm/err/bug505.s Normal file
View File

@@ -0,0 +1,28 @@
; Test for #505 taken from the issue
; Redefining a variable symbol "reopens" the old name space for cheap locals
; Behavior should be: First definition of a variable symbol opens a new
; scope for cheap locals, redefinitions of the same symbols do not.
;this starts a new scope for cheap local lables
SomeSymbol .set 4
jmp @CheapLocal1
@CheapLocal0:
.byte $8b
CheapLocalScopeBreaker0:
CheapLocalScopeBreaker1:
CheapLocalScopeBreaker2:
CheapLocalScopeBreaker3:
;this continues the same cheap scope as before, regardless of the many global labels in between
SomeSymbol .set 5
@CheapLocal1:
lda @CheapLocal0

6
test/asm/listing/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the assembler regression tests
ifneq ($(shell echo),)

6
test/asm/misc/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the remaining asm tests that need special care in one way or another
ifneq ($(shell echo),)

BIN
test/asm/opcodes/45GS02-opcodes.ref Normal file
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377
test/asm/opcodes/45GS02-opcodes.s Normal file
View File

@@ -0,0 +1,377 @@
.setcpu "45GS02"
brk
ora ($05,x)
cle
see
tsb $02
ora $02
asl $02
rmb0 $02
php
ora #$01
asl
tsy
tsb $1234
ora $1234
asl $1234
bbr0 $02,*+$34
bpl *+$32
ora ($06),y
ora ($07),z
lbpl *+$3133 ; bpl *+$3133
trb $02
ora $03,x
asl $03,x
rmb1 $02
clc
ora $1456,y
inc
inz
trb $1234
ora $1345,x
asl $1345,x
bbr1 $02,*+$34
jsr $1234
and ($05,x)
jsr ($2345)
jsr ($2456,x)
bit $02
and $02
rol $02
rmb2 $02
plp
and #$01
rol
tys
bit $1234
and $1234
rol $1234
bbr2 $02,*+$34
bmi *+$32
and ($06),y
and ($07),z
lbmi *+$3133 ; bmi *+$3133
bit $03,x
and $03,x
rol $03,x
rmb3 $02
sec
and $1456,y
dec
dez
bit $1345,x
and $1345,x
rol $1345,x
bbr3 $02,*+$34
rti
eor ($05,x)
neg
asr
asr $02
eor $02
lsr $02
rmb4 $02
pha
eor #$01
lsr
taz
jmp $1234
eor $1234
lsr $1234
bbr4 $02,*+$34
bvc *+$32
eor ($06),y
eor ($07),z
lbvc *+$3133 ; bvc *+$3133
asr $03,x
eor $03,x
lsr $03,x
rmb5 $02
cli
eor $1456,y
phy
tab
map
eor $1345,x
lsr $1345,x
bbr5 $02,*+$34
rts
adc ($05,x)
rtn #$09
bsr *+$3133
stz $02
adc $02
ror $02
rmb6 $02
pla
adc #$01
ror
tza
jmp ($2345)
adc $1234
ror $1234
bbr6 $02,*+$34
bvs *+$32
adc ($06),y
adc ($07),z
lbvs *+$3133 ; bvs *+$3133
stz $03,x
adc $03,x
ror $03,x
rmb7 $02
sei
adc $1456,y
ply
tba
jmp ($2456,x)
adc $1345,x
ror $1345,x
bbr7 $02,*+$34
bra *+$32
sta ($05,x)
sta ($0f,s),y
sta ($0f,sp),y
lbra *+$3133 ; bra *+$3133
sty $02
sta $02
stx $02
smb0 $02
dey
bit #$01
txa
sty $1345,x
sty $1234
sta $1234
stx $1234
bbs0 $02,*+$34
bcc *+$32
sta ($06),y
sta ($07),z
lbcc *+$3133 ; bcc *+$3133
sty $03,x
sta $03,x
stx $04,y
smb1 $02
tya
sta $1456,y
txs
stx $1456,y
stz $1234
sta $1345,x
stz $1345,x
bbs1 $02,*+$34
ldy #$01
lda ($05,x)
ldx #$01
ldz #$01
ldy $02
lda $02
ldx $02
smb2 $02
tay
lda #$01
tax
ldz $1234
ldy $1234
lda $1234
ldx $1234
bbs2 $02,*+$34
bcs *+$32
lda ($06),y
lda ($07),z
lbcs *+$3133 ; bcs *+$3133
ldy $03,x
lda $03,x
ldx $04,y
smb3 $02
clv
lda $1456,y
tsx
ldz $1345,x
ldy $1345,x
lda $1345,x
ldx $1456,y
bbs3 $02,*+$34
cpy #$01
cmp ($05,x)
cpz #$01
dew $02
cpy $02
cmp $02
dec $02
smb4 $02
iny
cmp #$01
dex
asw $1234
cpy $1234
cmp $1234
dec $1234
bbs4 $02,*+$34
bne *+$32
cmp ($06),y
cmp ($07),z
lbne *+$3133 ; bne *+$3133
cpz $02
cmp $03,x
dec $03,x
smb5 $02
cld
cmp $1456,y
phx
phz
cpz $1234
cmp $1345,x
dec $1345,x
bbs5 $02,*+$34
cpx #$01
sbc ($05,x)
lda ($0f,s),y
lda ($0f,sp),y
inw $02
cpx $02
sbc $02
inc $02
smb6 $02
inx
sbc #$01
eom
nop
row $1234
cpx $1234
sbc $1234
inc $1234
bbs6 $02,*+$34
beq *+$32
sbc ($06),y
sbc ($07),z
lbeq *+$3133 ; beq *+$3133
phd #$089a
phw #$089a
sbc $03,x
inc $03,x
smb7 $02
sed
sbc $1456,y
plx
plz
phd $1234
phw $1234
sbc $1345,x
inc $1345,x
bbs7 $02,*+$34
adc [$12],z
adcq $12
adcq $3456
adcq ($78)
adcq [$9a]
and [$12],z
andq $12
andq $3456
andq ($78)
andq [$9a]
aslq $12
aslq
aslq $3456
aslq $78,x
aslq $9abc,x
asrq
asrq $12
asrq $34,x
bitq $12
bitq $3456
cmp [$12],z
cmpq $12
cmpq $3456
cmpq ($78)
cmpq [$9a]
deq
deq $12
deq $3456
deq $78,x
deq $9abc,x
eor [$12],z
eorq $12
eorq $3456
eorq ($78)
eorq [$9a]
inq
inq $12
inq $3456
inq $78,x
inq $9abc,x
lda [$12],z
ldq $12
ldq $3456
ldq ($78),z
ldq [$9a],z
lsrq $12
lsrq
lsrq $3456
lsrq $78,x
lsrq $9abc,x
ora [$12],z
orq $12
orq $3456
orq ($78)
orq [$9a]
rolq $12
rolq
rolq $3456
rolq $78,x
rolq $9abc,x
rorq $12
rorq
rorq $3456
rorq $78,x
rorq $9abc,x
sbc [$12],z
sbcq $12
sbcq $3456
sbcq ($78)
sbcq [$9a]
sta [$12],z ; EA 92 12
stq $12
stq $3456
stq ($78)
stq [$9a]

6
test/asm/opcodes/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the assembler regression tests
ifneq ($(shell echo),)

BIN
test/asm/opcodes/m740-opcodes.ref Normal file
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823
test/asm/opcodes/m740-opcodes.s
View File

@@ -1,260 +1,565 @@
.setcpu "65C02"
; copy of 65c02, comments note changes to the m740 according to
; http://documentation.renesas.com/doc/products/mpumcu/rej09b0322_740sm.pdf
; da65 V2.19 - Git 89651fd8b
; Created: 2025-06-16 20:10:42
; Input file: testfile
; Page: 1
brk
ora ($12,x)
.byte $02,$00,$00 ; jsr zp,ind
.byte $03,$00,$00 ; bbs 0,a
tsb $12 ; .byte $04
ora $12
asl $12
rmb0 $12 ; bbs 0,zp
php
ora #$12
asl a
.byte $0B,$00,$00 ; seb 0,a
tsb $3456 ; .byte $0c
ora $3456
asl $3456
bbr0 $12,*+122 ; seb 0,zp
bpl *+122
ora ($12),y
ora ($12) ; clt
.byte $13,$00,$00 ; bbc 0,a
trb $12 ; .byte $14
ora $12,x
asl $12,x
rmb1 $12 ; bbc 0,zp
clc
ora $3456,y
inc a
.byte $1B,$00,$00 ; clb 0,a
trb $3456 ; .byte $1c
ora $3456,x
asl $3456,x
bbr1 $12,*+122 ; clb 0,zp
jsr $3456
and ($12,x)
.byte $22,$00,$00 ; jsr c_sp
.byte $23,$00,$00 ; bbs 1,a
bit $12
and $12
rol $12
rmb2 $12 ; bbs 1,zp
plp
and #$12
rol a
.byte $2B,$00,$00 ; seb 1,a
bit $3456
and $3456
rol $3456
bbr2 $12,*+122 ; seb 1,zp
bmi *+122
and ($12),y
and ($12) ; set
.byte $33,$00,$00 ; bbc 1,a
bit $12,x ; .byte $34
and $12,x
rol $12,x
rmb3 $12 ; bbc 1,zp
sec
and $3456,y
dec a
.byte $3B,$00,$00 ; clb 1,a
bit $3456,x ; ldm zp
and $3456,x
rol $3456,x
bbr3 $12,*+122 ; clb 1,zp
rti
eor ($12,x)
.byte $42,$00,$00 ; stp
.byte $43,$00,$00 ; bbs 2,a
.byte $44,$00,$00 ; com zp
eor $12
lsr $12
rmb4 $12 ; bbs 2,zp
pha
eor #$12
lsr a
.byte $4B,$00,$00 ; seb 2,a
jmp $3456
eor $3456
lsr $3456
bbr4 $12,*+122 ; seb 2,zp
bvc *+122
eor ($12),y
eor ($12) ; .byte $52
.byte $53,$00,$00 ; bbc 2,a
.byte $54,$00,$00
eor $12,x
lsr $12,x
rmb5 $12 ; bbc 2,zp
cli
eor $3456,y
phy
.byte $5B,$00,$00 ; clb 2,a
.byte $5C,$00,$00
eor $3456,x
lsr $3456,x
bbr5 $12,*+122 ; clb 2,zp
rts
adc ($12,x)
.byte $62,$00,$00 ; mul zp,x
.byte $63,$00,$00 ; bbs 3,a
stz $12 ; tst zp
adc $12
ror $12
rmb6 $12 ; bbs 3,zp
pla
adc #$12
ror a
.byte $6B,$00,$00 ; seb 3,a
jmp ($3456)
adc $3456
ror $3456
bbr6 $12,*+122 ; seb 3,zp
bvs *+122
adc ($12),y
adc ($12) ; .byte $72
.byte $73,$00,$00 ; bbc 3,a
stz $12,x ; .byte $74
adc $12,x
ror $12,x
rmb7 $12 ; bbc 3,zp
sei
adc $3456,y
ply
.byte $7B,$00,$00 ; clb 3,a
jmp ($3456,x) ; .byte $7c
adc $3456,x
ror $3456,x
bbr7 $12,*+122 ; clb 3,zp
bra *+122
sta ($12,x)
.byte $82,$00,$00 ; rrf zp
.byte $83,$00,$00 ; bbs 4,a
sty $12
sta $12
stx $12
smb0 $12 ; bbs 4,zp
dey
bit #$12
txa
.byte $8B,$00,$00 ; seb 4,a
sty $3456
sta $3456
stx $3456
bbs0 $12,*+122 ; seb 4,zp
bcc *+122
sta ($12),y
sta ($12) ; .byte $92
.byte $93,$00,$00 ; bbc 4,a
sty $12,x
sta $12,x
stx $12,y
smb1 $12 ; bbc 4,zp
tya
sta $3456,y
txs
.byte $9B,$00,$00 ; clb 4,a
stz $3456 ; .byte $9c
sta $3456,x
stz $3456,x ; .byte $9e
bbs1 $12,*+122 ; clb 4,zp
ldy #$12
lda ($12,x)
ldx #$12
.byte $A3,$00,$00 ; bbs 5,a
ldy $12
lda $12
ldx $12
smb2 $12 ; bbs 5,zp
tay
lda #$12
tax
.byte $AB,$00,$00 ; seb 5,a
ldy $3456
lda $3456
ldx $3456
bbs2 $12,*+122 ; seb 5,zp
bcs *+122
lda ($12),y
lda ($12) ; .byte $b2
.byte $B3,$00,$00 ; bbc 5,a
ldy $12,x
lda $12,x
ldx $12,y
smb3 $12 ; bbc 5,zp
clv
lda $3456,y
tsx
.byte $BB,$00,$00 ; clb 5,a
ldy $3456,x
lda $3456,x
ldx $3456,y
bbs3 $12,*+122 ; clb 5,zp
cpy #$12
cmp ($12,x)
.byte $C2,$00,$00 ; wit
.byte $C3,$00,$00 ; bbs 6,a
cpy $12
cmp $12
dec $12
smb4 $12 ; bbs 6,zp
iny
cmp #$12
dex
.byte $CB,$00,$00 ; seb 6,a
cpy $3456
cmp $3456
dec $3456
bbs4 $12,*+122 ; seb 6,zp
bne *+122
cmp ($12),y
cmp ($12) ; .byte $d2
.byte $D3,$00,$00 ; bbc 6,a
.byte $D4,$00,$00
cmp $12,x
dec $12,x
smb5 $12 ; bbc 6,zp
cld
cmp $3456,y
phx
.byte $DB,$00,$00 ; clb 6,a
.byte $DC,$00,$00
cmp $3456,x
dec $3456,x
bbs5 $12,*+122 ; clb 6,zp
cpx #$12
sbc ($12,x)
.byte $E2,$00,$00 ; div zp,x
.byte $E3,$00,$00 ; bbs 7,a
cpx $12
sbc $12
inc $12
smb6 $12 ; bbs 7,zp
inx
sbc #$12
nop
.byte $EB,$00,$00 ; seb 7,a
cpx $3456
sbc $3456
inc $3456
bbs6 $12,*+122 ; seb 7,zp
beq *+122
sbc ($12),y
sbc ($12) ; .byte $f2
.byte $F3,$00,$00 ; bbc 7,a
.byte $F4,$00,$00
sbc $12,x
inc $12,x
smb7 $12 ; bbc 7,zp
sed
sbc $3456,y
plx
.byte $FB,$00,$00 ; clb 7,a
.byte $FC,$00,$00
sbc $3456,x
inc $3456,x
bbs7 $12,*+122 ; clb 7,zp
.setcpu "m740"
L000C := $000C
L040C := $040C
LFF0C := $FF0C
brk
.byte $0C
.byte $04
ora (L000C,x)
.byte $04
jsr (L000C)
.byte $04
bbs0 a, L8018
.byte $04
.byte $04
.byte $0C
.byte $04
ora L000C
.byte $04
asl L000C
.byte $04
bbs0 L000C, L801C
L8018: php
.byte $0C
.byte $04
.byte $09
L801C: .byte $0C
.byte $04
asl a
.byte $0C
.byte $04
seb0 a
.byte $0C
.byte $04
.byte $0C
.byte $0C
.byte $04
ora L040C
asl L040C
seb0 L000C
.byte $04
bpl L803E
.byte $04
ora (L000C),y
.byte $04
clt
.byte $0C
.byte $04
bbc0 a, L8048
.byte $04
.byte $14
.byte $0C
L803E: .byte $04
ora L000C,x
.byte $04
asl L000C,x
.byte $04
bbc0 L000C, L804C
L8048: clc
.byte $0C
.byte $04
.byte $19
L804C: .byte $0C
.byte $04
inc a
.byte $0C
.byte $04
clb0 a
.byte $0C
.byte $04
.byte $1C
.byte $0C
.byte $04
ora L040C,x
asl L040C,x
clb0 L000C
.byte $04
jsr L040C
and (L000C,x)
.byte $04
jsr LFF0C
.byte $04
bbs1 a, L8078
.byte $04
bit L000C
.byte $04
and L000C
.byte $04
rol L000C
.byte $04
bbs1 L000C, L807C
L8078: plp
.byte $0C
.byte $04
.byte $29
L807C: .byte $0C
.byte $04
rol a
.byte $0C
.byte $04
seb1 a
.byte $0C
.byte $04
bit L040C
and L040C
rol L040C
seb1 L000C
.byte $04
bmi L809E
.byte $04
and (L000C),y
.byte $04
set
.byte $0C
.byte $04
bbc1 a, L80A8
.byte $04
.byte $34
.byte $0C
L809E: .byte $04
and L000C,x
.byte $04
rol L000C,x
.byte $04
bbc1 L000C, L80AC
L80A8: sec
.byte $0C
.byte $04
.byte $39
L80AC: .byte $0C
.byte $04
dec a
.byte $0C
.byte $04
clb1 a
.byte $0C
.byte $04
ldm L000C, #$04
and L040C,x
rol L040C,x
clb1 L000C
.byte $04
rti
.byte $0C
.byte $04
eor (L000C,x)
.byte $04
stp
.byte $0C
.byte $04
bbs2 a, L80D8
.byte $04
com L000C
.byte $04
eor L000C
.byte $04
lsr L000C
.byte $04
bbs2 L000C, L80DC
L80D8: pha
.byte $0C
.byte $04
.byte $49
L80DC: .byte $0C
.byte $04
lsr a
.byte $0C
.byte $04
seb2 a
.byte $0C
.byte $04
jmp L040C
eor L040C
lsr L040C
seb2 L000C
.byte $04
bvc L80FE
.byte $04
eor (L000C),y
.byte $04
.byte $52
.byte $0C
.byte $04
bbc2 a, L8108
.byte $04
.byte $54
.byte $0C
L80FE: .byte $04
eor L000C,x
.byte $04
lsr L000C,x
.byte $04
bbc2 L000C, L810C
L8108: cli
.byte $0C
.byte $04
.byte $59
L810C: .byte $0C
.byte $04
.byte $5A
.byte $0C
.byte $04
clb2 a
.byte $0C
.byte $04
.byte $5C
.byte $0C
.byte $04
eor L040C,x
lsr L040C,x
clb2 L000C
.byte $04
rts
.byte $0C
.byte $04
adc (L000C,x)
.byte $04
.byte $62
.byte $0C
.byte $04
bbs3 a, L8138
.byte $04
tst L000C
.byte $04
adc L000C
.byte $04
ror L000C
.byte $04
bbs3 L000C, L813C
L8138: pla
.byte $0C
.byte $04
.byte $69
L813C: .byte $0C
.byte $04
ror a
.byte $0C
.byte $04
seb3 a
.byte $0C
.byte $04
jmp (L040C)
adc L040C
ror L040C
seb3 L000C
.byte $04
bvs L815E
.byte $04
adc (L000C),y
.byte $04
.byte $72
.byte $0C
.byte $04
bbc3 a, L8168
.byte $04
.byte $74
.byte $0C
L815E: .byte $04
adc L000C,x
.byte $04
ror L000C,x
.byte $04
bbc3 L000C, L816C
L8168: sei
.byte $0C
.byte $04
.byte $79
L816C: .byte $0C
.byte $04
.byte $7A
.byte $0C
.byte $04
clb3 a
.byte $0C
.byte $04
.byte $7C
.byte $0C
.byte $04
adc L040C,x
ror L040C,x
clb3 L000C
.byte $04
bra L818E
.byte $04
sta (L000C,x)
.byte $04
rrf L000C
.byte $04
bbs4 a, L8198
.byte $04
sty L000C
L818E: .byte $04
sta L000C
.byte $04
stx L000C
.byte $04
bbs4 L000C, L819C
L8198: dey
.byte $0C
.byte $04
.byte $89
L819C: .byte $0C
.byte $04
txa
.byte $0C
.byte $04
seb4 a
.byte $0C
.byte $04
sty L040C
sta L040C
stx L040C
seb4 L000C
.byte $04
bcc L81BE
.byte $04
sta (L000C),y
.byte $04
.byte $92
.byte $0C
.byte $04
bbc4 a, L81C8
.byte $04
sty L000C,x
L81BE: .byte $04
sta L000C,x
.byte $04
stx L000C,y
.byte $04
bbc4 L000C, L81CC
L81C8: tya
.byte $0C
.byte $04
.byte $99
L81CC: .byte $0C
.byte $04
txs
.byte $0C
.byte $04
clb4 a
.byte $0C
.byte $04
.byte $9C
.byte $0C
.byte $04
sta L040C,x
.byte $9E
.byte $0C
.byte $04
clb4 L000C
.byte $04
ldy #$0C
.byte $04
lda (L000C,x)
.byte $04
ldx #$0C
.byte $04
bbs5 a, L81F8
.byte $04
ldy L000C
.byte $04
lda L000C
.byte $04
ldx L000C
.byte $04
bbs5 L000C, L81FC
L81F8: tay
.byte $0C
.byte $04
.byte $A9
L81FC: .byte $0C
.byte $04
tax
.byte $0C
.byte $04
seb5 a
.byte $0C
.byte $04
ldy L040C
lda L040C
ldx L040C
seb5 L000C
.byte $04
bcs L821E
.byte $04
lda (L000C),y
.byte $04
jmp (L000C)
.byte $04
bbc5 a, L8228
.byte $04
ldy L000C,x
L821E: .byte $04
lda L000C,x
.byte $04
ldx L000C,y
.byte $04
bbc5 L000C, L822C
L8228: clv
.byte $0C
.byte $04
.byte $B9
L822C: .byte $0C
.byte $04
tsx
.byte $0C
.byte $04
clb5 a
.byte $0C
.byte $04
ldy L040C,x
lda L040C,x
ldx L040C,y
clb5 L000C
.byte $04
cpy #$0C
.byte $04
cmp (L000C,x)
.byte $04
slw
.byte $0C
.byte $04
bbs6 a, L8258
.byte $04
cpy L000C
.byte $04
cmp L000C
.byte $04
dec L000C
.byte $04
bbs6 L000C, L825C
L8258: iny
.byte $0C
.byte $04
.byte $C9
L825C: .byte $0C
.byte $04
dex
.byte $0C
.byte $04
seb6 a
.byte $0C
.byte $04
cpy L040C
cmp L040C
dec L040C
seb6 L000C
.byte $04
bne L827E
.byte $04
cmp (L000C),y
.byte $04
.byte $D2
.byte $0C
.byte $04
bbc6 a, L8288
.byte $04
.byte $D4
.byte $0C
L827E: .byte $04
cmp L000C,x
.byte $04
dec L000C,x
.byte $04
bbc6 L000C, L828C
L8288: cld
.byte $0C
.byte $04
.byte $D9
L828C: .byte $0C
.byte $04
.byte $DA
.byte $0C
.byte $04
clb6 a
.byte $0C
.byte $04
.byte $DC
.byte $0C
.byte $04
cmp L040C,x
dec L040C,x
clb6 L000C
.byte $04
cpx #$0C
.byte $04
sbc (L000C,x)
.byte $04
fst
.byte $0C
.byte $04
bbs7 a, L82B8
.byte $04
cpx L000C
.byte $04
sbc L000C
.byte $04
inc L000C
.byte $04
bbs7 L000C, L82BC
L82B8: inx
.byte $0C
.byte $04
.byte $E9
L82BC: .byte $0C
.byte $04
nop
.byte $0C
.byte $04
seb7 a
.byte $0C
.byte $04
cpx L040C
sbc L040C
inc L040C
seb7 L000C
.byte $04
beq L82DE
.byte $04
sbc (L000C),y
.byte $04
.byte $F2
.byte $0C
.byte $04
bbc7 a, L82E8
.byte $04
.byte $F4
.byte $0C
L82DE: .byte $04
sbc L000C,x
.byte $04
inc L000C,x
.byte $04
bbc7 L000C, L82EC
L82E8: sed
.byte $0C
.byte $04
.byte $F9
L82EC: .byte $0C
.byte $04
.byte $FA
.byte $0C
.byte $04
clb7 a
.byte $0C
.byte $04
.byte $FC
.byte $0C
.byte $04
sbc L040C,x
inc L040C,x
clb7 L000C
.byte $04

6
test/asm/val/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the regression tests that return an error code on failure
ifneq ($(shell echo),)

381
test/dasm/45GS02-disass.s Normal file
View File

@@ -0,0 +1,381 @@
.setcpu "45GS02"
ZP = $12
ABS = $1234
brk
ora ($05,x)
cle
see
tsb $02
ora $02
asl $02
rmb0 $02
php
ora #$01
asl
tsy
tsb $1234
ora $1234
asl $1234
bbr0 $02, L0
L0:
bpl L0
ora ($06),y
ora ($07),z
lbpl *+$3133 ; bpl *+$3133
trb $02
ora $03,x
asl $03,x
rmb1 $02
clc
ora $1456,y
inc
inz
trb $1234
ora $1345,x
asl $1345,x
bbr1 $02,L1
L1:
jsr $1234
and ($05,x)
jsr ($2345)
jsr ($2456,x)
bit $02
and $02
rol $02
rmb2 $02
plp
and #$01
rol
tys
bit $1234
and $1234
rol $1234
bbr2 $02,L2
L2:
bmi L2
and ($06),y
and ($07),z
lbmi *+$3133 ; bmi *+$3133
bit $03,x
and $03,x
rol $03,x
rmb3 $02
sec
and $1456,y
dec
dez
bit $1345,x
and $1345,x
rol $1345,x
bbr3 $02,L3
L3:
rti
eor ($05,x)
neg
asr
asr $02
eor $02
lsr $02
rmb4 $02
pha
eor #$01
lsr
taz
jmp $1234
eor $1234
lsr $1234
bbr4 $02,L4
L4:
bvc L4
eor ($06),y
eor ($07),z
lbvc *+$3133 ; bvc *+$3133
asr $03,x
eor $03,x
lsr $03,x
rmb5 $02
cli
eor $1456,y
phy
tab
map
eor $1345,x
lsr $1345,x
bbr5 $02,L5
L5:
rts
adc ($05,x)
rtn #$09
bsr *+$3133
stz $02
adc $02
ror $02
rmb6 $02
pla
adc #$01
ror
tza
jmp ($2345)
adc $1234
ror $1234
bbr6 $02,L6
L6:
bvs L6
adc ($06),y
adc ($07),z
lbvs *+$3133 ; bvs *+$3133
stz $03,x
adc $03,x
ror $03,x
rmb7 $02
sei
adc $1456,y
ply
tba
jmp ($2456,x)
adc $1345,x
ror $1345,x
bbr7 $02,L7
L7:
bra L7
sta ($05,x)
sta ($0f,s),y
sta ($0f,sp),y
lbra *+$3133 ; bra *+$3133
sty $02
sta $02
stx $02
smb0 $02
dey
bit #$01
txa
sty $1345,x
sty $1234
sta $1234
stx $1234
bbs0 $02,L8
L8:
bcc L8
sta ($06),y
sta ($07),z
lbcc *+$3133 ; bcc *+$3133
sty $03,x
sta $03,x
stx $04,y
smb1 $02
tya
sta $1456,y
txs
stx $1456,y
stz $1234
sta $1345,x
stz $1345,x
bbs1 $02,L9
L9:
ldy #$01
lda ($05,x)
ldx #$01
ldz #$01
ldy $02
lda $02
ldx $02
smb2 $02
tay
lda #$01
tax
ldz $1234
ldy $1234
lda $1234
ldx $1234
bbs2 $02,L10
L10:
bcs L10
lda ($06),y
lda ($07),z
lbcs *+$3133 ; bcs *+$3133
ldy $03,x
lda $03,x
ldx $04,y
smb3 $02
clv
lda $1456,y
tsx
ldz $1345,x
ldy $1345,x
lda $1345,x
ldx $1456,y
bbs3 $02,L11
L11:
cpy #$01
cmp ($05,x)
cpz #$01
dew $02
cpy $02
cmp $02
dec $02
smb4 $02
iny
cmp #$01
dex
asw $1234
cpy $1234
cmp $1234
dec $1234
bbs4 $02,L12
L12:
bne L12
cmp ($06),y
cmp ($07),z
lbne *+$3133 ; bne *+$3133
cpz $02
cmp $03,x
dec $03,x
smb5 $02
cld
cmp $1456,y
phx
phz
cpz $1234
cmp $1345,x
dec $1345,x
bbs5 $02,L13
L13:
cpx #$01
sbc ($05,x)
lda ($0f,s),y
lda ($0f,sp),y
inw $02
cpx $02
sbc $02
inc $02
smb6 $02
inx
sbc #$01
eom
nop
row $1234
cpx $1234
sbc $1234
inc $1234
bbs6 $02,L14
L14:
beq L14
sbc ($06),y
sbc ($07),z
lbeq *+$3133 ; beq *+$3133
phd #$089a
phw #$089a
sbc $03,x
inc $03,x
smb7 $02
sed
sbc $1456,y
plx
plz
phd $1234
phw $1234
sbc $1345,x
inc $1345,x
bbs7 $02,L15
L15:
adc [$12],z
adcq $12
adcq $3456
adcq ($78)
adcq [$9a]
and [$12],z
andq $12
andq $3456
andq ($78)
andq [$9a]
aslq $12
aslq
aslq $3456
aslq $78,x
aslq $9abc,x
asrq
asrq $12
asrq $34,x
bitq $12
bitq $3456
cmp [$12],z
cmpq $12
cmpq $3456
cmpq ($78)
cmpq [$9a]
deq
deq $12
deq $3456
deq $78,x
deq $9abc,x
eor [$12],z
eorq $12
eorq $3456
eorq ($78)
eorq [$9a]
inq
inq $12
inq $3456
inq $78,x
inq $9abc,x
lda [$12],z
ldq $12
ldq $3456
ldq ($78),z
ldq [$9a],z
lsrq $12
lsrq
lsrq $3456
lsrq $78,x
lsrq $9abc,x
ora [$12],z
orq $12
orq $3456
orq ($78)
orq [$9a]
rolq $12
rolq
rolq $3456
rolq $78,x
rolq $9abc,x
rorq $12
rorq
rorq $3456
rorq $78,x
rorq $9abc,x
sbc [$12],z
sbcq $12
sbcq $3456
sbcq ($78)
sbcq [$9a]
sta [$12],z ; EA 92 12
stq $12
stq $3456
stq ($78)
stq [$9a]

8
test/dasm/6502-disass.s Normal file
View File

@@ -0,0 +1,8 @@
.setcpu "6502"
.repeat 256, cnt
.byte 0 + cnt, $02, $ea, $00
.endrepeat

188
test/dasm/6502DTV-disass.s Normal file
View File

@@ -0,0 +1,188 @@
.setcpu "6502DTV"
brk
ora ($12,x)
nop $12
ora $12
asl $12
php
ora #$12
asl a
anc #$12
nop $3456
ora $3456
asl $3456
bpl *+2
ora ($12),y
bra *+2
nop $12,x
ora $12,x
asl $12,x
clc
ora $3456,y
nop $3456,x
ora $3456,x
asl $3456,x
jsr $3456
and ($12,x)
rla ($12,x)
bit $12
and $12
rol $12
rla $12
plp
and #$12
rol a
bit $3456
and $3456
rol $3456
rla $3456
bmi *+2
and ($12),y
sac #$12
rla ($12),y
and $12,x
rol $12,x
rla $12,x
sec
and $3456,y
rla $3456,y
and $3456,x
rol $3456,x
rla $3456,x
rti
eor ($12,x)
sir #$12
eor $12
lsr $12
pha
eor #$12
lsr a
alr #$12
jmp $3456
eor $3456
lsr $3456
bvc *+2
eor ($12),y
eor $12,x
lsr $12,x
cli
eor $3456,x
lsr $3456,x
rts
adc ($12,x)
rra ($12,x)
adc $12
ror $12
rra $12
pla
adc #$12
ror a
arr #$12
jmp ($3456)
adc $3456
ror $3456
rra $3456
bvs *+2
adc ($12),y
rra ($12),y
adc $12,x
ror $12,x
rra $12,x
sei
adc $3456,y
rra $3456,y
adc $3456,x
ror $3456,x
rra $3456,x
nop #$12
sta ($12,x)
sty $12
sta $12
stx $12
dey
txa
sty $3456
sta $3456
stx $3456
bcc *+2
sta ($12),y
sty $12,x
sta $12,x
stx $12,y
tya
sta $3456,y
txs
shy $3456,x
sta $3456,x
shx $3456,y
ldy #$12
lda ($12,x)
ldx #$12
lax ($12,x)
ldy $12
lda $12
ldx $12
lax $12
tay
lda #$12
tax
lax #$12
ldy $3456
lda $3456
ldx $3456
lax $3456
bcs *+2
lda ($12),y
lax ($12),y
ldy $12,x
lda $12,x
ldx $12,y
lax $12,y
clv
lda $3456,y
tsx
las $3456,y
ldy $3456,x
lda $3456,x
ldx $3456,y
lax $3456,y
cpy #$12
cmp ($12,x)
cpy $12
cmp $12
dec $12
iny
cmp #$12
dex
axs #$12
cpy $3456
cmp $3456
dec $3456
bne *+2
cmp ($12),y
cmp $12,x
dec $12,x
cld
cmp $3456,y
cmp $3456,x
dec $3456,x
cpx #$12
sbc ($12,x)
cpx $12
sbc $12
inc $12
inx
sbc #$12
nop
cpx $3456
sbc $3456
inc $3456
beq *+2
sbc ($12),y
sbc $12,x
inc $12,x
sed
sbc $3456,y
sbc $3456,x
inc $3456,x

30
test/dasm/6502X-disass.s Normal file
View File

@@ -0,0 +1,30 @@
.setcpu "6502X"
.repeat 256, cnt
; generate a pattern with all opcodes. however, for the full cycle to work,
; we must take care of the "duplicate" opcodes, ie use only the favourite one.
.if ((cnt & $0f) = $02)
.byte $02 ; all JAM
.elseif ((cnt & $1f) = $1a)
.byte $ea ; all NOP
.elseif (cnt = $2b)
.byte $0b ; both ANC #imm
.elseif (cnt = $89)
.byte $80 ; both NOP #imm
.elseif (cnt = $eb)
.byte $e9 ; both SBC #imm
.elseif (cnt = $34) || (cnt = $54) || (cnt = $74) || (cnt = $d4) || (cnt = $f4)
.byte $14 ; all NOP zp, x
.elseif (cnt = $3c) || (cnt = $5c) || (cnt = $7c) || (cnt = $dc) || (cnt = $fc)
.byte $1c ; all NOP abs, x
.elseif (cnt = $44) || (cnt = $64)
.byte $04 ; all NOP zp
.else
.byte cnt
.endif
.byte $02, $ea, $00
.endrepeat

214
test/dasm/65C02-disass.s Normal file
View File

@@ -0,0 +1,214 @@
.setcpu "65C02"
brk
ora ($12,x)
tsb $12
ora $12
asl $12
rmb0 $12
php
ora #$12
asl a
tsb $3456
ora $3456
asl $3456
bbr0 $12,*+2
bpl *+2
ora ($12),y
ora ($12)
trb $12
ora $12,x
asl $12,x
rmb1 $12
clc
ora $3456,y
inc a
trb $3456
ora $3456,x
asl $3456,x
bbr1 $12,*+2
jsr $3456
and ($12,x)
bit $12
and $12
rol $12
rmb2 $12
plp
and #$12
rol a
bit $3456
and $3456
rol $3456
bbr2 $12,*+2
bmi *+2
and ($12),y
and ($12)
bit $12,x
and $12,x
rol $12,x
rmb3 $12
sec
and $3456,y
dec a
bit $3456,x
and $3456,x
rol $3456,x
bbr3 $12,*+2
rti
eor ($12,x)
eor $12
lsr $12
rmb4 $12
pha
eor #$12
lsr a
jmp $3456
eor $3456
lsr $3456
bbr4 $12,*+2
bvc *+2
eor ($12),y
eor ($12)
eor $12,x
lsr $12,x
rmb5 $12
cli
eor $3456,y
phy
eor $3456,x
lsr $3456,x
bbr5 $12,*+2
rts
adc ($12,x)
stz $12
adc $12
ror $12
rmb6 $12
pla
adc #$12
ror a
jmp ($3456)
adc $3456
ror $3456
bbr6 $12,*+2
bvs *+2
adc ($12),y
adc ($12)
stz $12,x
adc $12,x
ror $12,x
rmb7 $12
sei
adc $3456,y
ply
jmp ($3456,x)
adc $3456,x
ror $3456,x
bbr7 $12,*+2
bra *+2
sta ($12,x)
sty $12
sta $12
stx $12
smb0 $12
dey
bit #$12
txa
sty $3456
sta $3456
stx $3456
bbs0 $12,*+2
bcc *+2
sta ($12),y
sta ($12)
sty $12,x
sta $12,x
stx $12,y
smb1 $12
tya
sta $3456,y
txs
stz $3456
sta $3456,x
stz $3456,x
bbs1 $12,*+2
ldy #$12
lda ($12,x)
ldx #$12
ldy $12
lda $12
ldx $12
smb2 $12
tay
lda #$12
tax
ldy $3456
lda $3456
ldx $3456
bbs2 $12,*+2
bcs *+2
lda ($12),y
lda ($12)
ldy $12,x
lda $12,x
ldx $12,y
smb3 $12
clv
lda $3456,y
tsx
ldy $3456,x
lda $3456,x
ldx $3456,y
bbs3 $12,*+2
cpy #$12
cmp ($12,x)
cpy $12
cmp $12
dec $12
smb4 $12
iny
cmp #$12
dex
cpy $3456
cmp $3456
dec $3456
bbs4 $12,*+2
bne *+2
cmp ($12),y
cmp ($12)
cmp $12,x
dec $12,x
smb5 $12
cld
cmp $3456,y
phx
cmp $3456,x
dec $3456,x
bbs5 $12,*+2
cpx #$12
sbc ($12,x)
cpx $12
sbc $12
inc $12
smb6 $12
inx
sbc #$12
nop
cpx $3456
sbc $3456
inc $3456
bbs6 $12,*+2
beq *+2
sbc ($12),y
sbc ($12)
sbc $12,x
inc $12,x
smb7 $12
sed
sbc $3456,y
plx
sbc $3456,x
inc $3456,x
L0:
bbs7 $12,L0
nop

181
test/dasm/65SC02-disass.s Normal file
View File

@@ -0,0 +1,181 @@
.setcpu "65SC02"
brk
ora ($12,x)
tsb $12
ora $12
asl $12
php
ora #$12
asl a
tsb $3456
ora $3456
asl $3456
bpl *+2
ora ($12),y
ora ($12)
trb $12
ora $12,x
asl $12,x
clc
ora $3456,y
inc a
trb $3456
ora $3456,x
asl $3456,x
jsr $3456
and ($12,x)
bit $12
and $12
rol $12
plp
and #$12
rol a
bit $3456
and $3456
rol $3456
bmi *+2
and ($12),y
and ($12)
bit $12,x
and $12,x
rol $12,x
sec
and $3456,y
dec a
bit $3456,x
and $3456,x
rol $3456,x
rti
eor ($12,x)
eor $12
lsr $12
pha
eor #$12
lsr a
jmp $3456
eor $3456
lsr $3456
bvc *+2
eor ($12),y
eor ($12)
eor $12,x
lsr $12,x
cli
eor $3456,y
phy
eor $3456,x
lsr $3456,x
rts
adc ($12,x)
stz $12
adc $12
ror $12
pla
adc #$12
ror a
jmp ($3456)
adc $3456
ror $3456
bvs *+2
adc ($12),y
adc ($12)
stz $12,x
adc $12,x
ror $12,x
sei
adc $3456,y
ply
jmp ($3456,x)
adc $3456,x
ror $3456,x
bra *+2
sta ($12,x)
sty $12
sta $12
stx $12
dey
bit #$12
txa
sty $3456
sta $3456
stx $3456
bcc *+2
sta ($12),y
sta ($12)
sty $12,x
sta $12,x
stx $12,y
tya
sta $3456,y
txs
stz $3456
sta $3456,x
stz $3456,x
ldy #$12
lda ($12,x)
ldx #$12
ldy $12
lda $12
ldx $12
tay
lda #$12
tax
ldy $3456
lda $3456
ldx $3456
bcs *+2
lda ($12),y
lda ($12)
ldy $12,x
lda $12,x
ldx $12,y
clv
lda $3456,y
tsx
ldy $3456,x
lda $3456,x
ldx $3456,y
cpy #$12
cmp ($12,x)
cpy $12
cmp $12
dec $12
iny
cmp #$12
dex
cpy $3456
cmp $3456
dec $3456
bne *+2
cmp ($12),y
cmp ($12)
cmp $12,x
dec $12,x
cld
cmp $3456,y
phx
cmp $3456,x
dec $3456,x
cpx #$12
sbc ($12,x)
cpx $12
sbc $12
inc $12
inx
sbc #$12
nop
cpx $3456
sbc $3456
inc $3456
beq *+2
sbc ($12),y
sbc ($12)
sbc $12,x
inc $12,x
sed
sbc $3456,y
plx
sbc $3456,x
inc $3456,x

6
test/dasm/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the disassembler regression tests
ifneq ($(shell echo),)

250
test/dasm/huc6280-disass.s Normal file
View File

@@ -0,0 +1,250 @@
.setcpu "huc6280"
brk
ora ($12,x)
sxy
st0 #$12
tsb $12
ora $12
asl $12
rmb0 $12
php
ora #$12
asl a
tsb $3456
ora $3456
asl $3456
bbr0 $12,L0
L0:
bpl *+2
ora ($12),y
ora ($12)
st1 #$12
trb $12
ora $12,x
asl $12,x
rmb1 $12
clc
ora $3456,y
inc a
trb $3456
ora $3456,x
asl $3456,x
bbr1 $12,L1
L1:
jsr $3456
and ($12,x)
sax
st2 #$12
bit $12
and $12
rol $12
rmb2 $12
plp
and #$12
rol a
bit $3456
and $3456
rol $3456
bbr2 $12,L2
L2:
bmi *+2
and ($12),y
and ($12)
bit $12,x
and $12,x
rol $12,x
rmb3 $12
sec
and $3456,y
dec a
bit $3456,x
and $3456,x
rol $3456,x
bbr3 $12,L3
L3:
rti
eor ($12,x)
say
tma #$02
bsr *+2
eor $12
lsr $12
rmb4 $12
pha
eor #$12
lsr a
jmp $3456
eor $3456
lsr $3456
bbr4 $12,L4
L4:
bvc *+2
eor ($12),y
eor ($12)
tam #$12
csl
eor $12,x
lsr $12,x
rmb5 $12
cli
eor $3456,y
phy
eor $3456,x
lsr $3456,x
bbr5 $12,L5
L5:
rts
adc ($12,x)
cla
stz $12
adc $12
ror $12
rmb6 $12
pla
adc #$12
ror a
jmp ($3456)
adc $3456
ror $3456
bbr6 $12,L6
L6:
bvs *+2
adc ($12),y
adc ($12)
tii $3333,$7373,$1111
stz $12,x
adc $12,x
ror $12,x
rmb7 $12
sei
adc $3456,y
ply
jmp ($3456,x)
adc $3456,x
ror $3456,x
bbr7 $12,L7
L7:
bra *+2
sta ($12,x)
clx
tst #$12,$EA
sty $12
sta $12
stx $12
smb0 $12
dey
bit #$12
txa
sty $3456
sta $3456
stx $3456
bbs0 $12,LS0
LS0:
bcc *+2
sta ($12),y
sta ($12)
tst #$12,$EAEA
sty $12,x
sta $12,x
stx $12,y
smb1 $12
tya
sta $3456,y
txs
stz $3456
sta $3456,x
stz $3456,x
bbs1 $12,LS1
LS1:
ldy #$12
lda ($12,x)
ldx #$12
tst #$12,$EA,x
ldy $12
lda $12
ldx $12
smb2 $12
tay
lda #$12
tax
ldy $3456
lda $3456
ldx $3456
bbs2 $12,LS2
LS2:
bcs *+2
lda ($12),y
lda ($12)
tst #$12,$EAEA,x
ldy $12,x
lda $12,x
ldx $12,y
smb3 $12
clv
lda $3456,y
tsx
ldy $3456,x
lda $3456,x
ldx $3456,y
bbs3 $12,LS3
LS3:
cpy #$12
cmp ($12,x)
cly
tdd $3333,$C3C3,$1111
cpy $12
cmp $12
dec $12
smb4 $12
iny
cmp #$12
dex
cpy $3456
cmp $3456
dec $3456
bbs4 $12,LS4
LS4:
bne *+2
cmp ($12),y
cmp ($12)
tin $3333,$D3D3,$1111
cmp $12,x
dec $12,x
smb5 $12
cld
cmp $3456,y
phx
cmp $3456,x
dec $3456,x
bbs5 $12,LS5
LS5:
cpx #$12
sbc ($12,x)
tia $3333,$E3E3,$1111
cpx $12
sbc $12
inc $12
smb6 $12
inx
sbc #$12
nop
cpx $3456
sbc $3456
inc $3456
bbs6 $12,LS6
LS6:
beq *+2
sbc ($12),y
sbc ($12)
tai $3333,$F3F3,$1111
sbc $12,x
inc $12,x
smb7 $12
sed
sbc $3456,y
plx
sbc $3456,x
inc $3456,x
LS7:
bbs7 $12,LS7

8
test/dasm/m740-disass.s Normal file
View File

@@ -0,0 +1,8 @@
.setcpu "M740"
.repeat 256, cnt
.byte 0 + cnt, $12, $02, $ea
.endrepeat

9
test/dasm/readme.txt Normal file
View File

@@ -0,0 +1,9 @@
Per CPU, a test binary is produced (using the assembler), which should contain
all possible instructions. That file is then disassembled, and assembled again,
and finally the resulting binary compared with the binary produced in the first
step.
Given that we assume the assembler works (this is tested in other/previous
tests), this proves that the disassembler works, and can produce output that the
assembler will understand - and produce an identical binary from.

6
test/err/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the tests that MUST NOT compile
ifneq ($(shell echo),)

6
test/misc/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the remaining tests that need special care in one way or another
ifneq ($(shell echo),)

6
test/ref/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the regression tests that generate output which has to be
# compared with reference output

6
test/standard/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the regression tests that return an error code on failure
ifneq ($(shell echo),)

6
test/standard_err/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the tests that MUST NOT compile
ifneq ($(shell echo),)

6
test/todo/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the currently failing regression tests that return an error code on failure
ifneq ($(shell echo),)

6
test/val/Makefile
View File

@@ -1,3 +1,9 @@
# ---- Display info during parsing phase ----
SILENT:=$(findstring s,$(word 1, $(MAKEFLAGS)))
ifneq ($(SILENT),s)
$(info Using Makefile: $(realpath $(firstword $(MAKEFILE_LIST))) $(MAKECMDGOALS))
endif
# Makefile for the regression tests that return an error code on failure
ifneq ($(shell echo),)