update docs with some more info about the various cpu modes
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mrdudz
281
doc/ca65.sgml
281
doc/ca65.sgml
@@ -399,7 +399,7 @@ name="--bin-include-dir">/ option on the command line.
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<sect>Input format<p>
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<sect>Input format<p><label id="input-format">
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<sect1>Assembler syntax<p>
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@@ -426,21 +426,23 @@ Here are some examples for valid input lines:
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The assembler accepts
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<itemize>
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<item>all valid 6502 mnemonics when in 6502 mode (the default or after the
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<item>all valid 6502 mnemonics when in <ref id="6502-mode" name="6502 mode">
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(the default or after the
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<tt><ref id=".P02" name=".P02"></tt> command was given).
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<item>all valid 6502 mnemonics plus a set of illegal instructions when in
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<ref id="6502X-mode" name="6502X mode">.
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<item>all valid 6502DTV mnemonics when in 6502DTV mode (after the
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<item>all valid 6502 mnemonics, plus a set of illegal instructions, when in
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<ref id="6502X-mode" name="6502X mode"> (after the
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<tt><ref id=".P02X" name=".P02X"></tt> command was given).
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<item>all valid 6502DTV mnemonics when in <ref id="DTV-mode" name="DTV mode"> (after the
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<tt><ref id=".PDTV" name=".PDTV"></tt> command was given).
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<item>all valid 65SC02 mnemonics when in 65SC02 mode (after the
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<item>all valid 65SC02 mnemonics when in <ref id="65SC02-mode" name="65SC02 mode"> (after the
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<tt><ref id=".PSC02" name=".PSC02"></tt> command was given).
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<item>all valid 65C02 mnemonics when in 65C02 mode (after the
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<item>all valid 65C02 mnemonics when in <ref id="65C02-mode" name="65C02 mode"> (after the
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<tt><ref id=".PC02" name=".PC02"></tt> command was given).
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<item>all valid 65816 mnemonics when in 65816 mode (after the
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<item>all valid 65816 mnemonics when in <ref id="65816-mode" name="65816 mode"> (after the
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<tt><ref id=".P816" name=".P816"></tt> command was given).
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<item>all valid 4510 mnemonics when in 4510 mode (after the
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<item>all valid 4510 mnemonics when in <ref id="4510-mode" name="4510 mode"> (after the
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<tt><ref id=".P4510" name=".P4510"></tt> command was given).
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<item>all valid M740 mnemonics when in M740 mode (after the
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<item>all valid M740 mnemonics when in <ref id="M740-mode" name="M740 mode"> (after the
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<tt><ref id=".PM740" name=".PM740"></tt> command was given).
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</itemize>
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@@ -453,8 +455,206 @@ byte. If omitted, the assembler will only produce only 1 byte.
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brk #$34 ; 2-bytes: $00 $34
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</verb></tscreen>
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<sect1>6502 mode<label id="6502-mode"><p>
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<sect1>65816 mode<p>
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In 6502 mode (which is the default) the assembler accepts all regular "legal"
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6502 mnemonics and addressing modes.
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<sect1>6502X mode<label id="6502X-mode"><p>
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6502X mode is an extension to the normal 6502 mode. In this mode, several
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mnemonics for undocumented instructions of the NMOS 6502 CPUs are accepted.
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Note: Since these instructions are undocumented, there are no official mnemonics
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for them.
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<itemize>
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<item><tt>ALR: A:=(A and #{imm})/2;</tt>
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<item><tt>ANC: A:= A and #{imm};</tt> Generates opcode $0B.
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<item><tt>ANE: A:= (A or CONST) and X and #{imm};</tt>
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<item><tt>ARR: A:=(A and #{imm})/2;</tt>
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<item><tt>AXS: X:=A and X-#{imm};</tt>
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<item><tt>DCP: {addr}:={addr}-1; A-{addr};</tt>
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<item><tt>ISC: {addr}:={addr}+1; A:=A-{addr};</tt>
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<item><tt>JAM:</tt>
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<item><tt>LAS: A,X,S:={addr} and S;</tt>
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<item><tt>LAX: A,X:={addr};</tt>
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<item><tt>NOP: #{imm}; zp; zp,x; abs; abs,x</tt>
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<item><tt>RLA: {addr}:={addr}rol; A:=A and {addr};</tt>
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<item><tt>RRA: {addr}:={addr}ror; A:=A adc {addr};</tt>
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<item><tt>SAX: {addr}:=A and X;</tt>
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<item><tt>SHA: {addr}:=A and X and {addr hi +1};</tt>
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<item><tt>SHX: {addr}:=X and {addr hi +1};</tt>
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<item><tt>SHY: {addr}:=Y and {addr hi +1};</tt>
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<item><tt>SLO: {addr}:={addr}*2; A:=A or {addr};</tt>
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<item><tt>SRE: {addr}:={addr}/2; A:=A xor {addr};</tt>
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<item><tt>TAS: {addr}:=A and X and {addr hi +1}; SP:=A and X;</tt>
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</itemize>
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<sect1>DTV mode<label id="DTV-mode"><p>
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The C64DTV CPU is based on the 6510, but adds some instructions, and does not
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support all undocumented instructions.
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<itemize>
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<item><tt>bra {rel}</tt> Generates opcode $12.
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<item><tt>sac #{imm}</tt> Generates opcode $32.
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<item><tt>sir #{imm}</tt> Generates opcode $42.
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</itemize>
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Supported undocumented instructions:
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<itemize>
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<item><tt>ALR: A:=(A and #{imm})/2;</tt>
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<item><tt>ANC: A:=A and #{imm};</tt> Generates opcode $0B.
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<item><tt>ARR: A:=(A and #{imm})/2;</tt>
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<item><tt>AXS: X:=A and X-#{imm};</tt>
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<item><tt>LAS: A,X,S:={addr} and S;</tt>
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<item><tt>LAX: A,X:={addr};</tt>
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<item><tt>NOP: #{imm}; zp; zp,x; abs; abs,x</tt>
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<item><tt>RLA: {addr}:={addr}rol; A:=A and {addr};</tt>
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<item><tt>RRA: {addr}:={addr}ror; A:=A adc {addr};</tt>
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<item><tt>SHX: {addr}:=X and {addr hi +1};</tt>
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<item><tt>SHY: {addr}:=y and {addr hi +1};</tt>
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</itemize>
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<sect1>65SC02 mode<label id="65SC02-mode"><p>
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65SC02 mode supports all regular 6502 instructions, plus the following:
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<tscreen><verb>
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$04 tsb zp
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$0c tsb abs16
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$12 ora (zp)
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$14 trb zp
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$1a inc
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$1c trb abs16
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$32 and (zp)
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$34 bit zp, x
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$3a dec
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$3c bit abs16, x
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$52 eor (zp)
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$5a phy
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$64 stz zp
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$72 adc (zp)
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$74 stz zp, x
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$7a ply
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$7c jmp (abs16, x)
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$80 bra rel8
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$89 bit #imm8
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$92 sta (zp)
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$9c stz abs16
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$9e stz abs16, x
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$b2 lda (zp)
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$d2 cmp (zp)
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$da phx
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$f2 sbc (zp)
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$fa plx
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</verb></tscreen>
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<sect1>65C02 mode<label id="65C02-mode"><p>
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65C02 mode supports all "official" W65C02 opcodes.
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The R65C02 adds bit manipulation instructions:
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<tscreen><verb>
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smbB zp set bit in zp location
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rmbB zp reset bit in zp location
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bbsB zp, rel8 branch if bit is set in zp location
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bbrB zp, rel8 branch if bit is reset in zp location
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</verb></tscreen>
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And the W65C02 adds those:
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<tscreen><verb>
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$cb wai wait for interrupt
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$db stp wait for reset
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</verb></tscreen>
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<sect1>4510 mode<label id="4510-mode"><p>
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The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX.
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It contains among other functions a slightly modified 65CE02/4502 CPU, to allow
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address mapping for 20 bits of address space (1 megabyte addressable area).
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The 4510 mode supports the complete (legal) 65CE02 instruction set, plus these
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three, which were changed/added:
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<tscreen><verb>
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$5c map "4-byte NOP reserved for future expansion" on 65CE02
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$cb asw $1234 wai on W65C02
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$db phz stp on W65C02
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</verb></tscreen>
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As compared to the description of the CPU in the
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<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/c65manualupdated.txt.gz"
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name="C65 System Specification">
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<url url="https://raw.githubusercontent.com/MEGA65/c65-specifications/master/c65manualupdated.txt"
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name="(updated version)"> uses these changes:
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<itemize>
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<item><tt>LDA (d,SP),Y</tt> may also be written as <tt>LDA (d,S),Y</tt>
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(matching the 65816 notation).
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<item>All branch instruction allow now 16 bit offsets. To use a 16 bit
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branch you have to prefix these with an "L" (e.g. "<tt>LBNE</tt>" instead of
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"<tt>BNE</tt>"). This might change at a later implementation of the assembler.
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</itemize>
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For more information about the Commodore C65/C64DX and the 4510 CPU, see
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<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/"> and
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<url url="https://en.wikipedia.org/wiki/Commodore_65" name="Wikipedia">.
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<sect1>HUC6280 mode<label id="HUC6280-mode"><p>
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The HUC6280 is a superset of the R65C02. It adds some other instructions:
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<tscreen><verb>
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$02 sxy
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$03 st0 #{imm}
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$13 st1 #{imm}
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$22 sax
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$23 st2 #{imm}
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$42 say
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$43 tma #{imm}
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$44 bsr {rel}
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$53 tam #{imm}
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$54 csl
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$62 cla
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$73 tii {addr}, {addr}, {addr}
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$82 clx
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$83 tst #{imm}, {zp}
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$82 clx
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$83 tst #{imm}, {zp}
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$93 tst #{imm}, {addr}
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$a3 tst #{imm}, {zp}, x
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$b3 tst #{imm}, {addr}, x
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$c2 cly
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$c3 tdd {addr}, {addr}, {addr}
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$d3 tin {addr}, {addr}, {addr}
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$d4 csh
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$e3 tia {addr}, {addr}, {addr}
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$f3 tai {addr}, {addr}, {addr}
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$f4 set
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</verb></tscreen>
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Note that this CPU does not implement <tt>wai</tt> and <tt>stp</tt>.
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<sect1>M740 mode<label id="M740-mode"><p>
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The M740 is a microcontroller by Mitsubishi, which was marketed for embedded
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devices in the mid 80s. It is a superset of 6502, and a subset of 65SC02, plus
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some new instructions.
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For more information about the M740 Controllers, see
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<url url="https://en.wikipedia.org/wiki/Mitsubishi_740" name="Wikipedia">.
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<sect1>65816 mode<label id="65816-mode"><p><p>
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In 65816 mode, several aliases are accepted, in addition to the official
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mnemonics:
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@@ -482,64 +682,6 @@ or two far addresses whose high byte will be used.
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</verb></tscreen>
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<sect1>6502X mode<label id="6502X-mode"><p>
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6502X mode is an extension to the normal 6502 mode. In this mode, several
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mnemonics for illegal instructions of the NMOS 6502 CPUs are accepted. Since
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these instructions are illegal, there are no official mnemonics for them. The
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unofficial ones are taken from <url
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url="http://www.oxyron.de/html/opcodes02.html">. Please note that only the
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ones marked as "stable" are supported. The following table uses information
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from the mentioned web page, for more information, see there.
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<itemize>
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<item><tt>ALR: A:=(A and #{imm})/2;</tt>
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<item><tt>ANC: A:=A and #{imm};</tt> Generates opcode $0B.
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<item><tt>ARR: A:=(A and #{imm})/2;</tt>
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<item><tt>AXS: X:=A and X-#{imm};</tt>
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<item><tt>DCP: {adr}:={adr}-1; A-{adr};</tt>
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<item><tt>ISC: {adr}:={adr}+1; A:=A-{adr};</tt>
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<item><tt>LAS: A,X,S:={adr} and S;</tt>
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<item><tt>LAX: A,X:={adr};</tt>
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<item><tt>RLA: {adr}:={adr}rol; A:=A and {adr};</tt>
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<item><tt>RRA: {adr}:={adr}ror; A:=A adc {adr};</tt>
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<item><tt>SAX: {adr}:=A and X;</tt>
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<item><tt>SLO: {adr}:={adr}*2; A:=A or {adr};</tt>
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<item><tt>SRE: {adr}:={adr}/2; A:=A xor {adr};</tt>
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</itemize>
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<sect1>4510 mode<p>
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The 4510 is a microcontroller that is the core of the Commodore C65 aka C64DX.
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It contains among other functions a slightly modified 65CE02/4502 CPU, to allow
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address mapping for 20 bits of address space (1 megabyte addressable area).
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As compared to the description of the CPU in the
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<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/c65manualupdated.txt.gz"
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name="C65 System Specification">
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<url url="https://raw.githubusercontent.com/MEGA65/c65-specifications/master/c65manualupdated.txt"
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name="(updated version)"> uses these changes:
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<itemize>
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<item><tt>LDA (d,SP),Y</tt> may also be written as <tt>LDA (d,S),Y</tt>
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(matching the 65816 notataion).
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<item>All branch instruction allow now 16 bit offsets. To use a 16 bit
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branch you have to prefix these with an "L" (e.g. "<tt>LBNE</tt>" instead of
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"<tt>BNE</tt>"). This might change at a later implementation of the assembler.
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</itemize>
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For more information about the Commodore C65/C64DX and the 4510 CPU, see
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<url url="http://www.zimmers.net/anonftp/pub/cbm/c65/"> and
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<url url="https://en.wikipedia.org/wiki/Commodore_65" name="Wikipedia">.
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<sect1>M740 mode<p>
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The M740 is a microcontroller by Mitsubishi, which was marketed for embedded
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devices in the mid 80s.
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For more information about the M740 Controllers, see
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<url url="https://en.wikipedia.org/wiki/Mitsubishi_740" name="Wikipedia">.
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<sect1>sweet16 mode<label id="sweet16-mode"><p>
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SWEET 16 is an interpreter for a pseudo 16 bit CPU written by Steve Wozniak
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@@ -4851,6 +4993,7 @@ it is possible to determine if the
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instruction is supported, which is the case for the 65SC02, 65C02 and 65816
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CPUs (the latter two are upwards compatible to the 65SC02).
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see section <ref id="6502-mode" name="6502 format"> and following.
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<sect1><tt>.MACPACK module</tt><p>
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Reference in New Issue
Block a user