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Merge pull request #2707 from mrdudz/m740

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m740 Support
This commit is contained in:
Bob Andrews
2025-06-20 19:39:32 +02:00
committed by GitHub
parent 64c936317d 4f26d6d8b7
commit d333627081
19 changed files with 2100 additions and 473 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/ca65/condasm.c
View File

@@ -444,6 +444,16 @@ void DoConditionals (void)
CalcOverallIfCond ();
break;
case TOK_IFPM740:
D = AllocIf (".IFPM740", 1);
NextTok ();
if (IfCond) {
SetIfCond (D, GetCPU() == CPU_M740);
}
ExpectSep ();
CalcOverallIfCond ();
break;
case TOK_IFPSC02:
D = AllocIf (".IFPSC02", 1);
NextTok ();
@@ -500,6 +510,7 @@ int CheckConditionals (void)
case TOK_IFP816:
case TOK_IFPC02:
case TOK_IFPDTV:
case TOK_IFPM740:
case TOK_IFPSC02:
case TOK_IFREF:
DoConditionals ();

13
src/ca65/ea65.c
View File

@@ -186,10 +186,11 @@ void GetEA (EffAddr* A)
/* Remaining stuff:
**
** adr
** adr,x
** adr,y
** adr,s
** addr
** addr, x
** addr, y
** addr, s
** addr, relative addr
*/
A->Expr = Expression ();
@@ -214,7 +215,9 @@ void GetEA (EffAddr* A)
break;
default:
Error ("Syntax error");
/* FIXME: syntax error if not zp, ind */
A->AddrModeSet = AM65_ZP_REL;
break;
}

292
src/ca65/instr.c
View File

@@ -85,6 +85,12 @@ static void PutBlockTransfer (const InsDesc* Ins);
static void PutBitBranch (const InsDesc* Ins);
/* Handle 65C02 branch on bit condition */
static void PutBitBranch_m740 (const InsDesc* Ins);
/* Handle m740 branch on bit condition */
static void PutLDM_m740 (const InsDesc* Ins);
/* Handle m740 LDM instruction */
static void PutREP (const InsDesc* Ins);
/* Emit a REP instruction, track register sizes */
@@ -132,6 +138,11 @@ static void PutJSR816 (const InsDesc* Ins);
** Allowing the long_jsr_jmp_rts feature to permit a long JSR.
*/
static void PutJSR_m740 (const InsDesc* Ins);
/* Handle the JSR instruction for the m740
** Allowing the special page feature.
*/
static void PutRTS (const InsDesc* Ins attribute ((unused)));
/* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if
** the enclosing scope is FAR, but only if the long_jsr_jmp_rts feature applies.
@@ -1047,7 +1058,126 @@ static const struct {
}
};
/* CAUTION: in the pdf $1a is dec a, and $3a is inc a - if that is really the case,
* the table below (and the handler) should be fixed and this notice removed */
/* Instruction table for the m740 CPU */
static const struct {
unsigned Count;
InsDesc Ins[106];
} InsTabm740 = {
sizeof (InsTabm740.Ins) / sizeof (InsTabm740.Ins[0]),
{
/* BEGIN SORTED.SH */
{ "ADC", 0x0080A26C, 0x60, 0, PutAll },
{ "AND", 0x0080A26C, 0x20, 0, PutAll },
{ "ASL", 0x0000006e, 0x02, 1, PutAll },
{ "BBC0", 0x10000002, 0x13, 10, PutBitBranch_m740 },
{ "BBC1", 0x10000002, 0x33, 10, PutBitBranch_m740 },
{ "BBC2", 0x10000002, 0x53, 10, PutBitBranch_m740 },
{ "BBC3", 0x10000002, 0x73, 10, PutBitBranch_m740 },
{ "BBC4", 0x10000002, 0x93, 10, PutBitBranch_m740 },
{ "BBC5", 0x10000002, 0xb3, 10, PutBitBranch_m740 },
{ "BBC6", 0x10000002, 0xd3, 10, PutBitBranch_m740 },
{ "BBC7", 0x10000002, 0xf3, 10, PutBitBranch_m740 },
{ "BBS0", 0x10000002, 0x03, 10, PutBitBranch_m740 },
{ "BBS1", 0x10000002, 0x23, 10, PutBitBranch_m740 },
{ "BBS2", 0x10000002, 0x43, 10, PutBitBranch_m740 },
{ "BBS3", 0x10000002, 0x63, 10, PutBitBranch_m740 },
{ "BBS4", 0x10000002, 0x83, 10, PutBitBranch_m740 },
{ "BBS5", 0x10000002, 0xa3, 10, PutBitBranch_m740 },
{ "BBS6", 0x10000002, 0xc3, 10, PutBitBranch_m740 },
{ "BBS7", 0x10000002, 0xe3, 10, PutBitBranch_m740 },
{ "BCC", 0x00020000, 0x90, 0, PutPCRel8 },
{ "BCS", 0x00020000, 0xb0, 0, PutPCRel8 },
{ "BEQ", 0x00020000, 0xf0, 0, PutPCRel8 },
{ "BIT", 0x0000000C, 0x00, 2, PutAll },
{ "BMI", 0x00020000, 0x30, 0, PutPCRel8 },
{ "BNE", 0x00020000, 0xd0, 0, PutPCRel8 },
{ "BPL", 0x00020000, 0x10, 0, PutPCRel8 },
{ "BRA", 0x00020000, 0x80, 0, PutPCRel8 },
{ "BRK", 0x00000001, 0x00, 0, PutAll },
{ "BVC", 0x00020000, 0x50, 0, PutPCRel8 },
{ "BVS", 0x00020000, 0x70, 0, PutPCRel8 },
{ "CLB0", 0x00000006, 0x1b, 10, PutAll },
{ "CLB1", 0x00000006, 0x3b, 10, PutAll },
{ "CLB2", 0x00000006, 0x5b, 10, PutAll },
{ "CLB3", 0x00000006, 0x7b, 10, PutAll },
{ "CLB4", 0x00000006, 0x9b, 10, PutAll },
{ "CLB5", 0x00000006, 0xbb, 10, PutAll },
{ "CLB6", 0x00000006, 0xdb, 10, PutAll },
{ "CLB7", 0x00000006, 0xfb, 10, PutAll },
{ "CLC", 0x00000001, 0x18, 0, PutAll },
{ "CLD", 0x00000001, 0xd8, 0, PutAll },
{ "CLI", 0x00000001, 0x58, 0, PutAll },
{ "CLT", 0x00000001, 0x12, 0, PutAll },
{ "CLV", 0x00000001, 0xb8, 0, PutAll },
{ "CMP", 0x0080A26C, 0xc0, 0, PutAll },
{ "COM", 0x00000004, 0x44, 1, PutAll },
{ "CPX", 0x0080000C, 0xe0, 1, PutAll },
{ "CPY", 0x0080000C, 0xc0, 1, PutAll },
{ "DEC", 0x0000006F, 0x00, 3, PutAll },
{ "DEX", 0x00000001, 0xca, 0, PutAll },
{ "DEY", 0x00000001, 0x88, 0, PutAll },
{ "EOR", 0x0080A26C, 0x40, 0, PutAll },
{ "FST", 0x00000001, 0xe2, 0, PutAll },
{ "INC", 0x0000006f, 0x00, 4, PutAll },
{ "INX", 0x00000001, 0xe8, 0, PutAll },
{ "INY", 0x00000001, 0xc8, 0, PutAll },
{ "JMP", 0x00000C08, 0x00, 12, PutAll },
{ "JSR", 0x20000408, 0x00, 0, PutJSR_m740 },
{ "LDA", 0x0080A26C, 0xa0, 0, PutAll },
{ "LDM", 0x10000000, 0x3c, 0, PutLDM_m740 },
{ "LDX", 0x0080030C, 0xa2, 1, PutAll },
{ "LDY", 0x0080006C, 0xa0, 1, PutAll },
{ "LSR", 0x0000006F, 0x42, 1, PutAll },
{ "NOP", 0x00000001, 0xea, 0, PutAll },
{ "ORA", 0x0080A26C, 0x00, 0, PutAll },
{ "PHA", 0x00000001, 0x48, 0, PutAll },
{ "PHP", 0x00000001, 0x08, 0, PutAll },
{ "PLA", 0x00000001, 0x68, 0, PutAll },
{ "PLP", 0x00000001, 0x28, 0, PutAll },
{ "RMB0", 0x00000006, 0x1b, 10, PutAll },
{ "RMB1", 0x00000006, 0x3b, 10, PutAll },
{ "RMB2", 0x00000006, 0x5b, 10, PutAll },
{ "RMB3", 0x00000006, 0x7b, 10, PutAll },
{ "RMB4", 0x00000006, 0x9b, 10, PutAll },
{ "RMB5", 0x00000006, 0xbb, 10, PutAll },
{ "RMB6", 0x00000006, 0xdb, 10, PutAll },
{ "RMB7", 0x00000006, 0xfb, 10, PutAll },
{ "ROL", 0x0000006F, 0x22, 1, PutAll },
{ "ROR", 0x0000006F, 0x62, 1, PutAll },
{ "RRF", 0x00000004, 0x82, 6, PutAll },
{ "RTI", 0x00000001, 0x40, 0, PutAll },
{ "RTS", 0x00000001, 0x60, 0, PutAll },
{ "SBC", 0x0080A26C, 0xe0, 0, PutAll },
{ "SEB0", 0x00000006, 0x0b, 10, PutAll },
{ "SEB1", 0x00000006, 0x2b, 10, PutAll },
{ "SEB2", 0x00000006, 0x4b, 10, PutAll },
{ "SEB3", 0x00000006, 0x6b, 10, PutAll },
{ "SEB4", 0x00000006, 0x8b, 10, PutAll },
{ "SEB5", 0x00000006, 0xab, 10, PutAll },
{ "SEB6", 0x00000006, 0xcb, 10, PutAll },
{ "SEB7", 0x00000006, 0xeb, 10, PutAll },
{ "SEC", 0x00000001, 0x38, 0, PutAll },
{ "SED", 0x00000001, 0xf8, 0, PutAll },
{ "SEI", 0x00000001, 0x78, 0, PutAll },
{ "SET", 0x00000001, 0x32, 0, PutAll },
{ "SLW", 0x00000001, 0xC2, 0, PutAll },
{ "STA", 0x0000A26C, 0x80, 0, PutAll },
{ "STP", 0x00000001, 0x42, 0, PutAll },
{ "STX", 0x0000010c, 0x82, 1, PutAll },
{ "STY", 0x0000002c, 0x80, 1, PutAll },
{ "TAX", 0x00000001, 0xaa, 0, PutAll },
{ "TAY", 0x00000001, 0xa8, 0, PutAll },
{ "TST", 0x00000004, 0x64, 1, PutAll },
{ "TSX", 0x00000001, 0xba, 0, PutAll },
{ "TXA", 0x00000001, 0x8a, 0, PutAll },
{ "TXS", 0x00000001, 0x9a, 0, PutAll },
{ "TYA", 0x00000001, 0x98, 0, PutAll }
/* END SORTED.SH */
}
};
/* An array with instruction tables */
static const InsTable* InsTabs[CPU_COUNT] = {
@@ -1060,86 +1190,93 @@ static const InsTable* InsTabs[CPU_COUNT] = {
(const InsTable*) &InsTab65816,
(const InsTable*) &InsTabSweet16,
(const InsTable*) &InsTabHuC6280,
0, /* Mitsubishi 740 */
(const InsTable*) &InsTabm740, /* Mitsubishi 740 */
(const InsTable*) &InsTab4510,
};
const InsTable* InsTab = (const InsTable*) &InsTab6502;
/* Table to build the effective 65xx opcode from a base opcode and an
** addressing mode. (The value in the table is ORed with the base opcode)
** NOTE: each table has one entry per addressing mode!
*/
static unsigned char EATab[12][AM65I_COUNT] = {
{ /* Table 0 */
static unsigned char EATab[14][AM65I_COUNT] = {
{ /* Table 0 (sec, sed, seo, set, slw, sta, stp, tax, tay, tsx, txa, txs, tya) */
0x00, 0x00, 0x05, 0x0D, 0x0F, 0x15, 0x1D, 0x1F,
0x00, 0x19, 0x12, 0x00, 0x07, 0x11, 0x17, 0x01,
0x00, 0x00, 0x00, 0x03, 0x13, 0x09, 0x00, 0x09,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 1 */
{ /* Table 1 (rol, ror, stx, sty, tst) */
0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x80, 0x00
0x00, 0x00, 0x80, 0x00, 0x00, 0x00
},
{ /* Table 2 */
{ /* Table 2 (bit) */
0x00, 0x00, 0x24, 0x2C, 0x0F, 0x34, 0x3C, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 3 */
{ /* Table 3 (dec, dea) */
0x3A, 0x3A, 0xC6, 0xCE, 0x00, 0xD6, 0xDE, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 4 */
{ /* Table 4 (inc) */
0x1A, 0x1A, 0xE6, 0xEE, 0x00, 0xF6, 0xFE, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 5 */
{ /* Table 5 (stz) */
0x00, 0x00, 0x60, 0x98, 0x00, 0x70, 0x9E, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 6 */
{ /* Table 6 (jmp, rrf) */
0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00,
0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x90, 0x00
0x00, 0x00, 0x90, 0x00, 0x00, 0x00
},
{ /* Table 7 (Subroutine opcodes) */
{ /* Table 7 (jsr) */
0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 8 */
0x00, 0x40, 0x01, 0x41, 0x00, 0x09, 0x49, 0x00,
0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 9 */
{ /* Table 9 (dew, inw) */
0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x30, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 10 (NOPs) */
{ /* Table 10 (NOPs, clbX, sebX) */
0xea, 0x00, 0x04, 0x0c, 0x00, 0x14, 0x1c, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
0x00, 0x00, 0x00, 0x00
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
{ /* Table 11 (LAX) */
0x08, 0x08, 0x04, 0x0C, 0x00, 0x14, 0x1C, 0x00,
0x14, 0x1C, 0x00, 0x80, 0x00, 0x10, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
0x00, 0x00, 0x80, 0x00
0x00, 0x00, 0x80, 0x00, 0x00, 0x00
},
{ /* Table 12 (m740: JMP) */
0x00, 0x00, 0x00, 0x4c, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0xb2, 0x6c, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
},
};
@@ -1156,6 +1293,7 @@ static unsigned char Sweet16EATab[2][AMSW16I_COUNT] = {
};
/* Table that encodes the additional bytes for each 65xx instruction */
/* NOTE: one entry per addressing mode! */
unsigned char ExtBytes[AM65I_COUNT] = {
0, /* Implicit */
0, /* Accu */
@@ -1185,6 +1323,8 @@ unsigned char ExtBytes[AM65I_COUNT] = {
7, /* Block transfer (HuC6280) */
2, /* Absolute Indirect long */
2, /* Immidiate word */
2, /* Direct, Relative short */
1, /* Special Page */
};
/* Table that encodes the additional bytes for each SWEET16 instruction */
@@ -1361,6 +1501,20 @@ static void EmitCode (EffAddr* A)
}
static void PutLDM_m740 (const InsDesc* Ins)
{
EffAddr A;
/* Evaluate the addressing mode */
if (EvalEA (Ins, &A) == 0) {
/* An error occurred */
return;
}
Emit0 (Ins->BaseCode);
EmitByte (A.Expr);
Consume (TOK_HASH, "'#' expected");
EmitByte (Expression ());
}
static long PutImmed8 (const InsDesc* Ins)
/* Parse and emit an immediate 8 bit instruction. Return the value of the
@@ -1481,6 +1635,42 @@ static void PutBitBranch (const InsDesc* Ins)
EmitSigned (GenBranchExpr (1), 1);
}
static void PutBitBranch_m740 (const InsDesc* Ins)
/* Handle m740 branch on bit condition */
{
EffAddr A;
/* Evaluate the addressing mode used */
GetEA(&A);
/* From the possible addressing modes, remove the ones that are invalid
** for this instruction or CPU.
*/
A.AddrModeSet &= Ins->AddrMode;
/* Check if we have any adressing modes left */
if (A.AddrModeSet == 0) {
Error ("Illegal addressing mode");
return;
}
A.AddrMode = BitFind (A.AddrModeSet);
A.Opcode = Ins->BaseCode;
if (A.AddrMode == AM65I_ACCU) {
/* Accu */
Emit0 (A.Opcode);
ConsumeComma ();
EmitSigned (GenBranchExpr (2), 1);
} else if (A.AddrMode == AM65I_ZP_REL) {
/* FIXME: hacky, the comma was already consumed here */
A.Opcode += 0x04;
/* Zeropage */
Emit0 (A.Opcode);
EmitByte (A.Expr);
EmitSigned (GenBranchExpr (1), 1);
}
}
static void PutREP (const InsDesc* Ins)
@@ -1584,7 +1774,6 @@ static void PutTMAn (const InsDesc* Ins)
** an immediate argument.
*/
{
/* Emit the TMA opcode itself */
Emit0 (0x43);
/* Emit the argument, which is the opcode from the table */
@@ -1640,10 +1829,8 @@ static void PutJMP (const InsDesc* Ins)
*/
{
EffAddr A;
/* Evaluate the addressing mode used */
if (EvalEA (Ins, &A)) {
/* Check for indirect addressing */
if ((A.AddrModeBit & AM65_ABS_IND) && (CPU < CPU_65SC02) && (RelaxChecks == 0)) {
@@ -1701,6 +1888,57 @@ static void PutJSR816 (const InsDesc* Ins)
}
static void PutJSR_m740 (const InsDesc* Ins)
/* Handle a JSR instruction for m740 */
{
EffAddr A;
/* Evaluate the addressing mode used */
GetEA (&A);
/* From the possible addressing modes, remove the ones that are invalid
** for this instruction or CPU.
*/
A.AddrModeSet &= Ins->AddrMode;
/* Check if we have any adressing modes left */
if (A.AddrModeSet == 0) {
Error ("Illegal addressing mode");
return;
}
A.AddrMode = BitFind (A.AddrModeSet);
/* Build the opcode */
A.Opcode = Ins->BaseCode;
switch (A.AddrMode) {
case AM65I_DIR_IND:
A.Opcode = 0x02;
Emit1 (A.Opcode, A.Expr);
break;
case AM65I_ABS:
/* If we have an expression and it's const, get it's value */
if (A.Expr) {
long Val = -1;
if (IsConstExpr (A.Expr, &Val)) {
if ((Val & 0xff00) == 0xff00) {
/* direct page */
A.Opcode = 0x22;
Emit0 (A.Opcode);
EmitByte(GenByteExpr(A.Expr));
return;
}
}
}
A.Opcode = 0x20;
Emit2 (A.Opcode, A.Expr);
break;
default:
Internal ("Invalid Opcode 0x%02x", A.Opcode);
}
}
static void PutRTS (const InsDesc* Ins attribute ((unused)))
/* Handle the RTS instruction for the 816. In smart mode emit a RTL opcode if

88
src/ca65/instr.h
View File

@@ -58,34 +58,36 @@
** When assembling for the 6502 or 65C02, all addressing modes that are not
** available on these CPUs are removed before doing any checks.
*/
#define AM65_IMPLICIT 0x00000003UL
#define AM65_ACCU 0x00000002UL
#define AM65_DIR 0x00000004UL
#define AM65_ABS 0x00000008UL
#define AM65_ABS_LONG 0x00000010UL
#define AM65_DIR_X 0x00000020UL
#define AM65_ABS_X 0x00000040UL
#define AM65_ABS_LONG_X 0x00000080UL
#define AM65_DIR_Y 0x00000100UL
#define AM65_ABS_Y 0x00000200UL
#define AM65_DIR_IND 0x00000400UL
#define AM65_ABS_IND 0x00000800UL
#define AM65_DIR_IND_LONG 0x00001000UL
#define AM65_DIR_IND_Y 0x00002000UL
#define AM65_DIR_IND_LONG_Y 0x00004000UL
#define AM65_DIR_X_IND 0x00008000UL
#define AM65_ABS_X_IND 0x00010000UL
#define AM65_REL 0x00020000UL
#define AM65_REL_LONG 0x00040000UL
#define AM65_STACK_REL 0x00080000UL
#define AM65_STACK_REL_IND_Y 0x00100000UL
#define AM65_IMPLICIT 0x00000003UL /* IMP */
#define AM65_ACCU 0x00000002UL /* A, BIT, A */
#define AM65_DIR 0x00000004UL /* ZP, BIT, ZP */
#define AM65_ABS 0x00000008UL /* ABS */
#define AM65_ABS_LONG 0x00000010UL /* -- */
#define AM65_DIR_X 0x00000020UL /* ZP,X */
#define AM65_ABS_X 0x00000040UL /* ABS, X */
#define AM65_ABS_LONG_X 0x00000080UL /* -- */
#define AM65_DIR_Y 0x00000100UL /* ZP, Y */
#define AM65_ABS_Y 0x00000200UL /* ABS, Y */
#define AM65_DIR_IND 0x00000400UL /* (ZP IND) */
#define AM65_ABS_IND 0x00000800UL /* (IND) */
#define AM65_DIR_IND_LONG 0x00001000UL /* -- */
#define AM65_DIR_IND_Y 0x00002000UL /* IND, Y */
#define AM65_DIR_IND_LONG_Y 0x00004000UL /* -- */
#define AM65_DIR_X_IND 0x00008000UL /* IND, X */
#define AM65_ABS_X_IND 0x00010000UL /* -- */
#define AM65_REL 0x00020000UL /* REL */
#define AM65_REL_LONG 0x00040000UL /* -- */
#define AM65_STACK_REL 0x00080000UL /* SP ? */
#define AM65_STACK_REL_IND_Y 0x00100000UL /* ? */
#define AM65_IMM_ACCU 0x00200000UL
#define AM65_IMM_INDEX 0x00400000UL
#define AM65_IMM_IMPLICIT 0x00800000UL
#define AM65_BLOCKMOVE 0x01000000UL
#define AM65_BLOCKXFER 0x02000000UL
#define AM65_ABS_IND_LONG 0x04000000UL
#define AM65_IMM_IMPLICIT 0x00800000UL /* IMM */
#define AM65_BLOCKMOVE 0x01000000UL /* -- */
#define AM65_BLOCKXFER 0x02000000UL /* -- */
#define AM65_ABS_IND_LONG 0x04000000UL /* -- */
#define AM65_IMM_IMPLICIT_WORD 0x08000000UL /* PHW #$1234 (4510 only) */
#define AM65_ZP_REL 0x10000000UL /* ZP, REL (m740) */
#define AM65_SPECIAL_PAGE 0x20000000UL /* $FFxx (m740) */
/* Bitmask for all ZP operations that have correspondent ABS ops */
#define AM65_SET_ZP (AM65_DIR | AM65_DIR_X | AM65_DIR_Y | AM65_DIR_IND | AM65_DIR_X_IND)
@@ -106,11 +108,37 @@
#define AM65_ALL_IMM (AM65_IMM_ACCU | AM65_IMM_INDEX | AM65_IMM_IMPLICIT | AM65_IMM_IMPLICIT_WORD)
/* Bit numbers and count */
#define AM65I_IMM_ACCU 21
#define AM65I_IMM_INDEX 22
#define AM65I_IMM_IMPLICIT 23
#define AM65I_IMM_IMPLICIT_WORD 27
#define AM65I_COUNT 28
#define AM65I_IMPLICIT 0
#define AM65I_ACCU 1
#define AM65I_DIR 2
#define AM65I_ABS 3
#define AM65I_ABS_LONG 4
#define AM65I_DIR_X 5
#define AM65I_ABS_X 6
#define AM65I_ABS_LONG_X 7
#define AM65I_DIR_Y 8
#define AM65I_ABS_Y 9
#define AM65I_DIR_IND 10
#define AM65I_ABS_IND 11
#define AM65I_DIR_IND_LONG 12
#define AM65I_DIR_IND_Y 13
#define AM65I_DIR_IND_LONG_Y 14
#define AM65I_DIR_X_IND 15
#define AM65I_ABS_X_IND 16
#define AM65I_REL 17
#define AM65I_REL_LONG 18
#define AM65I_STACK_REL 19
#define AM65I_STACK_REL_IND_Y 20
#define AM65I_IMM_ACCU 21
#define AM65I_IMM_INDEX 22
#define AM65I_IMM_IMPLICIT 23
#define AM65I_BLOCKMOVE 24
#define AM65I_BLOCKXFER 25
#define AM65I_ABS_IND_LONG 26
#define AM65I_IMM_IMPLICIT_WORD 27
#define AM65I_ZP_REL 28
#define AM65I_SPECIAL_PAGE 29
#define AM65I_COUNT 30

12
src/ca65/pseudo.c
View File

@@ -1563,7 +1563,7 @@ static void DoP02 (void)
static void DoP02X (void)
/* Switch to 6502 CPU */
/* Switch to 6502X CPU */
{
SetCPU (CPU_6502X);
}
@@ -1602,6 +1602,14 @@ static void DoPDTV (void)
static void DoPM740 (void)
/* Switch to M740 CPU */
{
SetCPU (CPU_M740);
}
static void DoPageLength (void)
/* Set the page length for the listing */
{
@@ -2146,6 +2154,7 @@ static CtrlDesc CtrlCmdTab [] = {
{ ccKeepToken, DoConditionals }, /* .IFP816 */
{ ccKeepToken, DoConditionals }, /* .IFPC02 */
{ ccKeepToken, DoConditionals }, /* .IFPDTV */
{ ccKeepToken, DoConditionals }, /* .IFPM740 */
{ ccKeepToken, DoConditionals }, /* .IFPSC02 */
{ ccKeepToken, DoConditionals }, /* .IFREF */
{ ccNone, DoImport }, /* .IMPORT */
@@ -2182,6 +2191,7 @@ static CtrlDesc CtrlCmdTab [] = {
{ ccNone, DoUnexpected }, /* .PARAMCOUNT */
{ ccNone, DoPC02 }, /* .PSC02 */
{ ccNone, DoPDTV }, /* .PDTV */
{ ccNone, DoPM740 }, /* .PM740 */
{ ccNone, DoPopCharmap }, /* .POPCHARMAP */
{ ccNone, DoPopCPU }, /* .POPCPU */
{ ccNone, DoPopSeg }, /* .POPSEG */

2
src/ca65/scanner.c
View File

@@ -226,6 +226,7 @@ struct DotKeyword {
{ ".IFP816", TOK_IFP816 },
{ ".IFPC02", TOK_IFPC02 },
{ ".IFPDTV", TOK_IFPDTV },
{ ".IFPM740", TOK_IFPM740 },
{ ".IFPSC02", TOK_IFPSC02 },
{ ".IFREF", TOK_IFREF },
{ ".IMPORT", TOK_IMPORT },
@@ -268,6 +269,7 @@ struct DotKeyword {
{ ".PARAMCOUNT", TOK_PARAMCOUNT },
{ ".PC02", TOK_PC02 },
{ ".PDTV", TOK_PDTV },
{ ".PM740", TOK_PM740 },
{ ".POPCHARMAP", TOK_POPCHARMAP },
{ ".POPCPU", TOK_POPCPU },
{ ".POPSEG", TOK_POPSEG },

2
src/ca65/token.h
View File

@@ -198,6 +198,7 @@ typedef enum token_t {
TOK_IFP816,
TOK_IFPC02,
TOK_IFPDTV,
TOK_IFPM740,
TOK_IFPSC02,
TOK_IFREF,
TOK_IMPORT,
@@ -234,6 +235,7 @@ typedef enum token_t {
TOK_PARAMCOUNT,
TOK_PC02,
TOK_PDTV,
TOK_PM740,
TOK_POPCHARMAP,
TOK_POPCPU,
TOK_POPSEG,