2026-02-07 update

src/cpu.rs

@@ -1955,14 +1955,8 @@ pub enum DmaState {
 }
 
 impl DmaState {
-    pub fn merge(&mut self, other: DmaState) {
-        if matches!(other, DmaState::Running { .. }) {
-            if matches!(self, DmaState::Running { .. }) {
-                panic!("Merging incompatible dma states");
-            } else {
-                *self = other;
-            }
-        }
+    pub fn reset(&mut self) {
+        *self = Self::Passive;
     }
 
     pub fn cycle(self, mem: &mut CpuMem<'_>, cpu: &mut Cpu) -> Option<Self> {
@@ -1996,7 +1990,8 @@ impl DmaState {
                 rem,
                 read: None,
             } => {
-                if cpu.cycle % 2 != 1 {
+                if cpu.cycle % 2 == 0 {
+                    writeln!(&mut cpu.debug_log, "DMA: Waiting for cycle").unwrap();
                     return Some(self);
                 }
                 let read = mem.read(cpu_addr);