Major work

src/mem.rs

@@ -1,4 +1,4 @@
-use crate::hex_view::Memory;
+use crate::{hex_view::Memory, ppu::PPUMMRegisters};
 
 pub enum Value<'a, R> {
     Value(u8),
@@ -71,7 +71,10 @@ pub struct MemoryMap<R> {
 
 impl<R> MemoryMap<R> {
     pub fn new(segments: Vec<Segment<R>>) -> Self {
-        Self { edit_ver: 0, segments }
+        Self {
+            edit_ver: 0,
+            segments,
+        }
     }
     pub fn read(&self, addr: u16) -> Value<'_, R> {
         // self.edit_ver += 1;
@@ -88,12 +91,13 @@ impl<R> MemoryMap<R> {
                         let offset = addr - segment.position;
                         let s = &self.segments[*index];
                         self.read(s.position + offset % s.size)
-                    }
-                    // Data::Disabled() => todo!(),
+                    } // Data::Disabled() => todo!(),
                 };
             }
         }
-        todo!("Open bus")
+        // TODO: Open bus
+        Value::Value(0)
+        // todo!("Open bus")
     }
 
     pub fn write(&mut self, addr: u16, val: u8, reg_fn: impl FnOnce(&R, u16, u8)) {
@@ -111,8 +115,7 @@ impl<R> MemoryMap<R> {
                         let index = *index;
                         let s = &self.segments[index];
                         self.write(s.position + offset % s.size, val, reg_fn)
-                    }
-                    // Data::Disabled() => todo!(),
+                    } // Data::Disabled() => todo!(),
                 };
             }
         }
@@ -129,12 +132,50 @@ impl<R> MemoryMap<R> {
     }
 
     pub(crate) fn rom(&self, idx: usize) -> Option<&[u8]> {
-        if let Some(Segment { mem: Data::ROM(val), .. }) = self.segments.get(idx) {
+        if let Some(Segment {
+            mem: Data::ROM(val),
+            ..
+        }) = self.segments.get(idx)
+        {
             Some(val)
         } else {
             None
         }
     }
+
+    pub(crate) fn rom_or_ram(&self, idx: usize) -> Option<&[u8]> {
+        if let Some(Segment {
+            mem: Data::ROM(val),
+            ..
+        }) = self.segments.get(idx)
+        {
+            Some(val)
+        } else if let Some(Segment {
+            mem: Data::RAM(_), ..
+        }) = self.segments.get(idx)
+        {
+            Some(&[])
+        } else {
+            None
+        }
+    }
+
+    // pub fn with_peek_reg<'s>(&'s self, f: impl (Fn(&R, u16) -> Option<u8>) + 's) -> impl Memory + 's {
+    //     struct MemImpl<'a, R>(&'a MemoryMap<R>, Box<dyn Fn(&R, u16) -> Option<u8> + 'a>);
+    //     impl<R> Memory for MemImpl<'_, R> {
+    //         fn peek(&self, val: u16) -> Option<u8> {
+    //             match self.0.read(val) {
+    //                 Value::Value(v) => Some(v),
+    //                 Value::Register { reg, offset } => self.1(reg, offset),
+    //             }
+    //         }
+
+    //         fn edit_ver(&self) -> usize {
+    //             self.0.edit_ver()
+    //         }
+    //     }
+    //     MemImpl(self, Box::new(f))
+    // }
 }
 
 impl<R> Memory for MemoryMap<R> {
@@ -149,8 +190,7 @@ impl<R> Memory for MemoryMap<R> {
                         let offset = addr - segment.position;
                         let s = &self.segments[*index];
                         self.peek(s.position + offset % s.size)
-                    }
-                    // Data::Disabled() => todo!(),
+                    } // Data::Disabled() => todo!(),
                 };
             }
         }
@@ -161,3 +201,50 @@ impl<R> Memory for MemoryMap<R> {
         self.edit_ver
     }
 }
+
+#[derive(Clone, Copy, PartialEq, Eq)]
+pub struct Mapper {
+    horizontal_name_table: bool,
+}
+
+impl Mapper {
+    pub fn from_flags(flags: u8) -> Self {
+        if flags & 0b11111110 != 0 {
+            todo!("Support other mapper flags");
+        }
+        Self {
+            horizontal_name_table: flags & (1 << 0) == 1,
+        }
+    }
+
+    pub(crate) fn ppu_map(&self, rom: &[u8]) -> MemoryMap<PPUMMRegisters> {
+        let chr = if rom.len() == 0 {
+            Segment::ram("CHR RAM", 0x0000, 0x2000)
+        } else {
+            Segment::rom("CHR ROM", 0x0000, rom)
+        };
+        if self.horizontal_name_table {
+            MemoryMap::new(vec![
+                chr,
+                Segment::ram("Internal VRAM", 0x2000, 0x400),
+                Segment::ram("Internal VRAM", 0x2400, 0x400),
+                Segment::mirror("Internal VRAM", 0x2800, 0x400, 1),
+                Segment::mirror("Internal VRAM", 0x2C00, 0x400, 2),
+                Segment::mirror("Mirror of VRAM", 0x3000, 0x0F00, 1),
+                Segment::reg("Palette Control", 0x3F00, 0x0020, PPUMMRegisters::Palette),
+                Segment::mirror("Mirror of Palette", 0x3F20, 0x00E0, 6),
+            ])
+        } else {
+            MemoryMap::new(vec![
+                chr,
+                Segment::ram("Internal VRAM", 0x2000, 0x400),
+                Segment::mirror("Internal VRAM", 0x2400, 0x400, 1),
+                Segment::ram("Internal VRAM", 0x2800, 0x400),
+                Segment::mirror("Internal VRAM", 0x2C00, 0x400, 3),
+                Segment::mirror("Mirror of VRAM", 0x3000, 0x0F00, 1),
+                Segment::reg("Palette Control", 0x3F00, 0x0020, PPUMMRegisters::Palette),
+                Segment::mirror("Mirror of Palette", 0x3F20, 0x00E0, 6),
+            ])
+        }
+    }
+}