Finally find (& fix) bug in BIT instructions
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Cargo Build & Test / Rust project - latest (stable) (push) Failing after 26s

- BIT not longer ANDs the A register
- I now a pretty good debug view for debugging the CPU
- I wrote a number_input element for iced
- I upgraded to iced 0.14
- I added images for play and pause
- The debug log now displays in the debug view
This commit is contained in:
2025-12-14 13:10:57 -06:00
parent fecef26e2f
commit af770d232c
14 changed files with 2325 additions and 1330 deletions

View File

@@ -54,9 +54,10 @@ rom_test!(basic_init_0, "basic_init_0.nes", |nes| {
});
rom_test!(basic_init_1, "basic_init_1.nes", |nes| {
assert_eq!(nes.last_instruction, "0x8017 HLT :2 []");
assert_eq!(nes.cycle, 41);
assert_eq!(nes.cpu.pc, 0x8018);
assert_eq!(nes.last_instruction, "0x801C HLT :2 []");
assert_eq!(nes.cycle, 27403);
assert_eq!(nes.ppu.pixel, 30);
assert_eq!(nes.cpu.pc, 0x801D);
assert_eq!(nes.cpu.sp, 0xFF);
assert_eq!(nes.cpu.a, 0x00);
assert_eq!(nes.cpu.x, 0x00);