148ab2004d
Minor refactors and bug fixes
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Cargo Build & Test / Rust project - latest (stable) (push) Has been cancelled
- Bit instruction now sets Z flag correctly
- DMA is no longer handled by cpu.rs
2026-01-26 01:21:37 -06:00
f861f75b21
Major refactor
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- CPU is now it's own module
- Memory object is now shared to support mapper chips
- ROM is now stored as `Arc<[u8]>` to support mapper chips
2026-01-24 03:38:42 -06:00
42c3af28b4
Add run to address to debugger
2026-01-19 17:28:52 -06:00
cd3de5e361
Major work
Cargo Build & Test / Rust project - latest (stable) (push) Failing after 10s
2026-01-19 01:36:58 -06:00
c535e4e76d
Add new testcases with cc65 support
Cargo Build & Test / Rust project - latest (stable) (push) Failing after 8s
2025-12-22 02:13:10 -06:00
ce4532bcdf
Complete initial tests for startup
Cargo Build & Test / Rust project - latest (stable) (push) Failing after 8s
2025-12-14 14:44:54 -06:00
af770d232c
Finally find (& fix) bug in BIT instructions
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Cargo Build & Test / Rust project - latest (stable) (push) Failing after 26s
- BIT not longer ANDs the A register
- I now a pretty good debug view for debugging the CPU
- I wrote a number_input element for iced
- I upgraded to iced 0.14
- I added images for play and pause
- The debug log now displays in the debug view
2025-12-14 13:10:57 -06:00
