5 Commits

Author	SHA1	Message	Date
Matthew Pomes	22c586f15a	2026-02-07 update	2026-02-07 04:52:13 -06:00
Matthew Pomes	f861f75b21	Major refactor ... - CPU is now it's own module - Memory object is now shared to support mapper chips - ROM is now stored as `Arc<[u8]>` to support mapper chips	2026-01-24 03:38:42 -06:00
Matthew Pomes	5c3d537cfd	Update before heading home	2025-12-19 20:38:47 -06:00
Matthew Pomes	af770d232c	Finally find (& fix) bug in BIT instructions ... - BIT not longer ANDs the A register - I now a pretty good debug view for debugging the CPU - I wrote a number_input element for iced - I upgraded to iced 0.14 - I added images for play and pause - The debug log now displays in the debug view	2025-12-14 13:10:57 -06:00
Matthew Pomes	d97a8559ec	Initial commit	2025-12-07 11:34:37 -06:00